CN100351802C - Method and system for obtaining hardware information - Google Patents
Method and system for obtaining hardware information Download PDFInfo
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- CN100351802C CN100351802C CNB2005100514133A CN200510051413A CN100351802C CN 100351802 C CN100351802 C CN 100351802C CN B2005100514133 A CNB2005100514133 A CN B2005100514133A CN 200510051413 A CN200510051413 A CN 200510051413A CN 100351802 C CN100351802 C CN 100351802C
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Abstract
The present invention discloses a method for obtaining hardware information, which comprises the steps: the hardware information is connected to an interface bus of a central processing unit by a bus driving device; the hardware information is output by the bus driving device when the hardware information needs to be read; the hardware information is read by the interface bus of the central processing unit. The present invention also discloses a system for obtaining hardware information, which comprises a central processing unit, a plurality of hardware information units, at least one bus driving device and a control unit, wherein the control unit enables the hardware information to be output by the bus driving device to the interface bus of the central processing unit. The present invention saves pipe foot resources of a logic device and is convenient for design and integration of the system.
Description
Technical field
The present invention relates to electronic technology field, be specifically related to a kind of method and system of obtaining hardware information.Background technology
In electronic product, often can use the information of some hardware, such as: the version of hardware, the version of main devices, information etc.Usually, flexible and convenient for what design, I/O (I/O) pin of use programmable logic device (PLD) (as: complex programmable logic device (CPLD)) utilizes resistance that corresponding information is represented in drop-down processing on these I/O pins, as shown in Figure 1.CPU (CPU (central processing unit)) thus obtain relevant hardware information by the register that processor interface visits programmable logic device (PLD).When hardware information need be changed, only need to revise the corresponding pull down resistor of going up and get final product.
For example, the memory chip in certain system can dispose different capacity, is respectively 64MByte, 128MByte, 256MByte, 512MByte.As shown in Figure 2, in configuration different capabilities memory chip, revise 2 I/O pin I/O1 of programmable logic device (PLD) outside and the last pull down resistor of I/O2: R1, R2, R3, R4, wherein, the concrete memory span information that 2 I/O pin I/O1 and I/O2 represent is as shown in table 1 below:
Table 1:
| I/O1 | I/O2 | Memory | Implementation method | |
| 0 | 0 | 64MByte | Welding R3, R4 do not weld R1, R2 | |
| 0 | 1 | 128MByte | Welding R1, R3 do not weld R2, R4 | |
| 1 | 0 | 256MByte | Welding R2, R4 do not weld R1, R3 |
| 1 | 1 | 512MByte | Welding R1, R2 do not weld R3, R4 |
Like this, CPU just can obtain this information easily by the register of programmable logic device (PLD).
Though but this hardware information obtain manner is simple, but need take the I/O pin resource of a large amount of programmable logic device (PLD), especially at the hardware information of needs more for a long time, the resource of the logical device I/O pin that need take can be a lot, cause the waste of resource, the not enough situation of I/O pin perhaps occurs, and be unfavorable for the design of product and integrated.
Summary of the invention
The purpose of this invention is to provide a kind of method of obtaining hardware information, represent the mode of hardware information to overcome the I/O pin that utilizes programmable logic device (PLD) in the prior art, it is more to take I/O pin resource, causes the shortcoming of the pin wasting of resources.
Another object of the present invention provides a kind of system that obtains hardware information, to make things convenient for system design and integrated.
Technical scheme provided by the invention is as follows:
A kind of method of obtaining hardware information, described method comprises:
A, the hardware information unit is connected on the cpu interface bus by the bus driver device;
B, when needs read the hardware information of described hardware information unit, enable the output of described bus driver device;
C, read described hardware information by described cpu interface bus.
Described step B is specially: be changed to effectively by the control signal that enables of programmable logic device (PLD) with described bus driver device.
Alternatively, described programmable logic device (PLD) is: discreet logic device or simple programmable logical device SPLD or complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
Described step B is specially: be changed to effectively by the control signal that enables of fixed logic device with described bus driver device.
Alternatively, described bus driver device is one or more.
Especially, described hardware information is represented by pull-up resistor and/or pull down resistor.
Described method also comprises:
When not needing to read described hardware information, forbid the output of described bus driver device.
A kind of system that obtains hardware information comprises: CPU (central processing unit), and a plurality of hardware informations unit also comprises:
At least one bus driver device, link to each other with described CPU (central processing unit) by described cpu interface bus, link to each other with described hardware information unit respectively by level signal, be used for the hardware information of described hardware information unit is outputed to described cpu interface bus.
Control module links to each other with described CPU (central processing unit) by described cpu interface bus, is used to control the output of described bus driver device.
Alternatively, described control module is specially: programmable logic device (PLD) or fixed logic device.
By above technical scheme provided by the invention as can be seen, the hardware information that the present invention need obtain CPU, promptly go up pull down resistor, all be directly connected on the bus of processor interface by the bus driver device, programmable logic device (PLD) only need provide the enable signal that the bus driver device is controlled, can obtain relevant hardware information by bus, not need to take the I/O pin of a large amount of programmable logic device (PLD), significantly reduce the occupancy of logic pin.When the hardware information of needs increases, only need to increase the bus driver device and enable control signal accordingly to get final product, help the design and the expansion of system.
Description of drawings
Fig. 1 utilizes the I/O pin of logical device to represent the theory diagram of hardware information unit in the prior art;
Fig. 2 is the application example of the principle of expression hardware information shown in Figure 1 unit;
Fig. 3 is the realization flow figure of the inventive method;
Fig. 4 is the annexation synoptic diagram of hardware information unit and bus driver device in the inventive method;
Fig. 5 is a system principle diagram of the present invention;
Fig. 6 is the system of the present invention first embodiment theory diagram;
Fig. 7 is the first application example block diagram of system of the present invention;
Fig. 8 is the system of the present invention second embodiment theory diagram;
Fig. 9 is the second application example block diagram of system of the present invention.
Embodiment
Core of the present invention is by the bus driver device the hardware information unit of the equipment form with register, be connected on the interface bus of processor, and for providing, the bus driver device enables control signal by control module, in the time of need reading hardware information, it is effective that setting enables control signal, then corresponding external hardware information is sent on the bus, and CPU can be known relevant hardware information by the data that read on the bus
In order to make those skilled in the art person understand the present invention program better, the present invention is described in further detail below in conjunction with drawings and embodiments.
Realization flow with reference to the inventive method shown in Figure 3 may further comprise the steps:
Step 301: the hardware information unit is connected on the cpu i/f bus by the bus driver device.
Hardware information is represented by the upper and lower resistance that draws.Can be with reference to shown in Figure 4:
Suppose to have four kinds of hardware informations to need expression, then link to each other with IN2 with the input pin IN1 of bus driver device S4 by upper and lower resistance R 41, resistance R 42, resistance R 43 and the resistance R 44 of drawing, for CPU, remain by processor interface and obtain hardware information with the form of register, the concrete memory span information of two input pin IN1 and IN2 representative is as shown in table 2 below:
Table 2:
| IN1 | IN2 | Memory | Implementation method | |
| 0 | 0 | 64MByte | Welding R43, R44 do not weld R41, R42 |
| 0 | 1 | 128MByte | Welding R41, R43 do not weld R42, R44 |
| 1 | 0 | 256MByte | Welding R42, R44 do not weld R41, R43 |
| 1 | 1 | 512MByte | Welding R41, R42 do not weld R43, R44 |
Step 302: when needs read hardware information, enable the output of bus driver device.
For fear of bus collision, need the bus driver device to have the output enable control end, by it being enabled enabling or forbidding of control end, thereby guarantee only when needs read hardware information, it is effective just to make it enable control end, and at this moment, hardware information is then exported on the cpu i/f bus; Otherwise in other cases, it is invalid to make it enable control end, and at this moment, the bus driver device is output as high resistant.
Can be changed to effectively by the enable control signal of programmable logic device (PLD) the bus driver device, such as, discreet logic device or simple programmable logical device SPLD or complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
Can also be changed to effectively by the enable control signal of fixed logic device the bus driver device.
Step 303: read hardware information by the cpu i/f bus.
Still with reference to the hardware information shown in the above-mentioned table 2:
When the data that read by the cpu i/f bus were 0, the capacity of then representing storer was 64Mbyte; When the data that read were 1, the capacity of then representing storer was 128Mbyte; When the data that read were 2, the capacity of then representing storer was 256Mbyte; When the data that read were 3, the capacity of then representing storer was 512Mbyte.
When hardware information more after a little while, a plurality of information can be used the output of same bus driver device; When hardware information more for a long time, can using independently respectively, the bus driver device drives, at this moment, the different control that enables only need be provided, promptly in the time need reading the hardware information of certain bus driver device driving, enable the output of this bus driver device, forbid other bus driver device output simultaneously.Like this, just can guarantee to obtain more hardware information, and not need as increasing the I/O pin that takies a large amount of programmable logic device (PLD) in the prior art.
With reference to Fig. 5, Fig. 5 is a system principle diagram of the present invention:
This system comprises: CPU (central processing unit) S51, control module S52, bus driver device S53 and a plurality of hardware information: hardware information cell S 01, hardware information cell S 02 are to hardware information cell S ON.
Wherein, control module links to each other with CPU (central processing unit) by CPU (CPU (central processing unit)) interface bus respectively with the bus driver device, and control module enables control signal for the bus driver device provides, with the output of control bus driving element.
The different hardware message unit links to each other by the input end of level signal with the bus driver device respectively, so that the hardware information in the hardware information unit is outputed on the cpu i/f bus by the bus driver device.
Control module can pass through the fixed logic device, realize such as ASIC (special IC), also can realize by programmable logic device (PLD), such as, discreet logic device, SPLD (simple programmable logical device), CPLD (CPLD), FPGA (field programmable gate array) etc.Can select according to the actual design needs.
When CPU initiates to read the hardware information operation, will enable control signal by control module and be changed to effectively, this moment, relevant hardware information was sent on the cpu bus; When not needing to read hardware information, will enable control signal by control module and be changed to invalidly, at this moment, the bus driver device is output as high resistant, thereby has avoided the conflict of bus.
When hardware information more after a little while, a plurality of hardware informations can be merged and use a bus driver device, the system of the present invention as shown in Figure 6 first embodiment theory diagram:
When CPU read the version information register, EN1 was effective for the control enable signal, and the 8bit version information appears on the data line.When CPU read the memory span information register, EN2 was effective for the control enable signal, and the memory span information of 8bit appears on the data line.
Fig. 7 is the first application example block diagram of system of the present invention:
If hardware information is less, then can use a bus driver device, as the bus driver device 74LVTH245 of 8bit width.Several hardware informations are merged the bus of using this 8bit, as: the hardware version information of 2bit, the CPU version information of 3bit, the memory span information of 3bit.CPU adopts MPC860, and control module adopts CPLD LC4128V.Hardware information is connected the input A[0:7 of bus driver device] on the pin, output pin B[0:7] then be connected the interface data bus D[0:7 of CPU] on.By the output enable that control module provides enable signal OE to come the control bus driving element, when the enable signal of bus driver device was effective, these three hardware informations appeared on the interface bus together, thereby are obtained by CPU in the lump.
When hardware information more for a long time, can use a plurality of bus driver devices, the system of the present invention as shown in Figure 8 second embodiment theory diagram:
Programmable logic device (PLD) only need be exported and enable control signal separately accordingly and control, and does not take a large amount of IO pins and do not need to increase.Like this, significantly reduced the occupancy of logic pin,, only needed increase to enable control signal accordingly and get final product along with the increase of hardware information.
Fig. 9 is the second application example block diagram of system of the present invention:
When hardware information more for a long time, can use bus driver device 74LVTH16245, this device is the width of 16bit, is divided into 2 passages, each passage is the width of 8bit, have 2 Enable Pin/1OE and/2OE controls.The output of two passages all is connected cpu i/f data bus D[0:7] on, by control signal OE1, the OE2 of control module output, CPU can read this 2 hardware informations that passage connected respectively.If hardware information needs expansion, can increase the quantity of driving element or use the more driving element of long number (as the 32bit width), the output of control module simultaneously increases corresponding enable signal and gets final product.
As seen, only need to provide the enable signal that the bus driver device is controlled by the present invention by programmable logic device (PLD), can obtain relevant hardware information by bus, do not need to take the I/O pin of a large amount of programmable logic device (PLD), save logic pin resource greatly, made things convenient for the design of system.
Though described the present invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wish that appended claim comprises these distortion and variation and do not break away from spirit of the present invention.
Claims (10)
1, a kind of method of obtaining hardware information is characterized in that, described method comprises:
A, the hardware information unit is connected on the cpu interface bus by the bus driver device;
B, when needs read the hardware information of described hardware information unit, enable the output of described bus driver device;
C, read described hardware information by described cpu interface bus.
2, the method for obtaining hardware information according to claim 1 is characterized in that, described step B is specially: be changed to effectively by the control signal that enables of programmable logic device (PLD) with described bus driver device.
3, the method for obtaining hardware information according to claim 2, it is characterized in that described programmable logic device (PLD) is: discreet logic device or simple programmable logical device SPLD or complex programmable logic device (CPLD) or on-site programmable gate array FPGA.
4, the method for obtaining hardware information according to claim 1 is characterized in that, described step B is specially: be changed to effectively by the control signal that enables of fixed logic device with described bus driver device.
5, the method for obtaining hardware information according to claim 1 is characterized in that, described bus driver device is one or more.
6, the method for obtaining hardware information according to claim 1 is characterized in that, described hardware information is represented by pull-up resistor and/or pull down resistor.
7, the method for obtaining hardware information according to claim 1 is characterized in that, described method also comprises:
When not needing to read described hardware information, forbid the output of described bus driver device.
8, a kind of system that obtains hardware information comprises: CPU (central processing unit), and a plurality of hardware informations unit is characterized in that, also comprises:
At least one bus driver device, link to each other with described CPU (central processing unit) by described cpu interface bus, link to each other with described hardware information unit respectively by level signal, be used for the hardware information of described hardware information unit is outputed to described cpu interface bus;
Control module links to each other with described CPU (central processing unit) by described cpu interface bus, is used to control the output of described bus driver device.
9, the system that obtains hardware information according to claim 8 is characterized in that, described control module is specially: programmable logic device (PLD).
10, the system that obtains hardware information according to claim 8 is characterized in that, described control module is specially: the fixed logic device.
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| CNB2005100514133A CN100351802C (en) | 2005-03-02 | 2005-03-02 | Method and system for obtaining hardware information |
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| CNB2005100514133A CN100351802C (en) | 2005-03-02 | 2005-03-02 | Method and system for obtaining hardware information |
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| CN100351802C true CN100351802C (en) | 2007-11-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107533433A (en) * | 2015-04-16 | 2018-01-02 | 时间防御系统有限责任公司 | System and method for the Autonomous test of rear making external hardware annex |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101739257A (en) * | 2009-12-10 | 2010-06-16 | 中兴通讯股份有限公司 | Method and device for identifying and outputting information of mobile terminal component |
| CN103368916A (en) * | 2012-04-01 | 2013-10-23 | 百度在线网络技术（北京）有限公司 | Technology for generating trusted identity certification of computer terminal based on hardware information |
| CN103677672A (en) * | 2013-12-13 | 2014-03-26 | 中国航空工业集团公司第六三一研究所 | Method for achieving electronization of complex avionic device configuration information |
| CN103699339A (en) * | 2013-12-13 | 2014-04-02 | 中国航空工业集团公司第六三一研究所 | Device for electronizing complex avionic equipment configuration information |
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| CN1477529A (en) * | 2002-08-22 | 2004-02-25 | 联想(北京)有限公司 | Device for obtaining computer hardware information and method |
| US6725311B1 (en) * | 2000-09-14 | 2004-04-20 | Microsoft Corporation | Method and apparatus for providing a connection-oriented network over a serial bus |
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| CN86100445A (en) * | 1985-08-15 | 1987-02-11 | 米特尔公司 | Dynamic memory refresh and parity checker |
| US6453470B1 (en) * | 1999-09-30 | 2002-09-17 | General Instruments Corporation | Dynamic detection of hardware configuration in a digital terminal |
| US6725311B1 (en) * | 2000-09-14 | 2004-04-20 | Microsoft Corporation | Method and apparatus for providing a connection-oriented network over a serial bus |
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