CN100350572C

CN100350572C - Passivation method of semiconductor components

Info

Publication number: CN100350572C
Application number: CNB2003101027342A
Authority: CN
Inventors: 蔡耀铭; 张世昌; 邓德华; 王士宾
Original assignee: Toppoly Optoelectronics Corp
Current assignee: TPO Displays Corp
Priority date: 2003-10-22
Filing date: 2003-10-22
Publication date: 2007-11-21
Anticipated expiration: 2023-10-22
Also published as: CN1610074A

Abstract

The present invention discloses a passivation method aiming at a semiconductor element provided with at least two transistors (such as a PMOS transistor and an NMOS transistor) of different types. The semiconductor element is put into a pressurized and closed reaction chamber, and at least two passivation gases are led into the reaction chamber. Because one of the gases is suitable for passivating the PMOS transistor and the other gas is suitable for passivating the NMOS transistor by selecting proper passivation gases, the method of the present invention can obtain good passivation effect of the PMOS transistor and the NMOS transistor.

Description

The semiconductor element passivating method

Invention field

The present invention relates to a kind of semiconductor element passivation (passivating) method, the defective that its function is produced in order to repair technology in earlier stage in semiconductor element.

Background technology

In semiconductor element (for example CMOS (Complementary Metal Oxide Semiconductor) (CMOS)), use silicon to be widely known by the people.Semiconductor element generally is formed at P channel metal-oxide semiconductor (PMOS) transistor AND gate N channel metal-oxide semiconductor (NMOS) transistor on the same substrate via a plurality of steps, annealing (annealing) step that these steps may comprise sputter-deposited, photoetching, Wet-type etching, plasma etching, chemical vapour deposition (CVD), plasma auxiliary chemical vapor deposition, ion injection and inject ion in order to activation and driving.The meeting that has in these processing steps produces defective in semiconductor element.For example plasma etching can cause silicon dangling bonds (silicon dangling bond), and this silicon dangling bonds can further cause electron mobility (electron mobility) to descend, make semiconductor element usefulness reduce, and the ion injection also may cause damage to silicon crystalline structure.

Recently develop a kind of high pressure annealing (high pressure annealing) technology and reduced the problem that the silicon scission of link is caused.In high pressure annealing technology, semiconductor element is generally handled with single gases at high pressure (for example hydrogen or ammonia).When it is generally acknowledged scission of link (broken bonds) formation bond, can remove the aforementioned defective that produces when hydrogen and silicon.Yet owing to source electrode and the different types of impurity of drain electrode doping of PMOS and NMOS, so different reaction mechanisms is arranged in high pressure annealing technology, the high pressure annealing technological parameter optimization that therefore will make cmos element is quite difficult thing.In addition, also be not easy the anneal gas that finds PMOS and NMOS all suitable.

Summary of the invention

The purpose of this invention is to provide semiconductor element passivation (passivating) method of an improvement, can overcome or improve the aforementioned prior art problem.

For reaching above-mentioned and other purpose, semiconductor element with two kinds of dissimilar transistors (for example P channel metal-oxide semiconductor (PMOS) transistor AND gate N channel metal-oxide semiconductor (NMOS) transistor) is placed among the pressurization confined reaction chamber (chamber), and feeds at least two kinds of passivation gas.Because can be by selecting suitable passivation gas, make that wherein a kind of gas is suitable for passivation PMOS transistor, and another kind of gas is suitable for the passivation nmos pass transistor, and therefore method of the present invention can all obtain effect preferably at PMOS transistor and both passivation of nmos pass transistor.

These two kinds of passivation gas can be passed among reative cell simultaneously.Also can earlier the gas that is suitable for passivation first transistor npn npn be fed among the reative cell, and the heating semiconductor element is up to the purpose that is enough to reach passivation first transistor npn npn; The gas that will be suitable for passivation second transistor npn npn again feeds in the reative cell of keeping under high pressure, and the heating semiconductor element is up to the purpose that is enough to reach this second transistor npn npn of passivation.

According to an aspect of the present invention, a kind of passivation gas is hydrogen or nitrogen, and another kind of passivation gas is water or ammonia.

Therefore, be formed at indivedual passivation optimizations of the PMOS transistor AND gate nmos pass transistor in the semiconductor element, can reach by aforesaid two independent passivation step, thus, its technological parameter is optimization and make the PMOS transistor AND gate nmos pass transistor with desirable characteristics respectively.

Though as long as chamber pressure is greater than an atmospheric pressure, the efficient of passivation operation will be promoted to some extent, but suitable pressure is between 5 atmospheric pressures and 20 atmospheric pressures, and semiconductor element can be that CMOS (Complementary Metal Oxide Semiconductor) (CMOS) element, two-carrier CMOS (Complementary Metal Oxide Semiconductor) (BiCMOS) element, DRAM (Dynamic Random Access Memory) (DRAM) or other comprise at least two kinds of transistorized integrated circuits.

Description of drawings

Fig. 1: the embodiment one of according to the present invention, the semiconductor element in reative cell carries out the cutaway view of a passivation technology;

Fig. 2 to Fig. 4: cutaway view according to another embodiment of the present invention illustrates the key step of a passivation technology; And

Fig. 5: for according to semiconductor element shown in Figure 1 made cmos circuit cutaway view.

Description of reference numerals:

100 semiconductor elements

102 silicon dioxide layers

104 glass substrates

110 PMOS transistors

111 semiconductor structures

112 semiconductor structures

114 source electrodes

116 drain electrodes

118 gate electrodes

120 nmos pass transistors

124 source electrodes

126 drain electrodes

128 gate electrodes

130 passivation layers

200 reative cells

300 CMOS (Complementary Metal Oxide Semiconductor) circuit

Embodiment

With reference to Fig. 1, this figure is according to the principle of the present invention cutaway view of the semiconductor element 100 of passivation (passivation) in addition.Semiconductor element 100 has P channel conductor metal oxide (PMOS) transistor 110 and N channel metal-oxide semiconductor (NMOS) transistor 120.And this semiconductor element 100 can be that CMOS (Complementary Metal Oxide Semiconductor) (CMOS) element, two-carrier CMOS (Complementary Metal Oxide Semiconductor) (BiCMOS) element, DRAM (Dynamic Random Access Memory) (DRAM) or other have at least two kinds of transistorized integrated circuits.

As shown in Figure 1, semiconductor element 100 comprises that a resilient coating 102 (as silicon dioxide layer) is formed on the substrate 104 (as glass substrate), two semiconductor structures 111,121 (formed by a polysilicon membrane) are formed on the resilient coating 102, a gate insulator (as Si oxide) is formed on the semiconductor structure 111,121 and two gate electrodes 118,128.The source electrode 114 of PMOS transistor 110 and drain electrode 116, by utilizing this gate electrode 118 as photomask P type dopant (dopant), in the mode of self-aligned (self-align), inject this semiconductor structure 111 by ion implantation or plasma doping method and form.The source electrode 124 of nmos pass transistor 120 and drain 126 by utilizing this gate electrode 128 as covering N type alloy, injects this semiconductor structure 121 and forms.

In the present invention, at the defective that is produced in semiconductor element 100, for example dangling bonds (unsaturated silicon key) is repaired by semiconductor element 100 is used the high pressure passivation technology of two kinds of different passivation gas at least.Being suitable for passivation gas of the present invention is nitrogen, hydrogen, water, laughing gas, oxygen, ammonia or its mixture.

According to one embodiment of the invention, after semiconductor element 100 was placed a reative cell (chamber) 200, two kinds of different passivation gas (passivating gas) (for example steam/nitrogen or steam/hydrogen) were fed the reative cell (chamber) that is higher than 1 atmospheric pressure simultaneously and are carried out.Yet to handle be to carry out between 5 atmospheric pressures and 20 atmospheric pressures to high pressure annealing in a preferred embodiment, and the pressure of the basis of time use handled of high pressure annealing and deciding.Under high pressure carry out because this high pressure annealing is handled, its temperature and time can effectively reduce.In one embodiment, this high pressure annealing is handled and can be carried out being lower than under 600 ℃ the temperature.Those of skill in the art can obtain the optimum condition that high pressure annealing of the present invention is handled according to aforementioned technological parameter.It is believed that this passivation gas (steam/nitrogen or steam/hydrogen) not only provides the scission of link of hydrogen atom and silicon to form bond, to remove the aforementioned defective that is produced, and it also can diffuse into polysilicon membrane with passivation (passivate) grain boundary (grain boundaries), to provide performance better element.

It should be noted that, select suitable passivation gas owing to can see through, make that wherein a kind of gas is suitable for passivation PMOS transistor 110, and make another kind of gas be suitable for passivation nmos pass transistor 120, therefore method of the present invention can all obtain effect preferably at PMOS transistor and both passivation of nmos pass transistor.In an embodiment of the present invention, the electron mobility (mobility) of the semiconductor element 100 of process high pressure annealing processing can reach 150cm ²More than/the V-s.

According to another embodiment of the present invention, passivation technology can utilize two independent processes to finish.At first, after semiconductor element 100 was placed reative cell 200, first passivation gas (for example hydrogen or nitrogen) that is suitable for passivation PMOS transistor 110 fed among previous reaction chamber 200 (referring to the 2nd figure) earlier.Heat semiconductor element 100 again till being enough to produce passivation PMOS transistor 110, second passivation gas (for example steam or ammonia) that will be suitable for passivation nmos pass transistor 120 afterwards again feeds among the reative cell of keeping under high pressure 200.Afterwards, heat this semiconductor element 100 till being enough to produce passivation nmos pass transistor 120.Nmos pass transistor 120 can carry out passivation (referring to Fig. 3) under the mist of first passivation gas and second passivation gas.In addition, first passivation gas can be discharged in this reative cell by feeding second passivation gas, makes nmos pass transistor 120 only by the second passivation gas passivation (referring to Fig. 4).It should be noted that second passivation gas also can be passed into earlier in this reactive tank, in order to implementing passivation, and then carry out the passivation of pair pmos transistor 110 by feeding first passivation gas to this nmos pass transistor 120.

Use the cited technology of present embodiment, it makes PMOS transistor 110 and indivedual passivation of nmos pass transistor 120 obtain optimization.Because this PMOS transistor 110 carries out passivation with nmos pass transistor 120 respectively in aforesaid mode, therefore its technological parameter can be distinguished optimization, and makes the PMOS transistor 110 that makes have roughly the same critical voltage (threshold voltage) with nmos pass transistor 120.In one embodiment of this invention, the critical voltage difference of this PMOS transistor 110 and nmos pass transistor 120 can remain within two volts.

At semiconductor element 100 according to the principle of the invention and in addition after the passivation, can further be processed into CMOS (Complementary Metal Oxide Semiconductor) (CMOS) circuit 300 (referring to Fig. 5) that are used for the active matrix type display device.Detailed it, form a passivation layer 130 (as silicon nitride layer) prior to the surface of semiconductor element 100, this passivation layer 130 has after the predetermined thickness, patterned passivation layer 130 is with the part of the source of exposing/drain electrode 114,116 and source/drain electrode 124,126.Form a metallic film again on patterned passivation layer 130, this metallic film of patterning is to form a syndeton 140, in order to connect PMOS and nmos pass transistor 110,120 other zone to cmos circuit 300 afterwards.

Be understandable that passivating method of the present invention also can be implemented again after forming passivation layer 130.Gone through though The present invention be directed to CMOS (Complementary Metal Oxide Semiconductor) (CMOS) circuit that is used for the active matrix type display device, yet the present invention also can be applied at least two kinds of transistorized semiconductor devices that have of all kinds.

Though the present invention is open by preferred embodiment as described above; yet be not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention; obviously can do various changes and modification, so protection scope of the present invention should be as the criterion with the scope that appending claims was defined.

Claims

1. the passivating method of a semiconductor element comprises at least:

Semiconductor element is placed among the reative cell, and this semiconductor element has one first transistor npn npn and one second transistor npn npn, the conduction type of this first transistor npn npn and this second transistor npn npn is opposite each other;

One second passivation gas that will be suitable for one first passivation gas of this first transistor npn npn of passivation and be suitable for this second transistor npn npn of passivation feeds among this reative cell, and wherein this first passivation gas is hydrogen or nitrogen, and this second passivation gas is water or ammonia; And

Heat this semiconductor element, up to being enough to till this semiconductor element generation passivation.

2. semiconductor element passivating method as claimed in claim 1, wherein this first transistor npn npn is a P channel metal-oxide semiconductor transistor, and this second transistor npn npn is a N channel metal-oxide semiconductor transistor.

3. semiconductor element passivating method as claimed in claim 1, wherein this first and this second passivation gas be passed into simultaneously among this reative cell.

4. semiconductor element passivating method as claimed in claim 1 wherein feeds this first passivation gas in this reative cell earlier, and heats this semiconductor element up to being enough to till this first transistor npn npn generation passivation; Feed this second passivation gas again to this reative cell, and heat this semiconductor element up to being enough to till this second transistor npn npn generation passivation.

5. semiconductor element passivating method as claimed in claim 4, wherein this first passivation gas is discharged in this reative cell by feeding this second passivation gas, and this chamber pressure is kept greater than an atmospheric pressure always.

6. semiconductor element passivating method as claimed in claim 1, wherein this semiconductor element comprises a CMOS (Complementary Metal Oxide Semiconductor) circuit that is used for the active matrix type display device.

7. semiconductor element passivating method as claimed in claim 1, wherein this chamber pressure maintains between 5 atmospheric pressure to 20 atmospheric pressure.