CN100346454C - A metallized contact layer structure of silicon based device and method for making same - Google Patents
A metallized contact layer structure of silicon based device and method for making same Download PDFInfo
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- CN100346454C CN100346454C CNB2004100178405A CN200410017840A CN100346454C CN 100346454 C CN100346454 C CN 100346454C CN B2004100178405 A CNB2004100178405 A CN B2004100178405A CN 200410017840 A CN200410017840 A CN 200410017840A CN 100346454 C CN100346454 C CN 100346454C
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Abstract
The present invention belongs to the technical skill field of integrated circuit manufacture, and particularly relates to a metallization contact layer structure and a preparation method for metallization contact layers of silicon base devices. The metallization contact layer structure forms a metal silicide layer and a metal layer on a silicon base. The preparation method combines a self alignment metallization technique and a chemical plating technique or a plated metal technique and realizes a full self alignment metallization technique. The present invention has the advantages of good adhesive between the metallization contact layers and silicon, high mechanical strength, good corrosion resistance, simple manufacturing process of the preparation method and low cost. The present invention can be generally applied to integrated circuit manufacturing technique.
Description
Technical field
The invention belongs to field of IC technique, be specifically related to a kind of preparation method of metallization contact layer structure of silicon-based devices.
Background technology
A good silicon-based devices back face metalization contact layer requires to have good Ohmic contact, the low and good reliability of contact heat resistance.At present, the back face metalization contact layer of practical application, its structure generally is made up of three parts: ohmic contact layer, diffusion impervious layer and conductive layer.Ohmic contact layer requires with Si good adhesion is arranged, and has lower ohmic contact resistance, generally adopts Cr, Ti etc.; Conductive layer requires stable performance, easy and scolder welding, and conduction is good with heat conductivility, generally adopts Au, Ag etc.; And diffusion impervious layer is to stop Au, and Ag etc. are diffused in the ohmic contact layer, forms the high resistant phase, generally adopts Ni, Pd etc.
The preparation method of the metallization contact layers that device adopted such as some silicon-based devices such as thyristor is the back side or a two-sided evaporated metal on silicon chip at present.General three-layer metal: Ti-Pd-Ag or the Cr-Ni-Ag etc. of adopting by the metal level on the method removal oxide layer of dual surface lithography or polishing, weld on metal level then again, draw lead.The deficiency that this method exists is: existing process using three-layer metal still because intermetallic is difficult to form the good metal bonding, occurs dividing the metal level break-off of fault rupture as the transition zone of welding easily.And whole arts demand adopts multi-time two-sided photoetching, and technology is complicated.
Summary of the invention
The objective of the invention is to propose the new construction of the good device metallization contact layer of a kind of performance, and propose the preparation method of simple, the lower-cost contact layer that should metallize of technology.
The structure of the silicon-based devices metallization contact layer that the present invention proposes is the SiO at device
2Be formed with metal silicide layer in the substrate, thickness is 10-100nm; Also be coated with metal level on it, thickness is 100-500nm.
In the metallization contact layer of above-mentioned device, described metal silicide, metal wherein comprise transition metal (as Ti, V, Cr, Co etc.), refractory metal (as Ni, Pd, Mo, W, Ta etc.), near noble metal etc.Described metal level, its material is so long as can carry out chemical plating or electroplated metal all can.
For the new construction of above-mentioned device metallization contact layer, the present invention proposes the preparation method that self-aligned metal silicate technology and chemical plating or plated metal technology combine.In this method, need not photoetching, technical process is simple, and cost also further reduces.
Self-aligned silicide technology is a kind of technology commonly used in the integrated circuit, and its technical process is at the SiO that makes the silicon window by lithography
2Depositing metal on the substrate comprises transition metal (as Ti, V, Cr etc.), 3d, 4d and 5d metal (as Ni, Pd, Mo, W, Ta etc.), behind thermal annealing, metal and Si reaction generates silicide, and and SiO
2Do not react, corrode on the silicon then and SiO
2On behind the metal that do not react, further annealing just can be at the required silicide of Si zone formation, and at SiO
2The no silicide in zone.Utilize self-registered technology to form low-resistance conductive silicide layers at silicon and polysilicon surface, whole process need not photoetching, and technical process is very simple.In the forming process of self-aligned silicide, metal and Si react, and a part of silicon " is eaten up " in meeting, form silicide, so the adhesion of metal silicide and Si are very good.
The process of plating or chemical plating occurs in electric conductor and the surface that activated, and after Overheating Treatment, can make metal level optionally be plated in the metal silicide surface, and can not be plated in silica surface.Therefore plating or chemical plating process also are a kind of autoregistration processes, need not photoetching.The crystallization of plating or chemical nickel plating is careful, the hardness height, and coating is even, and solderability is good, and is corrosion-resistant.Compare with common three-layer metal Ti-Pd-Ag metallization process, the metal of plating or chemical plating and the solderability of scolder are better, and mechanical strength is higher, to the not influence of electric property of device.
The present invention proposes plating on metal silicide, can realize the metallization process of fully self aligned.The concrete operations step is as follows: a, a silicon-based devices 1 is provided, and its single or double all has device, comprises oxide layer isolated area and active device region, or pure Si substrate; B. at this silicon chip monolithic or two-sided depositing metal 2; C carries out first time annealing, makes the silicon of this metal and Si device region react and forms silicide 3, and do not react with oxide layer; D removes the metal level on the oxide layer; E carries out the annealing second time, further reacts with silicide, forms the metal silicide of low-resistivity; F, the oxide layer of removal suicide surfaces; G electroplates or chemical plating metal layer 4; H: on metal level, weld, draw lead 5.
In step a, the silicon-based devices figure that provides is not limit, but zone that is covered by medium and the zone of exposing silicon must be arranged, or is the zone of Si entirely.
In step b, the kind of depositing metal generally is the metal that energy and silicon form good low-resistivity silicide, comprises transition metal, refractory metal, and near noble metal, for example: Ti, V, Cr, Ni, Pd, Mo, W, Ta etc.The thickness of film in 10 nanometers between 100 nanometers.The too thin difficult film that forms good quality too thickly causes unnecessary waste.Physical vapor deposition is generally adopted in deposit, also can adopt chemical vapor deposition.
In step C, it is metal and Si are reacted, and do not react with silica that the selection of annealing temperature for the first time requires.Therefore, different metals requires different annealing temperatures.
In step D, the metal level of removing on the oxide layer can be with ways such as dry etching or wet etchings.
In step e, the second time, the selection requirement of annealing temperature was, silicide is further reacted, and forms the silicide of low-resistivity, but the thermal stability of silicide is destroyed; Just can form the metal of low-resistivity silicide at low temperatures for some, can carry out this step.
In step F, the metals deposited material so long as the conductor that chemical plating and plating can be carried out all can.
Description of drawings
Fig. 1: single or double has the schematic diagram of component graphics.
Fig. 2. the schematic diagram after deposit layer of metal on the pattern piece.
Fig. 3. after the annealed and selective etching, the schematic diagram after autoregistration on the Si forms silicide.
Fig. 4. at the place plating that silicide is arranged or the schematic diagram of chemical plating metal.
Number in the figure: 1 is silicon-based devices, and 2 is the metals deposited layer, and 3 is metal silicide layer, and 4 is metal level, and 5 is lead.
Embodiment
The invention is further illustrated by the following examples.
Embodiment 1, CoSi
2Last chemical plating metal
1,, provide one two-sided (single face also can) that the pattern piece of device is arranged with reference to Fig. 1.
2, with reference to Fig. 2, with the physical vapor deposition method at the two sides of pattern piece deposit one high melting metal layer Co.The thickness of metal is between 10nm～100nm.Vacuum chamber should have base vacuum preferably.If vacuum chamber does not have vacuum degree preferably, making has more oxygen in the atmosphere, causes the oxidation of film easily.Preferred vacuum degree is 10
-7Pa～10
-5Between the Pa.
3, with reference to Fig. 3, under 500～650 ℃ of temperature, carry out the annealing first time, on pattern piece, form a cobalt silicide.Select corrosive liquid (as adding H with acid or alkalescence then
2O
2And H
2The HCl solution of O), water-bath heating is carried out selective etching for about 60～90 ℃, erode do not react metal, use the deionized water rinsing some time then, the preferred time is to be no less than 10 minutes.Under 700～950 ℃ of temperature, carry out the annealing second time again.This moment, the cobalt disilicide of low-resistivity was completed on pattern piece.This step process is the autoregistration process, need not photoetching.
Then pattern piece is carried out surface treatment.(a preferred example is HCl: H with acidity or alkaline solution with pattern piece
2O
2: H
2O=1: the solution of 2: 8 proportionings) carry out rinsing after, use the deionized water rinsing some minutes, the preferred time is to be not less than 5 minutes.
4, then, will contain main salt, the reducing agent of Ni ion, the plating bath of complexing agent fully mixes, (a preferred example is with NiSO
4: 6H
2O: sodium acetate (NaC
2H
3O
2): natrium citricum (Na
3C
6H
6O
7)=25: 5: 5 and sodium hypophosphite (NaH
2PO
2: H
2O) 20 mix, and add ammoniacal liquor in solution, and regulating pH value is between 8 to 11.Solution is placed in the water-bath of constant temperature (between 70～100 ℃, a preferred temperature is about 75-85 ℃).
With reference to Fig. 4, before carrying out chemical plating, substrate is through activation processing.Activating solution is that (a preferred example is HF: H in the HF acid of diluting
2O=1: 40), soak time is about 1 minute to 5 minutes.The purpose of activation is to remove the oxide layer of suicide surfaces, makes metal can be plated in the suicide surfaces of conduction, if the too short purpose of activation that do not reach of soak time, the time, oversize then HF acid was over the whole corrosion of silicide.Then the slice, thin piece that activated is put into plating bath and carry out chemical plating process.When treating that bubble appears in the surface, begin to clock, after about a period of time,, take out the slice, thin piece washed with de-ionized water, and use N
2Air-blowing is done.The thickness of coating should be in 100nm～500nm, and the too thick coating that causes easily of coating ruptures.This moment, nickel was plated to the two sides of silicon chip simultaneously.Because Ni-Speed is the self-catalysis process, only carry out, so this step process still need not photoetching at conductive region.Or self-registered technology.
Embodiment 2, Electroless Plating Ni on NiSi:
1, with reference to Fig. 1, with the metal Ni film of sputtering method deposit one deck, thickness is 10-100nm on pattern piece.
2, with reference to Fig. 2, under high pure nitrogen protection, carry out first step annealing, annealing temperature is between 250 ℃～500 ℃, and the time is 10s～10 minute, and preferred time is 30S～2 minute.Then with acid solution H for example
2SO
4: H
2O=1: 1 solution carries out selective etching, and unreacted corrosion of metals completely on Si and the oxide layer is fallen, and the time is 5-10 minute.Use the deionized water rinsing some minutes then, use N
2After drying up.If first step annealing temperature is chosen in below 450 ℃, need carry out second step annealing again, annealing temperature is from 450 ℃ to 600 ℃, and the time was from 30S to 5 minute.If first step annealing temperature more than 450 ℃, then can not need to carry out second step annealing.3, then, will contain main salt, the reducing agent of Ni ion, the plating bath of complexing agent fully mixes, (a preferred example is with NiSO
4: 6H
2O: sodium acetate (NaC
2H
3O
2): natrium citricum (Na
3C
6H
6O
7)=25: 5: 5 and sodium hypophosphite (NaH
2PO
2: H
2O) 20 mix, and add ammoniacal liquor in solution, and regulating pH value is between 8 to 11.Solution is placed in the water-bath of constant temperature (between 70～100 ℃, a preferred temperature is about temperature 75-85 ℃).
Before carrying out chemical plating, (a preferred example is H with acid solution earlier
2SO
4: H
2O=1: 1 solution) clean sample.Behind the deionized water rinsing, activate with activating solution, (a preferred example is HF: H
2O=1: 40), soak time is about 1 minute to 5 minutes.Slice, thin piece after will activating is then inserted in the plating bath, when treating that bubble appears in the surface, begins to clock, after about a period of time, and, take out the slice, thin piece washed with de-ionized water, and use N
2Air-blowing is done.The thickness of coating should be in 100nm～500nm, and the too thick coating that causes easily of coating ruptures.This moment, nickel was plated to the two sides of silicon chip simultaneously.Because Ni-Speed is the self-catalysis process, only carry out, so this step process still need not photoetching at conductive region.So this step process or self-registered technology.
1, at the metal Ti film of using sputtering method deposit one deck (thickness is between 10～100nm) on the pattern piece.
2, through 500～650 ℃ of annealing for the first time, on pattern piece, form a titanium silicide.Select corrosive liquid (as adding H with acid or alkalescence then
2O
2And H
2The HCl solution of O), water-bath heating is carried out selective etching for about 60～90 ℃, erode do not react metal, with deionized water rinsing some time then, the preferred time is more than 10 minutes then.Again through 700～950 ℃ of annealing for the second time.This moment, the titanium disilicide of low-resistivity was completed on pattern piece.This step process is the autoregistration process, need not photoetching.
3, then, will contain main salt, the reducing agent of Ni ion, the plating bath of complexing agent fully mixes, (a preferred example is with NiSO
4: 6H
2O: sodium acetate (NaC
2H
3O
2): natrium citricum (Na
3C
6H
6O
7)=25: 5: 5 and sodium hypophosphite (NaH
2PO
2: H
2O) 20 mix, and add ammoniacal liquor in solution, and regulating pH value is between 8 to 11.Solution is placed in the water-bath of constant temperature (between 70～100 ℃, a preferred temperature is about 75-85 ℃).
3. before carrying out chemical plating, (a preferred example is NH with acidity or alkaline solution earlier
4OH: H
2O
2: H
2O=1: 2: 5 solution) clean sample.Behind the deionized water rinsing, activate with activating solution, (a preferred example is HF: H
2O=1: 40), soak time is about 1 minute to 5 minutes.Slice, thin piece after will activating is then inserted in the plating bath, when treating that bubble appears in the surface, begins to clock, after about a period of time, and, take out the slice, thin piece washed with de-ionized water, and use N
2Air-blowing is done.The thickness of coating should be in 100nm～500nm, and the too thick coating that causes easily of coating ruptures.This moment, nickel was plated to the two sides of silicon chip simultaneously.Because Ni-Speed is the self-catalysis process, only carry out, so this step process still need not photoetching at conductive region.Or self-registered technology.
Embodiment 4, on NiSi Electroless Cu Plating
1,, on pattern piece, uses the metal Ni film of sputtering method deposit one deck (about 30nm-100nm) with reference to Fig. 1.
2, with reference to Fig. 2, under high pure nitrogen protection, carry out first step annealing, annealing temperature is between 250 ℃～500 ℃, and the time is 10s～10 minute, and preferred time is 30S～2 minute.Then with acid solution H for example
2SO
4: H
2O=1: 1 solution carries out selective etching, and unreacted corrosion of metals completely on Si and the oxide layer is fallen, and the time is 5 minutes.Use the deionized water rinsing some minutes then, use N
2After drying up.If first step annealing temperature is chosen in below 450 ℃, need carry out second step annealing again, annealing time is from 450 ℃ to 600 ℃, and the time was from 30S to 5 minute.If first step annealing temperature more than 450 ℃, then can not need to carry out second step annealing.
3, then, will contain main salt, the reducing agent of Cu ion, the plating bath of complexing agent fully mixes, (a preferred example is with CuSO
4: 5H
2O: EDTA disodium salt (Na
2EDTA): bipyridine (C
5H
4N)
2=15: with formalin mix at 30: 0.1, and add NaOH (NaOH) in solution, regulating pH value is between 12 to 13.Solution is placed in the water-bath of constant temperature (between 20～50 ℃, a preferred temperature is about 25～35 ℃).
Before carrying out chemical plating, (a preferred example is H with acid solution earlier
2SO
4: H
2O=1: 1 solution) clean sample.Behind the deionized water rinsing, activate with activating solution, (a preferred example is HF: H
2O=1: 40), soak time is about 1 minute to 5 minutes.Slice, thin piece after will activating is then inserted in the plating bath, when treating that bubble appears in the surface, begins to clock, and after a period of time, takes out the slice, thin piece washed with de-ionized water, and uses N approximately
2Air-blowing is done.The thickness of coating should be in 100nm～500nm, and the too thick coating that causes easily of coating ruptures.This moment, Cu was plated to the two sides of silicon chip simultaneously.Because plating Cu process is the self-catalysis process, only carry out at conductive region, so this step process still need not photoetching.So this step process or self-registered technology.
Though what provide in the foregoing description is the example of Electroless Plating Ni or Cu, for other metals of chemical plating, perhaps with electroplating the plating associated metal, a skilled engineer can finish the used method of the present invention.
Claims (3)
1, a kind of preparation method of metallization contact layer structure of silicon-based devices is characterized in that self-aligned metal silicate technology and chemical plating or plated metal layer process are combined, and the concrete operations step is as follows:
A, provide a silicon-based devices (1), its single face that device is arranged or two-sided device arranged, comprise oxide layer isolated area and active device region;
B, at the single or double depositing metal (2) of this silicon-based devices (1);
C, carry out first time annealing, make the silicon of this metal and silicon-based devices react and form silicide (3), and do not react with the oxide layer isolated area;
Metal on d, the removal oxide layer isolated area;
E, carry out second time annealing, silicide is further reacted, form the metal silicide layer of low-resistivity;
The oxide layer of f, removal suicide surfaces;
G, electroplate or chemical plating metal layer (4);
H, on metal level, weld, draw lead (5);
Wherein, the thickness of described metal silicide layer is 10-100nm, and the thickness of described metal level (4) is 100-500nm.
2, the preparation method of the metallization contact layer structure of silicon-based devices according to claim 1 is characterized in that the metal in the said metal silicide layer is a transition metal, refractory metal, or near noble metal; Described metal layer material is for can carry out chemical plating or electroplated metal.
3, the preparation method of the metallization contact layer structure of silicon-based devices according to claim 1 is characterized in that metal in the said metal silicide layer is a kind of of Ti, V, Cr, Co, Ni, Pd, Mo, W, Ta.
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|---|---|---|---|
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1068444A (en) * | 1991-07-08 | 1993-01-27 | 三星电子株式会社 | Semiconductor device and manufacture method thereof |
| US5427981A (en) * | 1993-02-17 | 1995-06-27 | Hyundai Electronics Industries Co., Ltd. | Process for fabricating metal plus using metal silicide film |
| US5744395A (en) * | 1996-10-16 | 1998-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance, self-aligned, titanium silicide structures, using a single rapid thermal anneal procedure |
| US6420784B2 (en) * | 1999-04-16 | 2002-07-16 | Micron Technology, Inc | Electrochemical cobalt silicide liner for metal contact fills and damascene processes |
| CN1484285A (en) * | 2002-09-18 | 2004-03-24 | 上海宏力半导体制造有限公司 | Method for forming self-alignment metal silicide |
-
2004
- 2004-04-22 CN CNB2004100178405A patent/CN100346454C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1068444A (en) * | 1991-07-08 | 1993-01-27 | 三星电子株式会社 | Semiconductor device and manufacture method thereof |
| US5427981A (en) * | 1993-02-17 | 1995-06-27 | Hyundai Electronics Industries Co., Ltd. | Process for fabricating metal plus using metal silicide film |
| US5744395A (en) * | 1996-10-16 | 1998-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low resistance, self-aligned, titanium silicide structures, using a single rapid thermal anneal procedure |
| US6420784B2 (en) * | 1999-04-16 | 2002-07-16 | Micron Technology, Inc | Electrochemical cobalt silicide liner for metal contact fills and damascene processes |
| CN1484285A (en) * | 2002-09-18 | 2004-03-24 | 上海宏力半导体制造有限公司 | Method for forming self-alignment metal silicide |
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