CN100342348C - Fault-eliminating device and its method - Google Patents
Fault-eliminating device and its method Download PDFInfo
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- CN100342348C CN100342348C CNB2003101000744A CN200310100074A CN100342348C CN 100342348 C CN100342348 C CN 100342348C CN B2003101000744 A CNB2003101000744 A CN B2003101000744A CN 200310100074 A CN200310100074 A CN 200310100074A CN 100342348 C CN100342348 C CN 100342348C
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- 238000012545 processing Methods 0.000 claims description 34
- 238000013461 design Methods 0.000 claims description 6
- 238000002203 pretreatment Methods 0.000 claims description 4
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Abstract
The present invention relates to a debugging device and a method thereof. The device comprises a CPU connected with a chip set with a system managing and interrupting pin. The implement method comprises the steps that a system managing and interrupting pin of the chip set sends out a system managing and interrupting signal to the CPU; the CPU enters a system managing mode and executes a command to bounce out a debugging operating window, and debugging items are selected and executed; the CPU leaves the debugging operating window and returns to the next command to be processed before the CPU when the execution is completed. Therefore, as the CPU returns to a job system to continuously execute commands before the debugging after the debugging operating window is operated to execute the debugging items, the state and the program execution of any job system can not be influenced, and the present invention is convenient in use anytime for completing the debugging items.
Description
Technical field
The present invention relates to a kind of apparatus for debugging and method thereof.
Background technology
In computer system now because system designer is in the design of motherboard and debug during the stage, regular meeting face on some hardware and software on a difficult problem; To this, the deviser then often utilizes some debug engines or software debug program to solve, as utilize logic analyzer (Logical Analyzer, LA) and SCOPES capture PCI and handle cycle and signal waveform, perhaps utilize hardware IC E to catch the instruction flow of central processing unit (CPU), or utilize software I CE to catch instruction flow of operating system or the like.
Yet, to these a little hardware toolses, i.e. LA, SCOPES, hardware IC E or the like, generally all very expensive, and its operating process is also all very complicated, does not meet very much the demand of user's interface; And in other respects, as when utilizing software I CE implementing procedure to wait to carry out debug work, though non-costliness as hardware tools is also not cheap, and it uses qualification then only in the operating system start-up phase, yet still has many other mistakes (bug) may take place before its setting is finished; Moreover when utilizing software I CE implementing procedure to wait to carry out debug work, regular meeting changes the executive routine of operating system, its easier so and cause system to produce the mistake that other can not be estimated, so its use is not to be efficient selection.
Therefore, develop a kind of efficient and cheaply debugging tool make system design more convenient, the debug process is simpler, is the primary problem that solves of the present invention.
Summary of the invention
In view of this, fundamental purpose of the present invention is that a kind of apparatus for debugging and method thereof are being provided, be the debugging tool program of depositing in the System Management Mode block of BIOS, it is that break signal triggers that this debugging tool program can be utilized, and reaches the purpose of arbitrary time execution debug.
Secondary objective of the present invention is that a kind of apparatus for debugging and method thereof are being provided, and is to utilize the debugging tool program to show the debug operating window, simplifies and the convenient purpose of using conveniently to select and to carry out each debug project, to reach.
Another purpose of the present invention is that a kind of apparatus for debugging and method thereof are being provided, because after carrying out every debug project, its central processing unit is just got back to the next pending instruction before the debug, so just be unlikely to influence the executive routine of operating system, reach minimizing and produce other wrong purposes because of carrying out the debug process.
Above-mentioned purpose of the present invention is realized by following technical scheme.
A kind of debug method, this method are to be used for a computer system, and wherein this computer system includes a central processing unit, connects a chipset, and the feature of this method is to comprise:
Send a system management interrupt signal to this central processing unit from this chipset;
This central processing unit promptly enters a System Management Mode and executive routine is jumped out a debug operating window;
Each debug project that execution is selected by the user, this each debug project include the interruption of access I/O, storage access, access device configuration and the special I/O address of tool and set; And
Next pending instruction before when being finished, leaving this debug operating window and being back to this central processing unit.
This debug operating window is the programmable design.
Sending a system management interrupt signal to the step of this central processing unit from this chipset, is to trigger this chipset by the general I/O pin that a user utilizes this chipset to set, so that it sends system management interrupt signal.
Still comprise a step, this step is left this debug operating window and is back to this central processing unit after the next pending instruction of pre-treatment when being finished, and this debug operating window will be jumped out for operation when once triggering this chipset in this user.
Still comprise a step, this step is left this debug operating window and is back to this central processing unit after the next pending instruction of pre-treatment when being finished, and this debug operating window will be jumped out for operation when the interruption address set.
The present invention also provides a kind of apparatus for debugging, it is characterized in that this device comprises:
One central processing unit;
At least one storer, this storer is connected to this central processing unit, and this storer is provided with a System Management Mode interval, has a debugging tool program in this System Management Mode interval; And
One chipset, this chipset is connected to this central processing unit, and this chipset is provided with at least one general I/O pin, triggers this chipset by this pin and sends system management interrupt signal.
This debugging tool program is tool one a debug operating window Presentation Function.
This system management interrupt signal is to make this central processing unit enter this System Management Mode interval, and carries out this debugging tool program wherein.
The invention has the advantages that:
This debugging tool program is to be set among the BIOS, so except that not causing the influence of cost the dealer, the more further sequencing design of its debug operating window is to make the user more convenient to use; Not adding to influence operating system, and to produce possible other mistakes (bug), the present invention is for effectively solving the debug difficult problem of the expensive poor efficiency of current dealer.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 is the apparatus for debugging block schematic diagram of a preferred embodiment of the present invention;
Fig. 2 is the debug method process flow diagram of a preferred embodiment of the present invention;
Fig. 3 be executive routine of the present invention operation do not influence the operating system synoptic diagram.
Embodiment
In central processing unit (CPU) now, as the Pentium (Pentium4) of Intel or the K7 of ultra micro initialization system management mode (System Management Mode is arranged all, SMM), to allow the user can be by a piece of wood serving as a brake to halt a carriage body, wait the control and management computer system as BIOS, and can not influence its operating system (OperationSystem OS).This System Management Mode (SMM) can be by system management interrupt signal (System ManagementInterrupt, SMI) trigger, promptly when central processing unit receives system management interrupt signal (SMI#), just can enter System Management Mode (SMM) and carry out the setting program that is stored in wherein.And when use finishing, also can utilize to return to instruction (resume instruction RSM) jumps out of System Management Mode and returns operating system.The present invention is convenient to use this characteristic, a debugging tool program is stored in the System Management Mode interval of BIOS, uses for the user.
See also Fig. 1 and Fig. 2, be the apparatus for debugging block schematic diagram and the debug method process flow diagram thereof of a preferred embodiment of the present invention of the present invention.As shown in the figure, in this computer system, its central processing unit 10 is connected with a north bridge chipset 12, and north bridge chipset 12 is connected with a South Bridge chip group 14, and South Bridge chip group 14 also is connected to central processing unit 10 via circuit 16, wherein this South Bridge chip group include a plurality of general discrepancy pins (General Purpose Input/Output, GPIOpin).Stagger the time in operating to remove; At first, the user needs to select earlier the universal output and input pins (GPIO) of South Bridge chip group 14, be set at and trigger South Bridge chip group 14 and send system management interrupt signal (SMI#), so just, can be shown in step 20, the user can trigger South Bridge chip 14 according to the universal output and input pins of having set, make it to send system management interrupt signal (SMI#), promptly shown in step 22; Then, system management interrupt signal (SMI#) via circuit 16 to central processing unit 10, central processing unit 10 just enters System Management Mode (SMM) after receiving system management interrupt signal (SMI#), this System Management Mode is to be located among the BIOS of DRAM, be that to be provided with a section space among the BIOS be the System Management Mode interval, and in the System Management Mode interval, have a default debugging tool program, so after entering System Management Mode, just can trigger by central processing unit 10 this debugging tool program, shown in step 24; This debugging tool program can utilize the debug operating window to make the user operate each debug project of selection, comprising that access is exported into the interruption of (Access IO), storage access (Access Memory), access device configuration (Access device configuration) and the special I/O address of tool sets (Settrap for specific IO address) etc., shown in step 26; At last, when user's end of operation, leave the debug operating window after, just be back to next pending instruction before the central processing unit 10, carry out its original program (seeing also Fig. 3), shown in step 28.
As shown in Figure 3, be executive routine of the present invention operation do not influence the operating system synoptic diagram.When central processing unit executive routine 30, the user is in address 0100 place's triggering system management interrupt signal (SMI#), and operate after debugging tool program 32 finishes as the user, system just can be to the next pending instruction address before the central processing unit, as address 0101, to continue to carry out all original programs.So, just can not influence original operating system program implementation, also can reduce effectively when using the debugging tool program the mistake (bug) that may cause.
Certainly, if the user is after the execution debug finishes, in its random time, still but triggering system management interrupt signal (SMI#) is carried out the debugging tool program, and if the user has been set with the words of interrupting address (trap address) in this debug process, just can triggering system management interrupt signal (SMI#) when then central processing unit is carried out this address to jump out the debug operating window, carry out debug for the user, as repeating step 22 to 38.
Disclosed a kind of apparatus for debugging of the above embodiment of the present invention and method thereof, for utilizing system management interrupt signal to trigger the debug operating window,, make system design more convenient to carry out every debug project, the debug process is simpler, reaches effectively and purpose cheaply.
In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (7)
1, a kind of debug method, this method are to be used for a computer system, and wherein this computer system includes a central processing unit, connects a chipset, and the feature of this method is to comprise:
Send a system management interrupt signal to this central processing unit from this chipset;
This central processing unit promptly enters a System Management Mode and executive routine and jumps out a debug operating window;
Each debug project that execution is selected by the user; And
Leave this debug operating window and be back to the next pending instruction of this central processing unit in pre-treatment when being finished, this debug operating window will be jumped out for operation when the interruption address set afterwards.
2, debug method according to claim 1 is characterized in that: this each debug project includes the interruption of access I/O, storage access, access device configuration and the special I/O address of tool and sets.
3, debug method according to claim 1 is characterized in that: this debug operating window is the programmable design.
4, debug method according to claim 1, it is characterized in that: send a system management interrupt signal to the step of this central processing unit from this chipset, be to trigger this chipset, so that it sends system management interrupt signal by the general I/O pin that a user utilizes this chipset to set.
5, debug method according to claim 1, it is characterized in that: also comprise a step, this step is left this debug operating window and is back to this central processing unit after the next pending instruction of pre-treatment when being finished, this debug operating window will be jumped out for operation when once triggering this chipset in the user.
6, a kind of apparatus for debugging is characterized in that, this device comprises:
One central processing unit;
At least one storer, this storer is connected to this central processing unit, and this storer is provided with a System Management Mode interval, has a debugging tool program in this System Management Mode interval; And
One chipset, this chipset is connected to this central processing unit, and this chipset is provided with at least one general I/O pin, send system management interrupt signal by this pin flip chip group, this system management interrupt signal makes central processing unit entrance management pattern interval, and carries out debugging tool program wherein.
7, apparatus for debugging according to claim 6 is characterized in that: this debugging tool program is tool one a debug operating window Presentation Function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101000744A CN100342348C (en) | 2003-10-08 | 2003-10-08 | Fault-eliminating device and its method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101000744A CN100342348C (en) | 2003-10-08 | 2003-10-08 | Fault-eliminating device and its method |
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| Publication Number | Publication Date |
|---|---|
| CN1529241A CN1529241A (en) | 2004-09-15 |
| CN100342348C true CN100342348C (en) | 2007-10-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2003101000744A Expired - Lifetime CN100342348C (en) | 2003-10-08 | 2003-10-08 | Fault-eliminating device and its method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826046B (en) * | 2009-03-06 | 2011-12-14 | 纬创资通股份有限公司 | Power-on debugging method of computer |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI546660B (en) * | 2015-09-22 | 2016-08-21 | 新唐科技股份有限公司 | Debugging system and method |
| JP6996748B2 (en) * | 2018-11-22 | 2022-01-17 | Ｎｅｃプラットフォームズ株式会社 | Debug system, BIOS, information processing device and debugging method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5729760A (en) * | 1996-06-21 | 1998-03-17 | Intel Corporation | System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode |
| US5796984A (en) * | 1996-01-26 | 1998-08-18 | Dell Usa, L.P. | Operating system independent apparatus and method for eliminating peripheral device functions |
| CN1251448A (en) * | 1998-10-20 | 2000-04-26 | 富士通株式会社 | Error processing method, information processing system, control compartment and storage medium |
| CN1279427A (en) * | 1999-06-29 | 2001-01-10 | 神达电脑股份有限公司 | Error correcting system able to correct error of computer in shutdown state |
| US20020156958A1 (en) * | 2001-04-18 | 2002-10-24 | Chung-Ching Huang | Method and chipset for system management mode interrupt of multi-processor supporting system |
-
2003
- 2003-10-08 CN CNB2003101000744A patent/CN100342348C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796984A (en) * | 1996-01-26 | 1998-08-18 | Dell Usa, L.P. | Operating system independent apparatus and method for eliminating peripheral device functions |
| US5729760A (en) * | 1996-06-21 | 1998-03-17 | Intel Corporation | System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode |
| CN1251448A (en) * | 1998-10-20 | 2000-04-26 | 富士通株式会社 | Error processing method, information processing system, control compartment and storage medium |
| CN1279427A (en) * | 1999-06-29 | 2001-01-10 | 神达电脑股份有限公司 | Error correcting system able to correct error of computer in shutdown state |
| US20020156958A1 (en) * | 2001-04-18 | 2002-10-24 | Chung-Ching Huang | Method and chipset for system management mode interrupt of multi-processor supporting system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826046B (en) * | 2009-03-06 | 2011-12-14 | 纬创资通股份有限公司 | Power-on debugging method of computer |
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| CN1529241A (en) | 2004-09-15 |
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