CN100342335C - Chip program loading method - Google Patents
Chip program loading method Download PDFInfo
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- CN100342335C CN100342335C CNB2004100830259A CN200410083025A CN100342335C CN 100342335 C CN100342335 C CN 100342335C CN B2004100830259 A CNB2004100830259 A CN B2004100830259A CN 200410083025 A CN200410083025 A CN 200410083025A CN 100342335 C CN100342335 C CN 100342335C
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- loading method
- program loading
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
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Abstract
The present invention relates to the field of electron, which discloses a chip program loading method. The present invention avoids the situation that because a chip which does not need to be loaded is loaded repeatedly, the required time of system initialization is prolonged, so the upgrade of the system can be reliable and convenient. The present invention has the theory that the current program and an object program are compared with that a unique identity can be directly obtained from the self of a program file. When the current program and the object program are consistent, the chip can not be loaded repeatedly any longer. When the current program and the object program are not consistent, the program is loaded.
Description
Technical field
The present invention relates to electronic applications, particularly the program loading technique of programmable chip.
Background technology
Microelectric technique enters a very crucial period at present through 50 years of development, and process is more and more littler, and integrated level is more and more higher, combines more and more tightr with other subject.And the logical device field is an important development branch of microelectric technique, and with fastest developing speed in this field at present is programmable chip.The various electronic chips that need to carry out the program loading before use of programmable chip (Programmable Chip) general reference, in modern electronic product, use in a large number, include but not limited to field programmable gate array (Field Programmable Gate Array, abbreviation " FPGA "), digital signal processor (DigitalSignal Processor, abbreviation " DSP "), erasable programmable logical device logical devices such as (Erasable ProgrammableLogic Device are called for short " EPLD ").
The programmable chip lead time is shorter, directly development cost are lower, also unqualified minimum lot-size, increase along with gate circuit quantity in the reduction of gate circuit cost and the device, programmable chip is just carrying out on a large scale squeezing into traditional gate array field, but each company all must be different from the product design of oneself rival's product in the dirigibility that utilizes programmable chip, equally, semiconductor manufacturer has developed unique EPLD and FPGA etc., so that reach specific target at aspects such as performance, power consumption, integrated level and costs.Such way causes this class programmable chip to have notable difference on functional area and complexity.
But no matter how big this type of programmable chip have difference, all have a common ground,, need to be its loading procedure before the use promptly according to what describe in the aforementioned definitions.The program loading procedure of programmable chip normally powers on or resets at central processing unit (Central Processing Unit, be called for short " CPU ") and carries out after finishing, and controls whole loading procedure by CPU.With FPGA is example, the design process of whole programmable chip is such: at first chip design Shi Caiyong hardware description language (Hardware DescriptionLanguage is called for short " HDL ") is depicted the structure and the hardware behavior of hardware in the mode that is similar to programming; With design tool these are described then and comprehensively be mapped to the hardware technical papers relevant with semiconductor technology, the program in these descriptions and the software field is very similar, and programmable chip then is the carrier of these hardware technical paperss; By the special instrument that writes the hardware technical papers is loaded on the programmable chip at last, makes it to have function corresponding.
This shows that program loads and is the final step of whole programmable chip design process, and is very important.Though the program loading technique and the loading procedure of various programmable chips all are not quite similar, and all should satisfy reliable, quick, stable requirement, must fully take into account chip serviceable life and system upgrade process in addition.
Loading technique commonly used comprises following two kinds.
First kind is present modal loading technique: simple Loading Method.This method is used for the programmable chip that FPGA, DSP etc. can repeatedly load repeatedly more.Concrete implementation method is CPU in the moment that needs load, promptly power on or reset finish after, directly programmable chip is forced to load, the burning program that weaves is gone into wherein, make it to have specific function.This method is simply effective, realizes easily, also can fully satisfy the requirement of system upgrade.
Second method is the version checking Loading Method, is applicable to that EPLD etc. carries the programmable chip of nonvolatile memory.Concrete implementation method is that CPU carries out version detection to programmable chip earlier before loading, check promptly whether it carries on the nonvolatile memory program stored consistent with program version to be loaded, if testing result is consistent with program version to be loaded, then do not carry out load operation.This method can reduce the invalid number of times that repeats to load.
In actual applications, there is following problem in such scheme: for first kind of scheme, owing to insignificantly repeat to load often, consume the serviceable life of chip, therefore this scheme only is only applicable to the chip that can repeatedly load repeatedly, for example FPGA and DSP; In addition, because chip loads and need expend the long period, the mode that therefore this pressure loads has prolonged the required time of system initialization at large, however under many circumstances, especially system is charged reset after, do not need this extra loading.
For second kind of scheme, because this scheme need be attached unduplicated version number so system upgrade inconvenience in the chip program of issue.Specifically, if the version number that adopts the developer to set in advance, then because general development plan only is planned for large paper edition, cause inner little beta version and indefinite version to adopt identical version number, have to adopt manual mandatory upgrade when being upgraded to these versions, cause system upgrade unreliable and inconvenient; If according to program compilation time generation version number, the company for not adopting " day structure " method is difficult to manage and implement.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of chip program loading method, has avoided prolonging the required time of system initialization owing to the chip that does not need to load is repeated to load, and can make system upgrade reliable more and convenient.
For achieving the above object, the invention provides a kind of chip program loading method, comprise following steps:
B is according to the unique identification of directly deriving by program file, whether the detection chip present procedure is consistent with target program to be loaded, if inconsistent, execution in step C then, wherein, described unique identification is the attribute of program file or the information of itself being derived by this program file;
C is that described chip loads described target program.
Wherein, described method also comprises following steps:
D is to described chip initiation, and after carrying out described step C, carries out described step D.
When the present procedure of judging described chip among the described step B is consistent with target program to be loaded, execution in step D.
Described unique identification is the combination in any of any one or they in the digital digest, digital signature, contents of program check field, program size, program structure date and time of program.
Described chip is field programmable gate array or Erasable Programmable Logic Device or digital signal processor.
Described method also comprises following steps:
Whether A central processing unit detection chip function is normal, if, execution in step B then, otherwise, execution in step C.
In the described steps A, if described chip is field programmable gate array or Erasable Programmable Logic Device, carry out the detection that read-write operation is finished chip functions by detected register to the known address, if described chip is a digital signal processing chip, then carry out the detection that loopback test between digital signal processor-central processing unit is finished chip functions by communication link.
By relatively finding, technical scheme difference with the prior art of the present invention is, proposed the mode that present procedure and target program compared by the unique identification that can directly obtain, wherein unique identification is the information that the attribute of program file itself maybe can directly be derived from this program file itself.By above-mentioned uniquely identified relatively, for the present procedure situation consistent, no longer chip is repeated to load with target program.For inconsistent, just carry out program and load.
Difference on this technical scheme has brought comparatively significantly beneficial effect, avoided forcing in the prior art load mode causes the consumption chip problem in serviceable life, and has shortened the required time of system initialization under the situation that those reality do not need to load.In addition, this technical scheme does not rely on the version number of artificial setting only according to program file itself, makes system upgrade more reliable and convenient.
Description of drawings
Fig. 1 is the schematic flow sheet of chip program loading method according to an embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Generally speaking, principle of the present invention is by the attribute of program itself, or by the information that this program file itself derives out, judge whether the chip present procedure is consistent with target program, does not repeat to load under the situation of unanimity.Thereby avoided the invalid prolongation of system initialization required time, made system upgrade convenient, and this mode is applicable on other chips except loading repeatedly.
Below in conjunction with Fig. 1, launch in detail according to one embodiment of present invention, further explain and illustrate the principle and the workflow of the chip program loading method that proposes among the present invention.
At first in step 200, carry out default testing process by CPU, the function of programmable chip is detected, whether verify chip can operate as normal.If chip functions is normal, then change step 210 over to; If chip functions is unusual, then change step 220 over to.
In this step, for dsp chip, can carry out loopback test between DSP and the CPU by communication link.Specifically, CPU presets data, and sends a test data by the communication link between it and DSP to DSP.Then, DSP handles the test data from CPU, and result is returned to CPU by the communication link between CPU and DSP again.Then, CPU will make comparisons from result and its default data of DSP.If both are in full accord, then represent DSP energy operate as normal, the dsp chip function is normal; If both are not quite identical, then represent the DSP cisco unity malfunction, the dsp chip dysfunction.
On the other hand, for FPGA and EPLD, can carry out read-write operation to the detected register of known address.Specifically, CPU presets data, by address bus and data bus, is written in the detection input register of chip.The logical block of chip internal after detecting the content process computing of ad hoc rules of input register, is delivered in the detection output register of chip.Then, CPU reads the detection output register of chip, data that read out and the test data that before had been written to the detection input register is compared, if they meet desired computation rule, then represent detected register energy operate as normal, this chip functions is normal; If they do not meet desired computation rule, then represent the detected register cisco unity malfunction, this chip functions is unusual.
After this, enter step 210, whether the current working procedure of CPU detection chip is consistent with target program to be loaded, if consistent, then enters step 230, otherwise, enter step 220.
Need to prove, in the present invention, the unique identification that CPU directly obtains or derives according to the program file itself by chip, whether the present procedure of detection chip is consistent with target program to be loaded.In other words, CPU obtains the unique identification of current working procedure from chip, also obtains unique identification from target program to be loaded, relatively these two unique identifications.If in full accord, illustrate that then current working procedure of chip and target program to be loaded are just the same; If these two unique identifications are not quite identical, just illustrate that then current working procedure of chip and target program to be loaded are inconsistent.
Above-mentioned uniquely identified unique distinction is, directly obtains or derives by program file, does not need to set in advance artificially.In first embodiment of the present invention, unique identification can be a digital digest, this digital digest can be to use certain digest algorithm to calculate to contents of program, its content of different programs can be not in full accord, then uses the digital digest that respectively its content is calculated with a kind of digest algorithm generally can be not identical; In second embodiment of the present invention, unique identification also can be a digital signature, and this digital signature is to use known public keys and signature algorithm to calculate to contents of program, different contents of program, and its digital signature that calculates generally can be not identical; In the 3rd embodiment of the present invention, unique identification also can be to utilize the contents of program check field, can be that contents of program is carried out checking algorithm and the check field that obtains, such as cyclic redundancy check (CRC) code (Cyclic RedundancyCheck, be called for short " CRC "), its content of distinct program is not quite identical, then uses the CRC check algorithm and the check field that obtains generally can be not identical; In the fourth embodiment of the present invention, unique identification can also be the size of program, common two different programs, and its size also is different; In the fifth embodiment of the present invention, unique identification can also be the program structure date and time, and its structure date of common two different programs is generally inequality, if the structure date is identical, then its structure time can be not identical.Need to prove that in other embodiments of the invention, unique identification also can be the combination of above-mentioned some kinds of methods, the differentiation accuracy rate of distinct program uses a kind of technology higher than single like this.What deserves to be mentioned is, present most file layouts have comprised check field, digital digest or digital signature, system does not need to carry out extra computing, as long as some standard operations that utilize file system to provide just read check field, digital digest or the digital signature of file easily, thereby obtain the unique identification of target program; Perhaps system is according to canonical algorithm and public keys, after contents of program is calculated, just can obtain the unique identification of target program.In addition, after system generates a file, system will set attributes section for file automatically, and the byte number that has write down the shared storage space of file in the file attribute option is the size of file and the time that file generates, the attributes section of utilizing file system to read file is like this just obtained the size and the time of file easily, thereby obtains the unique identification of target program.Therefore, it generally is quite easy obtaining unique identification from target program file to be loaded, does not need system to carry out special computing or design.
This shows, the present invention does not limit uniquely identified specific implementation technology, so long as directly obtain or derive, and can correctly distinguish the uniquely identified realization technology of two distinct programs, in the category of the unique identification realization technology that all belongs to the present invention and supported from program itself.
In step 220 and since in the preceding step CPU to detect chip functions unusual, perhaps CPU detect the current working procedure of chip and target program to be loaded inconsistent, so CPU is this chip pressure loaded targets program in this step.
Those of ordinary skill in the art can understand, and for different chips, its concrete target program loading procedure is not quite similar.For example, for fpga chip, the target program data transmit with fixing data frame format, and a frame connects the transmission of a frame.The length of its Frame has than big-difference along with the difference of device model.After loading beginning, the counter of built-in chip type is just made plus coujnt since 0 to the data that are sent to chip internal, when the value of counting and target program big or small identical, represents that then target program loads end.Target program is in the middle of the process that loads, and the target program data that the FPGA self-verifying loads are in case find mistake, the just loading of interrupt targets program immediately, and export error flag and give CPU, tell CPU that loading procedure stops, CPU need restart loading procedure.
In step 230, CPU reinitializes chip.This step is used to carry out necessary initialization operation, and the execution time of the chip that resets is far fewer than the time of loading procedure.
Need to prove that this step is optionally, reinitializes the operation of chip, as the chip that resets, and can decide according to actual conditions.And generally be not quite similar for its initialization procedure of dissimilar chips.For example, for fpga chip, CPU is powering up/reset circuit of flip chip inside at first, and then FPGA removes the configurable memory in the sheet, and judge the working method of chip by the level that detects pin.Output pin need be set to high-impedance state during chip initiation, general fpga chip is built-in with delay circuit, makes chip have time enough to finish initialization operation.Need to prove that in chip target program loading procedure, if apply effective chip reset signal, then the chip target program will be interrupted, and chip is reinitialized, and reload the chip target program.After chip entered normal operating conditions, if extraneous the pressure applies effective reset signal, then chip also can reinitialize.
Though by reference some preferred embodiment of the present invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that, can do various changes to it in the form and details, and the spirit and scope of the present invention that do not depart from appended claims and limited.
Claims (8)
1. a chip program loading method is characterized in that, comprises following steps:
Whether B is consistent with target program to be loaded according to the unique identification detection chip present procedure of program file, if it is inconsistent, execution in step C then, wherein, described unique identification is the attribute of program file itself or the information of itself being derived by this program file;
C is that described chip loads described target program.
2. chip program loading method according to claim 1 is characterized in that, described method also comprises following steps:
D is to described chip initiation, and after carrying out described step C, carries out described step D.
3. chip program loading method according to claim 2 is characterized in that, when the present procedure of judging described chip among the described step B is consistent with target program to be loaded, and execution in step D.
4. according to claim 1 or 3 described chip program loading methods, it is characterized in that described unique identification is the combination in any of any one or they in the digital digest, digital signature, contents of program check field, program size, program structure date and time of program.
5. chip program loading method according to claim 4 is characterized in that, described chip is field programmable gate array or Erasable Programmable Logic Device or digital signal processor.
6. chip program loading method according to claim 5 is characterized in that, described method also comprises following steps:
Whether A central processing unit detection chip function is normal, if, execution in step B then, otherwise, execution in step C.
7. chip program loading method according to claim 6, it is characterized in that, in the described steps A,, carry out the detection that read-write operation is finished chip functions by detected register to the known address if described chip is field programmable gate array or Erasable Programmable Logic Device.
8. chip program loading method according to claim 6, it is characterized in that, in the described steps A,, then carry out the detection that loopback test between digital signal processor-central processing unit is finished chip functions by communication link if described chip is a digital signal processor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100830259A CN100342335C (en) | 2004-09-23 | 2004-09-23 | Chip program loading method |
| PCT/CN2005/001512 WO2006032196A1 (en) | 2004-09-23 | 2005-09-20 | A chip program loading method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100830259A CN100342335C (en) | 2004-09-23 | 2004-09-23 | Chip program loading method |
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| CN1752930A CN1752930A (en) | 2006-03-29 |
| CN100342335C true CN100342335C (en) | 2007-10-10 |
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| CNB2004100830259A Expired - Fee Related CN100342335C (en) | 2004-09-23 | 2004-09-23 | Chip program loading method |
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| CN (1) | CN100342335C (en) |
| WO (1) | WO2006032196A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI499929B (en) * | 2012-03-09 | 2015-09-11 | Nuvoton Technology Corp | Programming system |
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| US8429218B2 (en) * | 2006-04-06 | 2013-04-23 | International Business Machines Corporation | Process restart on a compute node |
| CN101441574B (en) * | 2007-11-20 | 2011-10-26 | 中兴通讯股份有限公司 | Multiple-FPGA logical loading method in embedded system |
| CN103677876A (en) * | 2012-09-12 | 2014-03-26 | 中兴通讯股份有限公司 | Manufacturing and installing method, device and system of software installation package |
| CN104102563A (en) * | 2014-07-10 | 2014-10-15 | 浪潮(北京)电子信息产业有限公司 | Method and device for finding MCA (machine check architecture) errors of server system |
| CN109120432B (en) * | 2018-07-18 | 2021-10-15 | 北京奇艺世纪科技有限公司 | Fault server positioning method and device |
| CN109032660A (en) * | 2018-07-31 | 2018-12-18 | 北京城市网邻信息技术有限公司 | A kind of generation method of VersionCode, device, electronic equipment and storage medium |
| CN112306402B (en) * | 2020-07-31 | 2024-05-07 | 神州融安科技（北京）有限公司 | Program execution method, electronic device, and computer-readable storage medium |
| CN112685089A (en) * | 2020-08-06 | 2021-04-20 | 艾德克斯电子（南京）有限公司 | Communication board system suitable for various machines and working method |
| CN112711560B (en) * | 2021-02-10 | 2023-05-26 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Reconstruction method for single-point connection of ZYNQ chip to rapidIO bus |
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| CN1476217A (en) * | 2002-08-16 | 2004-02-18 | 深圳市中兴通讯股份有限公司 | Single board edition automatic loading method |
| CN1490721A (en) * | 2002-10-18 | 2004-04-21 | 华为技术有限公司 | Loading method for digital signal processing program |
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| JP2786574B2 (en) * | 1992-05-06 | 1998-08-13 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Method and apparatus for improving the performance of out-of-order load operations in a computer system |
| TW368626B (en) * | 1998-04-17 | 1999-09-01 | Winbond Electronics Corp | Microprocessor with self-programmed embedded flash memory and programming method |
| CN1200347C (en) * | 2002-07-08 | 2005-05-04 | 华为技术有限公司 | Method for implementing dynamic loading of single board chip FIRMWARE program |
| CN1225691C (en) * | 2002-07-08 | 2005-11-02 | 华为技术有限公司 | Method for dynamic loading program |
| CN1223123C (en) * | 2002-11-21 | 2005-10-12 | 华为技术有限公司 | Method for upgrading TRX monoboard program in WCDMA |
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- 2004-09-23 CN CNB2004100830259A patent/CN100342335C/en not_active Expired - Fee Related
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2005
- 2005-09-20 WO PCT/CN2005/001512 patent/WO2006032196A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1160666A2 (en) * | 2000-04-27 | 2001-12-05 | Ncr International Inc. | Switching versions of software in a system background |
| CN1476217A (en) * | 2002-08-16 | 2004-02-18 | 深圳市中兴通讯股份有限公司 | Single board edition automatic loading method |
| CN1490721A (en) * | 2002-10-18 | 2004-04-21 | 华为技术有限公司 | Loading method for digital signal processing program |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI499929B (en) * | 2012-03-09 | 2015-09-11 | Nuvoton Technology Corp | Programming system |
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| CN1752930A (en) | 2006-03-29 |
| WO2006032196A1 (en) | 2006-03-30 |
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