CN100336169C - Manufacturing method of induction element and its structure - Google Patents
Manufacturing method of induction element and its structure Download PDFInfo
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- CN100336169C CN100336169C CNB2004100050416A CN200410005041A CN100336169C CN 100336169 C CN100336169 C CN 100336169C CN B2004100050416 A CNB2004100050416 A CN B2004100050416A CN 200410005041 A CN200410005041 A CN 200410005041A CN 100336169 C CN100336169 C CN 100336169C
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 230000006698 induction Effects 0.000 title claims description 20
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000001939 inductive effect Effects 0.000 claims description 260
- 229910052751 metal Inorganic materials 0.000 claims description 185
- 239000002184 metal Substances 0.000 claims description 185
- 239000000463 material Substances 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 239000007787 solid Substances 0.000 claims description 9
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 99
- 239000004020 conductor Substances 0.000 description 16
- 238000001459 lithography Methods 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 125000002915 carbonyl group Chemical group [*:2]C([*:1])=O 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BGOFCVIGEYGEOF-UJPOAAIJSA-N helicin Chemical compound O[C@@H]1[C@@H](O)[C@H](O)[C@@H](CO)O[C@H]1OC1=CC=CC=C1C=O BGOFCVIGEYGEOF-UJPOAAIJSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
The present invention relates to a manufacture method and a structure of an inductance element. The inductance element is erected onto a substrate; a flat dielectric layer is collocated on the substrate. The structure of the inductance element comprises a first inductance figure, a second inductance figure and a third inductance figure, wherein the first inductance figure is collocated on the dielectric layer. In addition, the second inductance figure is collocated on the first inductance figure, and is also electrically connected with the first inductance figure. Besides, the third inductance figure is collocated on the second inductance figure, and is electrically connected with the second inductance figure. The first inductance figure, the second inductance figure and the third inductance figure have similar figures. Because the inductance element uses multiple layers of inductance figures to increase thickness, the impedance of the inductance element can be reduced.
Description
Technical field
The invention relates to a kind of manufacture method and structure of semiconductor element, and particularly relevant for a kind of manufacture method and structure of inductance element.
Background technology
In integrated circuit, inductance element is a kind of important element, and these inductance element patterns generally are to be circular or square helical metal coil, and the range of application of these inductance elements can be described as considerably extensive.With the application of high frequency, its quality requirements for inductance element is higher, the meaning promptly be applied in this field inductance element its have higher Q value.For example in the application of wireless telecommunications, the Q value of inductance element must reach about 60.Above-mentioned Q value is defined as follows:
Q＝ω
0L/R (1)
ω wherein
0Be the resonant angular frequency (resonant angular frequency) of inductance element, R is the resistance of inductance element, and L is the inductive component values of wire coil.
By (1) formula as can be known, down fixing at L, the Q value can descend and improves along with the increase of resonant angular frequency and/or resistance, wherein resistance again with square being directly proportional of current density, so being the sectional area that increases wire coil, one of method that improves the Q value reduces the wire coil current density, reduce the resistance of wire coil in this way, reach the purpose that improves the Q value.
So, in semiconductor process,, can finish by the mode of overstriking plain conductor width if will make the high Q value inductance element to increase the plain conductor sectional area.But when if the width of plain conductor is too big, can concentrate the corner that is distributed in plain conductor because of charge tends again, and make the sectional area that plain conductor increased can't reach the effect that reduces metallic current density, also just can't improve the Q value of the inductance element of forming by plain conductor.Therefore, the general inductance element that can produce with semiconductor process, its Q value can only arrive about 10 at most.
And most inductance element all is disposed at the protective layer below of wafer, so inductance element is very near silicon substrate (＜10 μ m are following); therefore, under the high-frequency of using high-frequency component, silicon substrate can become conductor; and consume lot of energy, make the quality of inductance element reduce.
Even, though known technology proposes to form the three-dimensional inductance element that is made of plain conductor/interlayer hole/plain conductor by the metal interconnecting operation, yet, this inductance element has too the problem near silicon substrate equally, moreover interlayer hole layer wherein is subjected to process technology limit, and the method for there is no is made into to metal carbonyl conducting layer has similar figure, and only can form most connectors, thereby can't further improve the Q value of inductance element with double layer of metal conductor layer about connecting.So, how to address the above problem, and quality and its Q value of raising inductance element are the problems that present operation is concerned about.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of inductance element is being provided, and this method can additionally not increase under the process situation, reduces the impedance of inductance element, and improves the Q value of inductance element.
Another object of the present invention provides a kind of inductance element structure, and this inductance element structure can make the inductance element structure away from silicon substrate, to reduce silicon substrate the magnetic conduction that inductance element was caused is disturbed, to improve wafer usefulness.
A further object of the present invention provides a kind of inductance element structure, and this inductance element is to have the thickness of homogeneous for sandwich construction and whole inductance element, and can increase the Q value of inductance element.
The present invention proposes a kind of manufacture method of inductance element, this method is that framework is on substrate, at least be formed with first dielectric layer on this substrate, the manufacture method of this inductance element is at first to form the patterned the first metal layer and first inductive graph on first dielectric layer simultaneously.Afterwards, form patterned second dielectric layer on first dielectric layer, to cover the first metal layer, first inductive graph and first dielectric layer, and this second dielectric layer has several first openings and several second openings, wherein first opening exposes the first metal layer, and second opening exposes first inductive graph.Then, in first opening and second opening, insert metal,, and in second opening, form second inductive graph with while formation second metal level in first opening, wherein second metal level is electrically connected with the first metal layer, and second inductive graph is electrically connected with first inductive graph.Then, on second metal level, form patterned the 3rd metal level, and on second inductive graph, form the 3rd inductive graph simultaneously, wherein the 3rd metal level is electrically connected with second metal level, and the 3rd inductive graph is electrically connected with second inductive graph, and first inductive graph, second inductive graph have similar figure to the 3rd inductive graph.
Therefore as can be known by above-mentioned operation, the present invention utilizes the multilayer inductor figure to increase the thickness of the plain conductor of inductance element, so can reduce the resistance of inductance element, and increase its Q value, in addition, in operation of the present invention, do not need additionally to increase the operation that process just can be finished inductance element, therefore method of the present invention can be said so suitable easy.
The present invention propose a kind of inductance element be framework on substrate, dispose the dielectric layer of planarization on this substrate at least.This inductance element structure comprises one first inductive graph, one second inductive graph and one the 3rd inductive graph, and wherein first inductive graph is disposed on the dielectric layer.In addition, second inductive graph is disposed on first inductive graph, and second inductive graph is electrically connected with first inductive graph.In addition, the 3rd inductive graph is disposed on second inductive graph, and the 3rd inductive graph is electrically connected with second inductive graph, and wherein first inductive graph, second inductive graph have similar figure to the 3rd inductive graph.
In the manufacture method and structure of above-mentioned inductance element, first inductive graph, second inductive graph and the 3rd inductive graph form simultaneously with topmost metal layer, metal plug, the metal pad of multiple layer metal internal connection-wire structure respectively.
In the manufacture method and its structure of above-mentioned inductance element, its first inductive graph, second inductive graph and the 3rd inductive graph constitute a three-dimensional induction structure, for the symmetrical expression induction structure, this inductance element can have a juxtaposition zone, and, be that the inductive graph of winning is not connected by second inductive graph with the 3rd inductive graph in the juxtaposition location of inductive graph for fear of the inductance element short circuit.
The present invention proposes the manufacture method of another kind of inductance element, this inductance element framework is on a substrate, at least be formed with one first dielectric layer on this substrate, this method is to form a patterned the first metal layer and one second inductive graph in first dielectric layer simultaneously, then on first dielectric layer, form patterned one second dielectric layer, to cover the first metal layer, first inductive graph and first dielectric layer, and second dielectric layer has most first openings and most second openings, wherein first opening exposes the first metal layer, and second opening exposes first inductive graph, on second dielectric layer, form one second metal level that fills up first opening then, and one second inductive graph that second opening is filled up in formation on second dielectric layer simultaneously, wherein second metal level is electrically connected with the first metal layer, and second inductive graph is electrically connected with first inductive graph.
In the manufacture method of above-mentioned inductance element, first inductive graph, second inductive graph and the 3rd inductive graph are to form simultaneously with topmost metal layer, metal plug, the metal pad of multiple layer metal internal connection-wire structure respectively, and metal plug and metal pad (second inductive graph and the 3rd inductive graph) are to form in same deposition, lithography step.
In the manufacture method of above-mentioned inductance element, its first inductive graph, with second inductive graph constitute a three-dimensional induction structure, for the symmetrical expression induction structure, this inductance element can have a juxtaposition zone, and, be that the inductive graph of winning is not connected to each other with second inductive graph in the juxtaposition location of inductive graph for fear of the inductance element short circuit.
Therefore as can be known by the manufacture method of above-mentioned inductance element and structure, the present invention utilizes the inductive graph of multilayer to increase the thickness of the plain conductor of inductance element, so can reduce the resistance of inductance element, more can increase its Q value, and then improve the quality of inductance element.
And,, thereby can further effectively increase its Q value because each layer of multi-layer inductive element of the present invention has similar figure, thereby makes whole inductance element have the thickness of homogeneous.
And this inductance element can be made with the operation of metal pad, and therefore formed inductance element is more known further from substrate, disturbs for the magnetic conduction that inductance element caused so can reduce substrate, to improve wafer usefulness.
In addition, owing to the present invention can finish in same deposition, lithography step corresponding to the inductive graph of metal plug and metal pad part, so operation is simplified.
Moreover, owing to the inductive graph corresponding to metal plug and metal pad part is an identical materials, therefore can reduce the contact impedance that the different materials contact is caused, thereby increase the Q value of inductance element.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, several preferred embodiments cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 is the structure schematic top plan view according to a kind of inductance element of the first embodiment of the present invention.
Fig. 2 A to Fig. 2 C is the making flow process generalized section of Fig. 1 along I to I '.
Fig. 3 A to Fig. 3 C is the making flow process generalized section of Fig. 1 along II to II '.
Fig. 4 A to Fig. 4 C is the schematic top plan view of the inductive graph of Fig. 1, and wherein Fig. 4 A is inductive graph 104a, and Fig. 4 B is inductive graph 110b, and Fig. 4 C is inductive graph 112b.
Fig. 5 is the structure schematic top plan view according to a kind of inductance element of the second embodiment of the present invention.
Fig. 6 A to Fig. 6 C is the making flow process generalized section of Fig. 5 along III to III '.
Fig. 7 A to Fig. 7 C is the schematic top plan view of the inductive graph of Fig. 5, and wherein Fig. 7 A is inductive graph 204a, and Fig. 7 B is inductive graph 210b, and Fig. 7 C is inductive graph 214b.
The drawing reference numeral explanation
100,200: substrate
101,103,105: the zone
102,106,202,206: dielectric layer
104a, 110a, 112a, 204a, 210a, 212a, 214a: metal level
104b, 110b, 112b, 204b, 210b, 212b, 214b: inductive graph
108a, 108b, 208a, 208b: opening
Embodiment
First embodiment
Fig. 1 is a kind of schematic top plan view that form the structure of inductance element of expression according to first embodiment of the invention; Fig. 2 A to Fig. 2 C is by the making flow process generalized section of I-I ' in the presentation graphs 1; Fig. 3 A to Fig. 3 C is by the manufacturing process generalized section of II-II ' in the presentation graphs 1,101,103,105 the zone that is wherein indicated in Fig. 1 is corresponding mutually with Fig. 2 A to Fig. 2 C and Fig. 3 A to Fig. 3 C, and zone 105 parts overlapping with zone 103 that are expression zones 101.And in present embodiment, it is disclosed to be a symmetrical round screw thread formula inductance element, and this inductance element has a juxtaposition zone.
Simultaneously with reference to Fig. 1, Fig. 2 A and Fig. 3 A, the making of inductance element at first provides substrate 100, at least be formed with dielectric layer 102 on this substrate 100, its material for example is general known dielectric materials such as silica, silicon nitride, advanced low-k materials, its formation method is for example earlier with chemical vapour deposition technique, dielectric layer 102 and then is carried out planarisation step with chemical mechanical milling method on substrate 100.The known dielectric layer 102 of those skilled in the art can be the structure of most layers herein, and can be formed with most element and metal interconnecting on substrate 100 with in the dielectric layer 102.
Then, in dielectric layer 102, form patterned metal level 104a and inductive graph 104b simultaneously, wherein the vertical view of inductive graph 104b is shown in Fig. 4 A, and metal level 104a for example is the topmost metal layer of the multiple layer metal internal connection-wire structure on the substrate 100, also promptly in the process of carrying out the metal interconnecting operation, can in same processes, form inductive graph 104b.
In addition, the material of metal level 104a and inductive graph 104b for example is a copper, its formation method for example is with general known damascene operation, at first in dielectric layer 102, form patterned opening (not shown), again metal material is inserted in the opening to form patterned metal level 104a and inductive graph 104b.
Then, simultaneously with reference to Fig. 1, Fig. 2 B and Fig. 3 B, on dielectric layer 102, form patterned dielectric layer 106, to cover metal level 104a, inductive graph 104b and dielectric layer 102.In addition, have more several openings 108a, 108b in the dielectric layer 106, its split shed 108a exposes metal level 104a, and opening 108b exposes inductive graph 104b.
In addition, the method that forms dielectric layer 106 for example is to form the one dielectric layer (not shown) on dielectric layer 102 comprehensively, to cover metal level 104a, inductive graph 104b and dielectric layer 102.Carry out cmp afterwards, so that this dielectric layer global planarization.Then, utilize the lithography operation of known technology to come graphical this dielectric layer, to define dielectric layer 106 with most opening 108a, 108b.
In addition, what deserves to be mentioned is, in order to avoid the inductance element short circuit in design, when graphical above-mentioned dielectric layer forms opening 108b, do not form opening 108b in zone 101 and zone 103, promptly the inductive graph (not shown) of the formed the superiors can be by the inductive graph 104b in the inductive graph (not shown) join domain 101 and regional 103 in intermediate layer in subsequent handling for meaning, and except zone 101 and regional 103, the graphics track of opening 108b is similar to the figure of inductive graph 104b.
Afterwards, continue the while, in several openings 108a, 108b, insert metal,, and in opening 108b, form inductive graph 110b with while formation metal level 110a in opening 108a with reference to Fig. 1, Fig. 2 B and Fig. 3 B.Wherein, formed metal level 110a for example is the usefulness as metal plug, and it is to be electrically connected with metal level 104a.
In addition, the mode that forms inductive graph 110b and metal level 110a for example is to form layer of metal layer (not shown) in opening 108a, 108b and on the dielectric layer 106, wherein metal material for example is a tungsten, and its formation method for example is Low Pressure Chemical Vapor Deposition or sputtering method.Afterwards, carry out planarisation step again, removing the outer metal material of opening 108a, 108b, and form metal level 110a and inductive graph 110b.Therefore, this inductive graph 110b be with metal level 110a (for example: metal plug) in same step, form simultaneously.
And, the vertical view of above-mentioned formed inductive graph 110b is shown in Fig. 4 B, it is to be electrically connected with inductive graph 104b, and, except avoiding the inductance element short circuit in design, and do not form outside the inductive graph 110b in (zone 101,103,105) near the plain conductor overlapping region, inductive graph 110b has the figure similar to inductive graph 104b.
Continue it, with reference to Fig. 1, Fig. 2 C and Fig. 3 C, go up the patterned metal level 112a of formation simultaneously, and upward form inductive graph 112b in inductive graph 110b simultaneously in metal level 110a, wherein metal level 112a for example is the usefulness as metal pad, and it is to be electrically connected with metal level 110a.
In addition, the material of metal level 112a and inductive graph 112b for example is an aluminium, and its formation method for example is to form comprehensive ground metal level (not shown) on dielectric layer 106, and its generation type for example is a physical vaporous deposition.Then, utilize the technology of known lithography, graphically this metal level is to form metal level 112a and inductive graph 112b.Therefore, inductive graph 112b be with metal level 112a (for example: metal pad) in same step, form simultaneously.
And, the vertical view of above-mentioned formed inductive graph 112b is shown in Fig. 4 C, it is to be electrically connected with inductive graph 110b, and, except avoiding the inductance element short circuit in design, only be formed with outside the inductive graph 112b in zone 105 and regional 103 places, inductive graph 112b has the figure similar to inductive graph 110b, 104b.
What deserves to be mentioned is, the inductive graph 104b of above-mentioned multilayer, 110b and 112b constitute a three-dimensional induction structure, its vertical view as shown in Figure 1, and juxtaposition zone that should the solid induction structure (zone 105) is by inductive graph 104b, dielectric layer 106 constitutes with inductive graph 112b, and be not connected with inductive graph 112b by inductive graph 110b at the inductive graph 104b in this zone 105, do above-mentioned design via juxtaposition zone at three-dimensional induction structure, when electric current is mobile along this solid induction structure, when flowing through the juxtaposition zone for the first time, electric current only can flow along first inductive graph, and when electric current is flowed through the juxtaposition zone for the second time, only flowing, thereby the problem that can avoid inductive graph to be short-circuited in the juxtaposition zone along the 3rd inductive graph.
In addition, the present invention is not limited to above-mentioned process, above-mentioned metal level 110a, 112a, and the inductive graph 110b, the 112b that form simultaneously more can finish with known dual damascene operation.
Therefore as can be known by above-mentioned operation, the present invention utilizes the inductive graph of multilayer to increase the thickness of the plain conductor of inductance element, so can reduce the resistance of inductance element, and increase its Q value, in addition, in operation of the present invention, do not need additionally to increase the operation that process just can be finished inductance element, therefore method of the present invention can be said so suitable easy.
Even, in operation of the present invention, in order to form the opening 108b of inductive graph 110b, be to form with opening 108a in order to the connector that forms metal pad, because opening 108a, 108b are the superiors that are positioned at metal interconnecting structure, therefore the operation restriction is few, thereby makes opening 108b to have similar figure to inductive graph 104b.
Below the structure of utilizing the inductance element that above-mentioned operation made comes out is illustrated, continue simultaneously with reference to Fig. 1, Fig. 2 C and Fig. 3 C, wherein Fig. 1 is the schematic top plan view for inductance element of the present invention, Fig. 2 C is the generalized section of Fig. 1 along I to I ', Fig. 3 C is the generalized section of Fig. 1 along II to II ', 101,103,105 the zone that is wherein indicated in Fig. 1 is corresponding mutually with Fig. 2 C and Fig. 3 C, and zone 105 parts overlapping with zone 103 that are expression zones 101.
The structure of inductance element of the present invention be framework on substrate 100, dispose dielectric layer 102 at least on this substrate 100.This inductance element structure comprises three layers of inductive graph 104b, 110b, 112b.
Wherein, inductive graph 104b is disposed on the dielectric layer 102, the vertical view of this inductive graph 104b is shown in Fig. 4 A, on dielectric layer 102, more dispose metal level 104a, that is metal level 104a is disposed on the identical rete with inductive graph 104b, metal level 104a for example is the topmost metal layer of the multiple layer metal internal connection-wire structure on the substrate 100, and the material of metal level 104a and inductive graph 104b for example is a copper.What deserves to be mentioned is that in zone 103, except the zone 105 with regional 101 juxtapositions disposes the inductive graph 104b, remaining zone 103 there is no the configuration of inductive graph 104b.
In addition, inductive graph 110b is disposed on the inductive graph 104b, and the vertical view of this inductive graph 110b is shown in Fig. 4 B, except the juxtaposition zone, inductive graph 110b has similar figure to inductive graph 104b, and inductive graph 110b is electrically connected with inductive graph 104b.In addition, more dispose metal level 110a on metal level 104a, that is metal level 110a is disposed on the identical rete with inductive graph 110b, this metal level 110a for example is a metal plug, and the material of metal level 110a and inductive graph 110b for example is a tungsten.What deserves to be mentioned is, in zone 103 and zone 101 (zone 105 that comprises juxtaposition), there is no the configuration of inductive graph 110b.
In addition, inductive graph 112b is disposed on the inductive graph 110b, and the vertical view of this inductive graph 112b is shown in Fig. 4 C, except the juxtaposition zone, inductive graph 112b has similar figure to inductive graph 110b, 104b, and inductive graph 112b is electrically connected with inductive graph 110b.In addition, more dispose metal level 112a on metal level 110a, that is metal level 112a is disposed on the identical rete with inductive graph 112b, this metal level 112a for example is a metal pad 114.What deserves to be mentioned is that in zone 101, except the zone 105 with regional 103 juxtapositions disposes the inductive graph 112b, remaining zone 101 there is no the configuration of inductive graph 112b.
In addition, above-mentioned three layers inductive graph 104b, 110b, 112b constitute a three-dimensional induction structure, its vertical view as shown in Figure 1, and juxtaposition zone that should the solid induction structure (zone 105) is made of with inductive graph 112b inductive graph 104b, dielectric layer 106, and be not connected by inductive graph 110b with inductive graph 112b at the inductive graph 104b in this zone 105, so that the problem that inductive graph can not be short-circuited in the juxtaposition zone.
Second embodiment
Fig. 5 is the schematic top plan view of expression according to the structure of a kind of inductance element of second embodiment of the invention; Fig. 6 A to Fig. 6 C is by the making flow process generalized section of III-III ' in the presentation graphs 5.And in the present embodiment, its disclosed be a concentric screw type inductive element.
Simultaneously with reference to Fig. 5 and Fig. 6 A, the making of inductance element at first provides substrate 200, then on substrate 200, be formed with dielectric layer 202 at least, wherein this material for example is general known dielectric materials such as silica, silicon nitride, advanced low-k materials, its formation method is for example earlier with chemical vapour deposition technique, dielectric layer 202 and then is carried out planarisation step with chemical mechanical milling method on substrate 200.Those of ordinary skill known dielectric layer 202 in present technique field can be the structure of most layers herein, and can be formed with most element and metal interconnecting on substrate 200 with in the dielectric layer 202.
Then, in dielectric layer 202, form patterned metal level 204a and inductive graph 204b simultaneously, wherein the vertical view of inductive graph 204b is shown in Fig. 7 A, and metal level 204a for example is the topmost metal layer of the multiple layer metal internal connection-wire structure on the substrate 200, also promptly in the process of carrying out the metal interconnecting operation, can in same processes, form inductive graph 204b.
In addition, the material of metal level 204a and inductive graph 204b for example is a copper, its formation method for example is with general known damascene operation, at first in dielectric layer, form patterned opening (not shown), again metal material is inserted in the opening to form patterned metal level 204a and inductive graph 204b.
Then, simultaneously with reference to Fig. 5 and Fig. 6 B, on dielectric layer 202, form patterned dielectric layer 206, to cover metal level 204a, inductive graph 204b and dielectric layer 202.In addition, have more several openings 208a, 208b in the dielectric layer 206, its split shed 208a exposes metal level 204a, and opening 208b exposes inductive graph 204b, and, the graphics track of opening 208b is similar to the figure of inductive graph 204b, that is to say along inductive graph 204b to form spiral helicine opening 208b.
In addition, the method that forms dielectric layer 206 for example is to form the one dielectric layer (not shown) on dielectric layer 202 comprehensively, to cover metal level, inductive graph 204 and dielectric layer 202.Carry out cmp afterwards, so that this dielectric layer global planarization.Then, utilize the lithography operation of known technology to come graphical this dielectric layer, to define dielectric layer 206 with most opening 208a, 208b.
Afterwards, continue simultaneously with reference to Fig. 5 and Fig. 6 C, on dielectric layer 206, form metal level 210a and the inductive graph 210b that fills up opening 208a, 208b, wherein metal level 210a is electrically connected with metal level 204a, and can be considered by metal level 212a in the opening and the metal level 214a on the dielectric layer 206 and constituted, and the metal level 212a among the opening 208a for example is the usefulness that can be used as metal plug, and the metal level 214a on the dielectric layer 206 for example is the usefulness that can be used as metal pad.
In addition, forming the mode of inductive graph 210b and metal level 210a, for example is to form layer of metal layer (not shown) in opening 208a, 208b and on the dielectric layer 206, and wherein metal material for example is an aluminium, and its formation method for example is a physical vaporous deposition.Afterwards, utilize the technology of known lithography, graphically this metal level is to form metal level 210a (212a, 214a) and inductive graph 210b (212b, 214b).Therefore, inductive graph 210b forms in same step simultaneously with metal level 210a.
Same, because the present invention utilizes the inductive graph of multilayer to increase the thickness of the plain conductor of inductance element, therefore can reduce the resistance of inductance element, and increase its Q value, in addition, in operation of the present invention, do not need additionally to increase the operation that process just can be finished inductance element, therefore method of the present invention can be said so suitable easy.
Even, in operation of the present invention, in order to form the opening 208b of inductive graph 210b, be to form with opening 208a in order to the connector that forms metal pad, because opening 208a, 208b are the superiors that are positioned at metal interconnecting structure, therefore the operation restriction is few, thereby makes opening 208b to have similar figure to inductive graph 204b.
Moreover, in present embodiment, because metal level 212a, 214a and the inductive graph 212b, the 214b that form simultaneously can finish in same deposition, lithography step, therefore comparing with first embodiment is to simplify working process, even, for inductive graph 212b, 214b, owing to be identical materials, therefore can reduce the contact impedance that the different materials contact is caused, increase its Q value.Moreover, for inductive graph 212b,, adopt tungsten in comparison with first embodiment owing to can adopt aluminium, be to reduce contact impedance, increase its Q value.
Below be that the structure of utilizing the inductance element that above-mentioned operation made comes out is illustrated, continue simultaneously with reference to Fig. 5 and Fig. 6 C that wherein Fig. 5 is the schematic top plan view for inductance element of the present invention, Fig. 6 C is the generalized section of Fig. 5 along III to III '.
The structure of inductance element of the present invention be framework on substrate 200, dispose dielectric layer 202 at least on this substrate 200.This inductance element structure comprises inductive graph 204b, 210b.
Wherein, inductive graph 204b is disposed on the dielectric layer 202, the vertical view of this inductive graph 204b is shown in Fig. 7 A, and on dielectric layer 202, more dispose metal level 204a, also be that metal level 204a is disposed on the identical rete with inductive graph 204b, metal level 204a for example is the topmost metal layer to the multiple layer metal internal connection-wire structure at the end 200, and the material of metal level 204a and inductive graph 204b for example is a copper.
Certainly, the form of above-mentioned inductance element be not be defined in as shown in Figure 1 symmetrical round screw thread style or circular concentric helical pattern shown in Figure 5, other for example symmetrical square spiral patterns or concentric square helical pattern also can utilize the present invention to be finished.
Even, in the symmetrical round screw thread formula inductance element of first embodiment, its first inductive graph, second inductive graph, the 3rd inductive graph (topmost metal layer, metal plug, metal pad) formed by different deposition procedures, yet the present invention is not limited thereto, the inductance element of first embodiment can also be as second embodiment, make second inductive graph, the 3rd inductive graph (metal plug, metal pad) in same deposition, finish in the lithography step, furthermore, the inductance element of arbitrary form can both be by first embodiment or the disclosed operation of second embodiment to form.
In sum, by said structure as can be known, the present invention utilizes the inductive graph of multilayer to increase the thickness of the plain conductor of inductance element, so can reduce the resistance of inductance element, more can increase its Q value, and then improves the quality of inductance element.
And,, thereby can further effectively increase its Q value because each layer of multi-layer inductive element of the present invention has similar figure, thereby makes whole inductance element structure have the thickness of homogeneous.
And because this inductance element can be made with the operation that forms metal pad, therefore formed structure is more known further from substrate, disturbs for the magnetic conduction that inductance element caused so can reduce substrate, to improve wafer usefulness.
In addition, owing to the present invention can finish in same deposition, lithography step corresponding to the inductive graph of metal plug and metal pad part, so operation is simplified.
Moreover, owing to the inductive graph corresponding to metal plug or metal pad part is an identical materials, therefore can reduce the contact impedance that the different materials contact is caused, thereby increase the Q value of inductance element.
Though the present invention with several preferred embodiments openly as above; yet it is not in order to limit the present invention; any present technique field those of ordinary skill; without departing from the spirit and scope of the present invention; certainly can do some and change and retouching, so protection scope of the present invention is when looking with being as the criterion that the claim scope of applying for a patent is defined.
Claims (17)
1. the manufacture method of an inductance element, this inductance element framework is formed with one first dielectric layer at least on this substrate on a substrate, and this method comprises:
In this first dielectric layer, form a patterned the first metal layer and one first inductive graph simultaneously;
On this first dielectric layer, form patterned one second dielectric layer, to cover this first metal layer, this first inductive graph and this first dielectric layer, and this second dielectric layer has most first openings and most second openings, wherein these first openings expose this first metal layer, and these second openings expose this first inductive graph;
In these first openings and these second openings, insert a metal, in these first openings, to form one second metal level simultaneously, and in these second openings, form one second inductive graph, wherein this second metal level is electrically connected with this first metal layer, and this second inductive graph is electrically connected with this first inductive graph; And
On this second metal level, form patterned one the 3rd metal level, and on this second inductive graph, form one the 3rd inductive graph simultaneously, wherein the 3rd metal level is electrically connected with this second metal level, and the 3rd inductive graph is electrically connected with this second inductive graph.
Wherein first inductive graph, second inductive graph have similar figure to the 3rd inductive graph.
2. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: this first metal layer comprises the topmost metal layer of the multiple layer metal internal connection-wire structure on this substrate.
3. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: this second metal level comprises metal plug.
4. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: the 3rd metal level comprises metal pad.
5. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: this inductance element comprises symmetrical round screw thread formula inductance element or circular concentric screw type inductive element.
6. the manufacture method of inductance element as claimed in claim 1, it is characterized in that: this first inductive graph, this second inductive graph and the 3rd inductive graph constitute a three-dimensional induction structure, and should have a juxtaposition zone by the solid induction structure, and in this juxtaposition zone, this first inductive graph is not connected by this second inductive graph with the 3rd inductive graph, so that electric current is when this solid induction structure flows, when flowing through for the first time this juxtaposition zone, only flow, and when flowing through for the second time this juxtaposition zone, only flow along the 3rd inductive graph along this first inductive graph.
7. inductance element, this inductance element framework disposes a dielectric layer at least on this substrate on a substrate, and this structure comprises:
One is disposed at first inductive graph in this dielectric layer;
One is disposed at second inductive graph on this first inductive graph, and this second inductive graph is electrically connected with this first inductive graph; And
One is disposed at the 3rd inductive graph on this second inductive graph, and the 3rd inductive graph is electrically connected with this second inductive graph,
Wherein first inductive graph, second inductive graph have similar figure to the 3rd inductive graph,
This first inductive graph, this second inductive graph and the 3rd inductive graph constitute a three-dimensional induction structure, and should have a juxtaposition zone by the solid induction structure, in described juxtaposition location, this first inductive graph is not connected by this second inductive graph with the 3rd inductive graph, so that electric current is when this solid induction structure flows, when flowing through for the first time this juxtaposition zone, only flow, and when flowing through for the second time this juxtaposition zone, only flow along the 3rd inductive graph along this first inductive graph.
8. inductance element as claimed in claim 7 is characterized in that: the patterned the first metal layer on this first inductive graph and this substrate is same one deck, and this first metal layer comprises the topmost metal layer of the multiple layer metal internal connection-wire structure on this substrate.
9. inductance element as claimed in claim 7 is characterized in that: patterned one second metal level on this second inductive graph and this substrate is same one deck, and this second metal level comprises metal plug.
10. inductance element as claimed in claim 7 is characterized in that: patterned one the 3rd metal level on the 3rd inductive graph and this substrate is same one deck, and the 3rd metal level comprises metal pad.
11. inductance element as claimed in claim 7 is characterized in that: this inductance element comprises symmetrical round screw thread formula inductance element or circular concentric screw type inductive element.
12. the manufacture method of an inductance element, this inductance element framework are formed with one first dielectric layer at least on this substrate on a substrate, this method comprises:
In this first dielectric layer, form a patterned the first metal layer and one first inductive graph simultaneously;
On this first dielectric layer, form patterned one second dielectric layer, to cover this first metal layer, this first inductive graph and this first dielectric layer, and this second dielectric layer has most first openings and most second openings, wherein these first openings expose this first metal layer, and these second openings expose this first inductive graph; And
On this second dielectric layer, form one second metal level that fills up these first openings, and one second inductive graph that these second openings are filled up in formation on this second dielectric layer simultaneously, wherein this second metal level is electrically connected with this first metal layer, and this second inductive graph is electrically connected with this first inductive graph.
13. the manufacture method of inductance element as claimed in claim 12 is characterized in that: this first metal layer comprises the topmost metal layer of the multiple layer metal internal connection-wire structure on this substrate.
14. the manufacture method of inductance element as claimed in claim 12 is characterized in that: this second metal level comprises metal plug and metal pad.
15. the manufacture method of inductance element as claimed in claim 14 is characterized in that: the material of this second metal level and this second inductive graph comprises aluminium.
16. the manufacture method of inductance element as claimed in claim 12 is characterized in that: this inductance element comprises symmetrical round screw thread formula inductance element or circular concentric screw type inductive element.
17. the manufacture method of inductance element as claimed in claim 12, it is characterized in that: this first inductive graph and this second inductive graph constitute a three-dimensional induction structure, and should have a juxtaposition zone by the solid induction structure, and in this juxtaposition zone, this first inductive graph is not connected with this second inductive graph, so that electric current is when this solid induction structure flows, when flowing through for the first time this juxtaposition zone, only flow, and when flowing through for the second time this juxtaposition zone, only flow along this second inductive graph along this first inductive graph.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100050416A CN100336169C (en) | 2004-02-16 | 2004-02-16 | Manufacturing method of induction element and its structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100050416A CN100336169C (en) | 2004-02-16 | 2004-02-16 | Manufacturing method of induction element and its structure |
Publications (2)
| Publication Number | Publication Date |
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| CN1658370A CN1658370A (en) | 2005-08-24 |
| CN100336169C true CN100336169C (en) | 2007-09-05 |
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| CNB2004100050416A Expired - Lifetime CN100336169C (en) | 2004-02-16 | 2004-02-16 | Manufacturing method of induction element and its structure |
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| CN103489852B (en) * | 2013-09-30 | 2016-01-27 | 江阴长电先进封装有限公司 | A kind of encapsulating structure of radio frequency inductive and method for packing thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5446311A (en) * | 1994-09-16 | 1995-08-29 | International Business Machines Corporation | High-Q inductors in silicon technology without expensive metalization |
| JPH086514A (en) * | 1994-06-15 | 1996-01-12 | Yayoi Mitsuyoshi | Spring and poster pin with lead wire |
| US5656849A (en) * | 1995-09-22 | 1997-08-12 | International Business Machines Corporation | Two-level spiral inductor structure having a high inductance to area ratio |
| CN1378220A (en) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | Multilayer spiral inductor structure having high inductance and high quality factor |
| WO2003015110A1 (en) * | 2001-08-09 | 2003-02-20 | Koninklijke Philips Electronics N.V. | Planar inductive component and a planar transformer |
-
2004
- 2004-02-16 CN CNB2004100050416A patent/CN100336169C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH086514A (en) * | 1994-06-15 | 1996-01-12 | Yayoi Mitsuyoshi | Spring and poster pin with lead wire |
| US5446311A (en) * | 1994-09-16 | 1995-08-29 | International Business Machines Corporation | High-Q inductors in silicon technology without expensive metalization |
| US5656849A (en) * | 1995-09-22 | 1997-08-12 | International Business Machines Corporation | Two-level spiral inductor structure having a high inductance to area ratio |
| CN1378220A (en) * | 2001-03-29 | 2002-11-06 | 华邦电子股份有限公司 | Multilayer spiral inductor structure having high inductance and high quality factor |
| WO2003015110A1 (en) * | 2001-08-09 | 2003-02-20 | Koninklijke Philips Electronics N.V. | Planar inductive component and a planar transformer |
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|---|---|
| CN1658370A (en) | 2005-08-24 |
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