CN100336042C - Device and relative method for pre-reading data using north bridge circuit to maintain south bridge circuit - Google Patents
Device and relative method for pre-reading data using north bridge circuit to maintain south bridge circuit Download PDFInfo
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- CN100336042C CN100336042C CNB2004100785465A CN200410078546A CN100336042C CN 100336042 C CN100336042 C CN 100336042C CN B2004100785465 A CNB2004100785465 A CN B2004100785465A CN 200410078546 A CN200410078546 A CN 200410078546A CN 100336042 C CN100336042 C CN 100336042C
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Abstract
The present invention provides a device and a corresponding method which can use a north bridge circuit to assist and increase the pre-reading efficiency and the accuracy of a south bridge circuit. When a south bridge circuit carries out pre-reading and stores pre-reading data to the south bridge circuit, a north bridge circuit can store addresses of the pre-reading data; when a central processing unit carries out snoop or the central processing unit writes data in a quick access memory inside the central processing unit back to a system memory, whether the contents of the data corresponding to the addresses are updated in the quick access memory of the central processing unit is checked; if so, the north bridge circuit can remind the south bridge circuit to require the contents of the updated data again so as to guarantee that the pre-reading data in the south bridge circuit can be kept consistent with the data in the quick access memory of the central processing unit.
Description
Technical field
The invention provides a kind of device and correlation technique that improves pre-read performance of south bridge circuit and correctness, refer in particular to a kind of address that can write down pre-reading data with north bridge circuit to improve the device and the correlation technique of pre-read performance of south bridge and correctness.
Background technology
Computer system is one of most important hardware foundation of modernized information society, how to improve the task performance and the correctness of computer system, also becomes one of emphasis of information manufacturer research and development.
Computer system can be provided with central processing unit, includes the chipset of north and south bridge circuit, system storage and other peripherals etc.The processing and the computing of central processing unit master control data, system storage are used for writing down the required data of central processing unit duration of work.North bridge circuit is electrically connected to central processing unit and system storage, and south bridge circuit then can be electrically connected to each peripherals by bus (as the PC1 bus); And just can coordinate exchanges data between central processing unit, system storage and each peripherals by the chipset that the north and south bridge circuit makes up out.For instance, when reading the data of some given address in the peripherals (as hard disk unit, optical disc apparatus etc.) of south bridge circuit will be by system storage, peripherals will propose the data read requirement to south bridge circuit; And south bridge circuit will be coordinated north bridge circuit, by north bridge circuit with the data of these given addresses by reading in the system storage, give peripherals via south bridge circuit with these data transmission again, realize the requirement of peripherals.
In order to improve the service efficiency to peripherals, south bridge circuit can carry out a mechanism that reads in advance.When peripherals will read the data of some given address from system storage, south bridge circuit was read the data of these given addresses except requiring north bridge circuit, also can read the data of contiguous address as pre-reading data by the extra demand north bridge circuit.North bridge circuit is finished after the reading of data, south bridge circuit can with the data transmission of given address to peripherals to realize its requirement, pre-reading data then can be deposited in the south bridge circuit.By the time peripherals is when requirement is read the data of other addresses in will be by system storage again next time, and south bridge circuit will check whether the address of peripherals requirement data meets the address of pre-reading data.If peripherals requires the address of data to meet the address of pre-reading data just, south bridge circuit just can directly transfer to peripherals with pre-reading data, need not pass through north bridge circuit access system storer again.So, south bridge circuit just can be served the reading requirement of peripherals quickly.
For instance, when peripherals will read (burst read) continuously to system storage, peripherals can require to read the data of neighbor address, for example was four batch datas of address AD (n), AD (n+1), AD (n+2), AD (n+3).And when reading in advance, south bridge circuit can require north bridge circuit to read eight batch datas of address AD (n) to AD (n+7) continuously from system storage, wherein, address AD (n) is that peripherals requires to the data of AD (n+3), and south bridge circuit can be with these data transmission to peripherals.Address AD (n+4) then can be deposited at south bridge circuit to the data of AD (n+7), as pre-reading data.When peripherals requires to read once again next time by the time, if the data of its requirement are exactly the data of address AD (n+4) to AD (n+7), south bridge circuit just directly its pre-reading data of depositing transfer to peripherals.Because peripherals characteristic regular meeting requires the adjacent data in address in the reading system storer,, above-mentioned south bridge circuit can improve service efficiency to peripherals so reading mechanism in advance.
On the other hand, as is known to the person skilled in the art, the central processing unit in the computer system also can be provided with inner get soon (memory cache).Central processing unit can read in data, the data of some address in the system storage to its memory cache via north bridge circuit, during operation directly by these data of access in the memory cache.For instance, central processing unit is when certain program of execution, may need to utilize the data space of address AD in the system storage (m) to deposit a certain parameter in the program, this moment, central processing unit just can read in the data of address AD (m) to memory cache by system storage by north bridge circuit.Thereafter, according to the flow process that program is carried out, suppose that the data of address AD (m) should be updated, central processing unit just can directly upgrade the corresponding data content in the memory cache, and needn't the access system storer.Certainly, central processing unit when specific chance with the data write-back in the memory cache (write back) to system storage, but central processing unit can not carry out write-back continually, otherwise has just lost the meaning of memory cache utilization.
The mechanism that reads in advance of south bridge circuit all designs in order to improve computer working usefulness with the mechanism of getting soon of central processing unit, yet, when above-mentioned two kinds of mechanism were worked together, the situation of data inconsistent (incoherence) but may take place.For instance, if south bridge circuit deposited the data of a certain address AD (m) and be pre-reading data, and the data of same address AD (m) are read into the memory cache to central processing unit.At this moment, central processing unit is if upgrade the data content of address AD (m) in the memory cache, because south bridge circuit can't be learnt the central processing unit data of scheduler AD (m), the data of address AD in the south bridge circuit (m) will be data old, that renewal is preceding.Under this kind situation,, will cause data inconsistent, and make the computer working mistake if south bridge circuit offers peripherals with its address AD of depositing (m) data.Because, be the data of address AD (m) equally, central processing unit upgrades its data content, but the data content that peripherals is obtained by south bridge circuit is a data updated content not.
Inconsistent for fear of above-mentioned data, routine techniques can be provided with counter in south bridge circuit, calculate the lifetime of pre-reading data.Surpassed the default time (being the lifetime) if in the south bridge circuit certain data is saved as the time of pre-reading data, just forced south bridge circuit its removing (invalidate).The hypothesis of this routine techniques institute basis is that along with the computer working time increases, each batch data in system storage all more and more might be read into the memory cache to central processing unit; So if south bridge circuit continues to deposit the time of certain address data above a default lifetime, the data of this address have been read into to the probability of central processing unit should also surpass a certain threshold value, represents the data of this address very likely to be read into memory cache to central processing unit.Inconsistent for fear of data, south bridge circuit should not continue to deposit the original content of this address date, it should be removed.
In other words, in above-mentioned routine techniques, south bridge circuit only can guess in fact whether its pre-reading data of depositing is updated in the memory cache of central processing unit, and can't positively avoid the inconsistent of data.Especially aspect the setting of lifetime length, if the lifetime is too short, south bridge circuit certainly will will be removed the pre-reading data that it is deposited continually; In this case, perhaps the data of a certain address are not read into the memory cache to central processing unit at all in the pre-reading data, but south bridge circuit so just can't use these pre-reading datas effectively with its removing, and each removing all can influence the usefulness of north and south bridge circuit work.On the other hand, if the lifetime is long, then the inconsistent generation of data certainly will can't be avoided.
Summary of the invention
Therefore, fundamental purpose of the present invention promptly is to propose a kind of auxiliary device and correlation technique that makes south bridge circuit can more effective, more correctly use the mechanism of reading in advance with north bridge circuit, to overcome the shortcoming of routine techniques.
In computer system, because north bridge circuit has the ability of central processing unit being spied upon (snooping), also be in charge of the write-back of the memory cache of central processing unit, deposit the data of which address in the memory cache of central processing unit and whether be updated etc. so north bridge circuit can be learnt.One of purpose of the present invention will be utilized the ability of north bridge circuit exactly, assists south bridge circuit to safeguard pre-reading data.
In preferred embodiment of the present invention, can one address sequence module be set at north bridge circuit, when north bridge circuit the data in the memory cache of system storage or central processing unit are read and during as the pre-reading data of south bridge circuit, also these pre-reading data corresponding address can be deposited in the address sequence module.North bridge circuit can utilize one to spy upon and check module periodically central processing unit is spied upon, and according to the address of writing down in the block of address, whether whether the data of checking these addresses are read into the memory cache to central processing unit, be updated.If the data of some address are updated in central processing unit in the address sequence module, north bridge circuit can utilize dominant frequency signal (in-band) the notice south bridge circuit between the bridge circuit of north and south, make south bridge circuit remove the data of these addresses, again require the data after these addresses are upgraded, keep the consistance of data.If north bridge circuit is found the data in the address sequence module and is not updated that south bridge circuit just keeps original pre-reading data sustainably in the memory cache of central processing unit.
In addition, when central processing unit will be written back to system storage via north bridge circuit with the data in the memory cache, spying upon of north bridge circuit checks module can check also whether the data of each address in the address sequence module are upgraded by the memory cache of central processing unit, and then guarantees the consistance of the memory cache data of pre-reading data and central processing unit.
In other words, the present invention can utilize the spy upon ability of north bridge circuit to the central processing unit memory cache, guarantee data that south bridge circuit reads in advance can with the data consistent of central processing unit memory cache.Except keeping data consistency, the present invention also can promote the usefulness that south bridge circuit reads mechanism in advance, because south bridge circuit only is updated the content that Shi Caihui removes pre-reading data at pre-reading data in memory cache, can reduce the work of removing as far as possible, reduce the influence of removing work usefulness.
According to an aspect of the present invention, provide a kind of chipset, be connected between a central processing unit and the peripherals, described chipset includes: a south bridge circuit connects this peripherals, and has the module of depositing, store a plurality of pre-reading datas, in order to offer this peripherals in good time; And a north bridge circuit, connecting this central processing unit and this south bridge circuit, this north bridge circuit comprises: an address sequence module is used for storing the address of these a plurality of pre-reading datas; And one spy upon the inspection module, address according to these a plurality of pre-reading datas, whether the data content of checking this a plurality of addresses correspondence is upgraded by this central processing unit, wherein, if the described inspection module of spying upon finds that the data of the address correspondence of these a plurality of pre-reading datas are updated in this central processing unit, then remove the pre-reading data that this south bridge circuit is deposited, with the data content transmission that is updated of the address correspondence of these a plurality of pre-reading datas to this south bridge circuit.
According to a further aspect of the invention, providing a kind of assists south bridge circuit to safeguard the method for pre-reading data with north bridge circuit, it includes: when south bridge circuit will transfer to a peripherals with a collection of at least perimeter data, at least a collection of pre-reading data is deposited to this south bridge circuit, and made the address of these a plurality of pre-reading datas different with the address of these a plurality of perimeter data; The address of each batch pre-reading data is deposited at this north bridge circuit; And periodically carry out one and check step, check whether the data content of the address correspondence of these a plurality of pre-reading datas is upgraded by a central processing unit; If find that when carrying out this inspection step the data of the address correspondence of these a plurality of pre-reading datas are updated in this central processing unit, remove the pre-reading data that this south bridge circuit is deposited, with the data content transmission that is updated of the address correspondence of these a plurality of pre-reading datas to this south bridge circuit.
Description of drawings
Fig. 1 unifies the synoptic diagram of embodiment for department of computer science of the present invention.
Fig. 2 is the sequential synoptic diagram of each coherent signal during computer working among Fig. 1.
Fig. 3 is the schematic flow sheet of computer working among Fig. 1.
The reference numeral explanation
10 computer systems, 12 central processing units
14 north bridge circuits, 16 south bridge circuits
18 storeies, 20 peripherals
22 spy upon the inspection module
24 address sequence modules 26 are deposited module
30 memory caches
The 101-122 step
Ta0-ta5, tb0-tb2, tc1-tc4 time point
AD (P1), AD (P2), AD (Pm) address
CLK, FRAME, IRDY, TRDY, DEVSEL, UPCMD, DNCMD, TLRRDY, ADS, HA, FLUSH signal
Embodiment
Please refer to Fig. 1.Fig. 1 is the function block schematic diagram of computer system 10 1 embodiment of the present invention.Be provided with a central processing unit 12 in the computer system 10, the chipset that forms by north bridge circuit 14, south bridge South Road 16, be electrically connected to north bridge circuit with storer 18 (as dynamic RAM) as system storage, and the peripherals 20 that is connected in south bridge circuit by bus (as the PC1 bus, peripheral communications interface bus); In the computer system 10 one or more peripherals can be arranged, among Fig. 1 then be with peripherals 20 as representative, it can be hard disk unit, optical disc apparatus or various additional card, as sound card, network card etc.Central processing unit 12 is used for host computer system 10, with software program for execution, carries out the processing and the computing of data, wherein also is provided with a memory cache 30, is used for depositing data.Then be provided with one in the south bridge circuit 16 and deposit module 26, be used for depositing pre-reading data.In order to realize the present invention, north bridge circuit 14 is provided with one and spies upon an inspection module 22 and an address sequence module 24.
When peripherals 20 will be read address AD (n) to the data of AD (n+k) from storer 18, south bridge circuit 16 can send one to north bridge circuit 14 and upload requirement (upstream request), require north bridge circuit 14 by reading the data of address AD (n) in the storer 18, and additionally read the data to AD (Pm) such as address AD (P1), AD (P2) to AD (n+k).Address AD (n) is the data that peripherals 20 requires to the data of AD (n+k), can be described as perimeter data; Address AD (P1), AD (P2) to the data of AD (Pm) then are the data that south bridge circuit 16 reads in advance.Address AD (P1), AD (P2) can be the address of contiguous address AD (n) to AD (n+k) to AD addresses such as (Pm), and address AD (P1), AD (P2) to AD (Pm) also can be the address that is connected with each other.
After north bridge circuit 14 receives the requirement of south bridge circuit 16, require the address of data at south bridge circuit 16, spying upon in the north bridge circuit 14 checks that module 22 will spy upon memory cache 30, whether whether the data of checking these addresses are read into to memory cache 30, be changed in memory cache 30.If the data of these addresses are not updated in memory cache 30, north bridge circuit 14 will transfer to south bridge circuit 16 by in the storer 18 data of these addresses being read.If there is some data to be updated in memory cache 30 in the data of these addresses, north bridge circuit 14 just transmits it to south bridge circuit 16 after can obtaining data updated.In any case, when north bridge circuit 14 offers south bridge circuit 16 in the data that south bridge circuit 16 is required, can confirm south bridge circuit 16 resulting data contents be with memory cache 30 in consistent (if having the data of some address to be read into) to memory cache 30.
In the present invention, north bridge circuit 14 is except carrying out the affirmation of data consistency data transmission to south bridge circuit, simultaneously, north bridge circuit 14 also can be deposited at the address AD (P1) of pre-reading data, AD (P2) in the address sequence module 24 to AD (Pm).South bridge circuit 16 receives address AD (n) that north bridge circuit the transmits perimeter data to AD (n+k), will directly transfer to peripherals 20, allows peripherals 20 can obtain its desired data.Address AD (P1), AD (P2) then can be deposited in the south bridge circuit 16 to the pre-reading data of AD (Pm), and south bridge circuit 16 can continue to keep these data, because peripherals 20 may will continue to require these data after a while.
Certainly, as previously mentioned, south bridge circuit 16 address AD (P1), AD (P2) to the data of AD (Pm) are continued be left pre-reading data during, central processing unit 12 might read in the data of some address in these addresses to memory cache 30 by storer 18, and in memory cache 30, upgraded, and this will cause the data of pre-reading data and memory cache 30 inconsistent.Inconsistent in order to prevent this data effectively, south bridge circuit 16 address AD (P1), AD (P2) to the data of AD (Pm) are continued be left pre-reading data during, north bridge circuit 14 can be periodically checks that to spy upon module 22 spy upon memory cache 30.Because the address AD (P1), AD (P2) that have recorded pre-reading data in the address sequence module 24 are to AD (Pm), check that the result that module 22 is spied upon compares with spying upon again, just can check whether whether address AD (P1), AD (P2) to the data of AD (Pm) have been read into memory cache 30, be updated in memory cache 30.If address AD (P1), AD (P2) all are not updated in memory cache 30 to the data of AD (Pm), south bridge circuit 16 is with regard to the content of sustainable each pre-access data of reservation; When peripherals 20 requires the data of some address once again, if the address that peripherals 20 requires conforms to the address of pre-access data, south bridge circuit 16 just can be directly with the content delivery of pre-access data to peripherals 20, satisfy the requirement of peripherals 20 apace.
On the other hand, check that module 22 is when checking contrast if spy upon, find that address AD (P1), AD (P2) have the data of some address to be updated in memory cache 30 to AD (Pm), this pre-reading data of just representing south bridge circuit 16 to keep out-of-date (not upgrading the up-to-date content in back and do not have), this moment, north bridge circuit 14 just can utilize following biography (downstream) instruction of dominant frequency (in-band) to notify south bridge circuit 16.South bridge circuit 16 will be removed (invalidate) pre-reading data content that it kept automatically, and again northwards bridge circuit 14 send and upload requirement, require north bridge circuit 14 by the content delivery after in the memory cache 30 pre-reading data being upgraded to south bridge circuit 16.So, the pre-reading data in memory cache 30 and the south bridge circuit 16 will keep the consistance of data.
Except periodically spying upon the inspection, when central processing unit 12 will be written back to storer 18 with the data of memory cache 30, spying upon in the north bridge circuit 14 checks that module 22 also can compare automatically, look at whether to include in the address of write-back the address of pre-reading data, whether be updated.If not, south bridge circuit 16 still can keep original pre-reading data content; If, north bridge circuit 14 will be notified south bridge circuit 16, make south bridge circuit 16 can remove original pre-reading data content, and make content delivery after north bridge circuit 14 is updated pre-reading data to south bridge circuit 16, like this except keeping data consistency, also can promote south bridge circuit and read machine-processed usefulness in advance, because can reduce unnecessary removing work as far as possible.
For further specifying situation of the invention process, please refer to Fig. 2 (and in the lump with reference to figure 1); When the present invention assists south bridge circuit to obtain with the north bridge circuit in the computer system 10 and safeguards its pre-reading data, be that the waveform sequential of each signal among available Fig. 2 is illustrated with the situation of signal exchange co-ordination between its north and south bridge circuit; Transverse axis among Fig. 2 is the time.In each signal that Fig. 2 illustrated out, as is known to the person skilled in the art, signal CLK is the time clock of north and south bridge circuit co-ordination, and signal FRAME, IRDY, TRDY, DESVEL are south bridge circuit 16 and 20 basic bus signals of peripherals.
Suppose that peripherals 20 will read the data in the storer 18 when time point ta0, peripherals 20 will make signal FRAME become numeral 0 by numeral 1, requires data to south bridge circuit 16.Next, at time point ta1, south bridge circuit 16 will be in signal UPCMD sends to north bridge circuit 14 uploads requirement, requires north bridge circuit 14 to obtain its required data for south bridge circuit 16, comprises required perimeter data of peripherals and the data that read in advance.And when time point ta2, send digital 0 signal ADS, begin the memory cache 30 of central processing unit 12 is spied upon with regard to representative.Arrived time point ta3.On behalf of north bridge circuit 14, the signal TLRRDY of numeral 1 just obtained the response of central processing unit 12; Next, at time point ta4, north bridge circuit 14 will send the signal that passes down to south bridge circuit 16 in signal DNCMD, make south bridge circuit 16 obtain required data; North bridge circuit 14 also is deposited at the address of pre-access data in the address sequence module 24 itself.And south bridge circuit 16 also will be given peripherals 20 with peripherals 20 required data transmission between time point ta4 to ta5, and south bridge circuit 16 also begins to preserve pre-reading data.
Arrived time point tb1, the signal ADS that numeral 0 takes place central processing unit 12 comes access memory 18, to prepare to carry out the renewal of data, north bridge circuit 14 will begin to assist south bridge circuit 16 to confirm the consistance of the data of its pre-reading data and memory cache 30, so central processing unit 12 is spied upon, with each address, check whether the data of these addresses are updated in memory cache 30 according to record in the address block 24.Suppose north bridge circuit 14 after time point tb1 begins to spy upon, find that the data that truly have some address in the address sequence module 24 are updated in memory cache 30; In this case, north bridge circuit 14 will be as shown in Figure 2, when time point tb1, change signal FLUSH into numeral 1 to represent pre-reading data to be eliminated, and when time point tb2, in signal DNCMD, send specific instruction notification south bridge circuit 16, allow south bridge circuit 16 learn its data that read in advance with memory cache 30 in data inconsistent.Next, south bridge circuit 16 will carry out the removing of pre-reading data: south bridge circuit 16 can start among the signal UPCMD sending to north bridge circuit 14 at time point tc1 uploads requirement, require the content after north bridge circuit 14 provides the pre-reading data renewal, north bridge circuit 14 can require the data of its memory cache 30 at time point tc2 to central processing unit 12, tc3 obtains data in time point, and the content delivery after time point tc4 upgrades pre-reading data is to south bridge circuit 16.Like this, south bridge circuit 16 just can make pre-reading data keep consistent with the data in the memory cache 30.
Comprehensive the above, the flow process that the present invention carries out can be illustrated with Fig. 3; Please refer to Fig. 3 (and in the lump with reference to figure 1), the flow process among Fig. 3 includes the following step:
Step 102: peripherals 20 requirements will be read the data in the storer 18, so peripherals 20 proposes reading requirement to south bridge circuit 16.
Step 104: south bridge circuit 16 sends to north bridge circuit 14 and uploads requirement, requires north bridge circuit 14 that required perimeter data of peripherals 20 and extra pre-reading data are provided.
Step 106: except from storer 18 south bridge circuit 16 required data being read, north bridge circuit 14 can be spied upon central processing unit 12 earlier, offers south bridge circuit so that will have the data of what be new.
Step 110: south bridge circuit 16 offers peripherals 20 with peripherals 20 required perimeter data.Simultaneously, south bridge circuit 16 also begins to preserve pre-reading data.
Step 112: in order to assist south bridge circuit 16 to keep its pre-reading data is latest data, north bridge circuit 14 can be spied upon the memory cache 30 of central processing unit 12 or at central processing unit 12 memory cache 30 contents is written back to storer 18 when carrying out access address and Data Update, with according to the address of depositing in the block of address, check whether the data of these addresses are updated in memory cache 30.
Step 114: if in the address sequence module, have the data of some address in memory cache 30, to be updated, will proceed to step 116; If not, then proceed to step 112.
Step 116: north bridge circuit 14 sends down the instruction that passes to south bridge circuit 16, and notice south bridge circuit 16 will be removed its pre-reading data.
Step 118: south bridge circuit 16 can be when removing pre-reading data sends to north bridge circuit 14 uploads requirement, requires north bridge circuit 14 to obtain content after pre-reading data upgrades.
Step 120: north bridge circuit 14 can be spied upon central processing unit 12, by the content that obtains in the memory cache 30 after pre-reading data upgrades.
Step 122: via north bridge circuit 14, south bridge circuit 16 just can be obtained the what be new of pre-reading data, keeps the consistance of pre-reading data and memory cache 30 data.
Compare with routine techniques, the present invention can be recorded in north bridge circuit with the address of south bridge circuit pre-reading data, and utilize north bridge circuit can spy upon the ability of central processing unit, whether the content of checking pre-reading data is updated in the memory cache of central processing unit, assists south bridge circuit to safeguard its pre-reading data.So the present invention can not only keep the consistance of pre-reading data and memory cache data, can also improve the utilization usefulness of pre-reading data.In the present invention in the embodiment of Fig. 1, each module of north bridge circuit 14, south bridge circuit 16 can realize in modes such as hardware or firmwares widely, for instance, deposit module 26 and can utilize the register of a first in first out (FIFO) to realize, spy upon the controller of the then available sequencing of function of checking module 22 and realized.
The above only is preferred embodiment of the present invention, allly makes equivalence according to claim of the present invention and changes and revise, and all should belong to covering scope of the present invention.
Claims (10)
1. a chipset is connected between a central processing unit and the peripherals, and described chipset includes:
One south bridge circuit connects this peripherals, and has the module of depositing, and stores a plurality of pre-reading datas, in order to offer this peripherals in good time; And
One north bridge circuit connects this central processing unit and this south bridge circuit, and this north bridge circuit comprises:
One address sequence module is used for storing the address of these a plurality of pre-reading datas; And
One spies upon the inspection module, address according to these a plurality of pre-reading datas, whether the data content of checking this a plurality of addresses correspondence is upgraded by this central processing unit, wherein, if the described inspection module of spying upon finds that the data of the address correspondence of these a plurality of pre-reading datas are updated in this central processing unit, then remove the pre-reading data that this south bridge circuit is deposited, with the data content transmission that is updated of the address correspondence of these a plurality of pre-reading datas to this south bridge circuit.
2. chipset as claimed in claim 1, wherein, module finds that the data content of this a plurality of addresses correspondence is updated in this central processing unit if this spies upon inspection, then this south bridge circuit is removed and is deposited this stored pre-reading data of module.
3. chipset as claimed in claim 2, wherein, check that module finds that the data content of this a plurality of addresses correspondence is updated in this central processing unit if this is spied upon, then this south bridge circuit requires the data content transmission that is updated that this north bridge circuit will this a plurality of addresses correspondence to deposit module to this.
4. chipset as claimed in claim 1 checks wherein whether the data content of this a plurality of addresses correspondence is upgraded by this central processing unit, is to spy upon the inspection module by this periodically to check this central processing unit.
5. chipset as claimed in claim 1, wherein whether the data content of this a plurality of addresses correspondence of this inspection is upgraded by this central processing unit, be after the data content that this central processing unit will this a plurality of addresses correspondence upgrades, be written back to one when being electrically connected on the storer of this north bridge circuit through this north bridge circuit, spy upon by this and check that module is checked and obtain.
6. chipset as claimed in claim 1, wherein those pre-reading datas are according to the desired a collection of perimeter data of this peripherals, extract the adjacent data in this batch perimeter data address.
7. chipset as claimed in claim 6, wherein those pre-reading datas are positioned at continuous address.
8. assist south bridge circuit to safeguard the method for pre-reading data with north bridge circuit for one kind, it includes:
When south bridge circuit will transfer to a peripherals with a collection of at least perimeter data, a collection of at least pre-reading data is deposited to this south bridge circuit, and made the address of these a plurality of pre-reading datas different with the address of these a plurality of perimeter data;
The address of each batch pre-reading data is deposited at this north bridge circuit; And
Periodically carry out one and check step, check whether the data content of the address correspondence of these a plurality of pre-reading datas is upgraded by a central processing unit;
If find that when carrying out this inspection step the data of the address correspondence of these a plurality of pre-reading datas are updated in this central processing unit, remove the pre-reading data that this south bridge circuit is deposited, with the data content transmission that is updated of the address correspondence of these a plurality of pre-reading datas to this south bridge circuit.
9. method as claimed in claim 8, wherein the address of these a plurality of pre-reading datas is adjacent with the address of these a plurality of perimeter data.
10. method as claimed in claim 9, wherein these a plurality of pre-reading datas are positioned at continuous address.
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| CNB2004100785465A CN100336042C (en) | 2004-09-09 | 2004-09-09 | Device and relative method for pre-reading data using north bridge circuit to maintain south bridge circuit |
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| US5991833A (en) * | 1998-03-13 | 1999-11-23 | Compaq Computer Corporation | Computer system with bridge logic that reduces interference to CPU cycles during secondary bus transactions |
| CN1405686A (en) * | 2001-09-14 | 2003-03-26 | 东维成科技股份有限公司 | System and method for ensuring computer host safety |
| CN2606396Y (en) * | 2002-11-18 | 2004-03-10 | 威盛电子股份有限公司 | Computer system with error eliminating turn-on system |
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| CN1588334A (en) | 2005-03-02 |
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