CH690157GA3 - Device multitasking processing instruction sequences. - Google Patents

Description

The present invention relates to a multi-task device for processing instruction sequences, and more particularly, to a device of the type which comprises means for storing N instruction sequences corresponding to N different tasks, means for activating any plurality of said tasks, means for successively executing an instruction from each active task and means for interleaving the execution of instructions from the active tasks.

Such multitask devices are known, in particular from the international patent application WO-A9 415 287 filed on December 10, 1993 in the name of Center Electronique Horloger SA. The device described in this patent application comprises a microprocessor for processing simultaneous and in time sharing any plurality of N tasks, a multitask sequencer to control the execution of said tasks by the microprocessor, means for storing N instruction counters used by the sequencer to control the sequencing of a particular of said tasks. Thus the sequencer selects the instruction of the next task by another counter when the instruction of the previous task is finished, which quickly transfers data from storage means of this data. Advantageously, the microprocessor of the device also includes as many accumulators and index registers as there are instruction counters, always to avoid data transfers. The energy consumption of the device is thus reduced and the execution of the tasks is interleaved, which improves the response time of the device. This is particularly interesting in the horological field where the microprocessors are supplied with low voltage, this low voltage favorably affecting the speed of execution of instructions by the microprocessor.

In a multitsche device as described in the aforementioned patent application, the execution of an instruction requires several clock phases, for example 4. Taking into account the constraint of low consumption at low voltage posed in micro clock electronics, we understand that there is a need for a device capable of executing, for example, an instruction per phase, which would quadruple the speed with the same clock frequency and the same supply voltage , or would execute the same number of instructions at a frequency 4 times lower allowing a reduced supply voltage.

We also know the technique of processing instructions of compounds in several successive phases, called "overlapping" or "pipeline" according to the English expression. At each instant, different phases of several successive instructions are treated which makes it possible to reduce the apparent duration of execution of a complete instruction and therefore to reduce the duration of execution of a sequence of instructions. However, pipeline processing has two serious drawbacks that reduce the gain in duration that can be expected. On the one hand, when the sequence includes a connection, it is most often necessary to "empty" the pipeline before filling it with a new sequence of instructions, which leads to empty phases slowing down the execution of the s quence. We observe the same drawback when the execution of an instruction calls for a result which is not yet available because it is produced by a previous instruction which has not yet left the pipeline.

The object of the present invention is to provide a device for processing instruction sequences which does not suffer from the constraints which reduce the speed of execution of "multitask" or "pipeline" processing devices and which allows , in particular, to reduce to a minimum the number of empty phases.

These objects of the invention are achieved, as well as others which will appear on reading the description which follows, with a multitask device for processing sequences of instructions, of the type which includes means for storing N s instruction sequences corresponding to N different tasks, means for activating any plurality of said tasks, and means for interleaving the execution of the instructions of X active tasks (X </ = N) so that the execution of an instruction of an active task following the execution of an instruction of the preceding active task, this device being so remarkable in that it comprises means for processing in pipeline of M successive phases of each of several interleaved instructions, and a task manager sensitive to events involving the activation of said tasks to control the processing means so as to ensure the execution in pipeline of the successive phases of the interleaved instructions ac es active tasks.

As will be seen below, it follows from the multitsche structure of the device according to the invention that the successive instructions which are treated in overlap or in "pipeline" do not belong to the same sequences of instructions. Thus, the speed of execution of the device is not reduced either by waiting for the result of an instruction that is not completely executed or by an "emptying" of the pipeline required by the execution of a connection instruction.

According to an embodiment of the device according to the invention, designed for the execution of a maximum of four active tasks, the pipeline processing means process instructions of compounds in three phases, of reading in memory of storage of instructions, performing an operation in an arithmetic and logical unit, and storing the result in memory simultaneously with an incrementation of a program counter or with a loading of connection address, respectively.

According to a first variant of the device according to the invention, designed for the execution of four active tasks, the processing means and the task manager control the execution of instructions of compounds in two phases, of extraction and execution respectively.

According to a second variant of the device according to the invention, designed for the execution of a maximum of four active tasks by instructions d composed in four phases, the processing means and the task manager control the addressing of accumulators , program counters, random access memory associated with the microprocessor and means for storing the four sequences of instructions, so as to ensure the execution of an active task in a constant time, whatever the number of active tasks.

According to a third variant of the device according to the invention, the sequence of M phases of an instruction is chosen so as to avoid any blocking of the processing in pipeline when the number of active tasks is greater than or equal to a number pr d termin lower than the number N of instruction sequences stored in memory in the storage means.

Other characteristics and advantages of the present invention will become apparent on reading the description which follows and on examining the appended drawing, in which:

 fig. 1 schematically represents the architecture of an embodiment of the device according to the invention and,  fig. 3, 5 and 6 schematically represent the architecture of three variants of this device, and  fig. 2, 4 and 7 are timing diagrams of the instructions executed by the devices of FIGS. 1, 3 and 6, respectively.

We refer to fig. 1 of the accompanying drawing where the architecture of an embodiment of the device according to the invention has been represented, adapted to the execution of a maximum of four tasks, with processing of instructions in "pipeline" Ù three floors. The four instruction sequences corresponding to the four tasks are stored in different sections of a permanent ROM memory forming part of the first stage of the device's "pipeline" architecture. This includes a microprocessor formed by an arithmetic and logic unit ALU, a RAM memory mounted between a bus 1 and a bus 2 and, like the multitssche device described in the aforementioned patent application , a plurality of program counters PC0 Ù PC3 to address the ROM memory and a corresponding plurality of accumulators AC0 Ù AC3 associated with the arithmetic and logic unit ALU. These counters and accumulators are selectively addressed, in reading, as in writing, by a task manager G controlled by a token loop, which selects the tasks activated by events. In this embodiment, the manager selects either three tasks or four tasks. In the hypothesis that only one or two tasks should be activated, the manager could insert empty phases, at the expense of the speed of execution of the device.

The events triggering the selection of a task can be of internal origin (control of a stepping motor in a watch, for example) or external (selection of the stopwatch function, for example). The selection is made in the following manner. If the token J, for example, is in a CO cell of the loop which corresponds to task O, the task manager points at output task s = 0 to command the activation of the program counter PC0, of the accumulator AC0, etc ... When the token goes to task 1, = 1, which is selected AC1, PC1, etc ... As the multitssche device according to the invention also ensures pipeline processing of the various phases of the instructions, the different stages of the pipeline deal with different tasks.

In fig. 1, it appears that the task manager selects in reading (L) the counter PCi (i = 0, 1, 2, 3) corresponding to the task s, selects in write mode (E) the accumulator ACi corresponding to the task (s-1), selects the accumulator by reading and writes the counter which corresponds to task s-2.

The RAM memory used in the device according to the invention must be able to be read and written at each phase of the instructions. We therefore choose a fast memory with double access via bus 1 and bus 2.

It will also be noted, in the device of FIG. 1, the presence of two instruction registers RI 1 and RI 2 placed in series in this order between the ROM memory and the input of the program counters PC0 Ù PC3. The presence of these two registers results from the phasing chosen for the instructions, which is established as follows: <tb> <TABLE> Columns = 2 <tb> <SEP> phase 1 <SEP> RI 1 <- ROM (PCi) <tb> <SEP> phase 2 <SEP> ACi <- ALU (ACi, RAM), RI 2 <- RI 1 <tb> <CEL AL = L> phase 3 <SEP> RAM <- ACi, PCi <- PCi + 1 or PCi <- ad <tb> </TABLE>

Thus an instruction is executed in three phases, the first to read the memory at the address indicated by the program counter PCi (i = 0, 1, 2, 3), the second me to carry out an operation in the ALU unit and charge the ACi accumulator and the third to store the result in memory and increment the PCi program counter or load it with a jump address, in case of connection. The instruction read in the memory is entered in the register RI 1 during the first phase and the content of RI 1 transferred to RI 2 during the second phase.

For four active tasks 1, 2, 3 and 4 and the accumulators and program counters with the same indices assigned to them, the multitasking three-stage pipeline processing of the four corresponding instruction sequences develops over time according to the timing diagram shown in fig. 2. In this fig., It appears that the three phases of the same instruction are tagged in staircase steps, the successive instructions overlapping one another. This is how, for example, during the third phase of the first instruction of task 0: - stage 3 of the pipeline is occupied by an instruction from task 0. The accumulator AC0 is read in order to load it into the RAM addressed in writing and the counter PC0 is addressed either to increment it, or to load it with a connection address ad, - stage 2 of the pipeline is occupied by an instruction from task 1. The accumulator AC1 is addressed to charge it with the result of a f ex cut operation in the ALU unit, operation whose operations routes are the contents of AC1 and RAM, read address, - stage 1 of the pipeline reads an instruction from task 2 in ROM memory by sending the program counter PC2 for reading.

Otherwise, task 2 being treated in stage 1, we have s = 2 (see fig. 1). The previous task s-1 = 1 is in stage 2 and the task s-2 = 0 is in stage 3.

If task 3 was in stage 1 (s = 3), we would have task 2 in stage 2 (s-1 = 2) and task 1 in stage 3 (s-2 = 1).

It appears that the management of the tasks and of the pipeline in the device according to the invention makes it possible to ensure that each instruction of each task is executed in turn, each having no relation to the other instructions dealt with in the pipeline.

Thus, more generally, during the execution of N different tasks in multiprogramming, with a pipeline Ù M stages (with M </ = N), the M instructions contained in the pipeline are independent. The pipeline is never blocked by the intervention of a connection or by the fact that an instruction must wait for the result of a previous instruction that was not fully executed. The delays thus eliminated, in particular during the connections (which commonly represent around 25% of the instructions), make it possible to appreciably increase the speed of execution of the tasks or to maintain a given speed of execution with a device Ù lower consumption, in accordance with the objectives we set for ourselves.

We refer to fig. 3 of the accompanying drawing where we have schematically represented the architecture of a variant of the device according to the invention, designed to execute a maximum of four tasks with a two-stage pipeline. In this figure as in the following, identical references to references already used denote identical or similar elements or organs. Thus, like the embodiment of FIG. 1, that of FIG. 3 includes four program counters PC0 Ù PC3 and four accumulators AC0 Ù AC3, each pair of counter and accumulator of the same digital index as evolved in the execution of one of the four possible tasks. The device also includes a manager G of tasks s and (s-1) for respectively controlling the selection in reading of any one of the counters, the selection in writing of these counters and the selection in writing or reading of accumulators. . The device comprises a single instruction register and a central processing unit CPU such as a microprocessor conventionally comprising an ALU processing unit and a RAM memory, not shown, like the device in FIG. 1.

The two stages of the pipeline, extraction F and execution E, execute the following operations: <tb> <TABLE> Columns = 3 <tb> <SEP> Phase 1A Phase 1B <SEP> Extraction <SEP> RI <- ROM (PC) PchRom <tb> <SEP> Phase 2A Phase 2B <SEP> Execution <SEP> ACi <- ALU (ACi, RAM) RAM <- ACi; PCi <- PCi + 1 or ad <tb> </TABLE>

The first stage ensures the extraction of the instruction, ie the reading of the ROM memory and the loading of the instruction register RI with the instruction read, then a preload Pch of the memory ROM (sub-phases 1A and 1B). The second stage realizes "the execution", that is to say the loading of the accumulator ACi associated with a task active i particular, by an operation carried out in the unit ALU, the loading of the RAM by l ACi accumulator and incrementation of the program counter PCi or its loading with a connection address ad (sub-phases 2A and 2B). The ROM memory contains the four tasks and is read at each phase.

We have shown in fig. 4 the chronogram of the ex cut operations in the case where there are four active tasks. In this timing diagram I0.1, for example, reads "instruction 0 of task 1". It is clear that the pipeline processing is never blocked (that is to say, empty phase congestion) as soon as at least two tasks are activated. On this condition, the speed of execution of these tasks is optimal. If there is only one active task, the manager can insert an empty task (that is to say without "extraction" or "execution"). It is also possible to choose to operate the device according to the sole processing of instructions by pipeline. It is then necessary to insert a "delay" (ie for example the inoperative instruction "NOP" in the mnemonic language of microprocessors of the MC 6800 type) after a connection instruction or ignore the instruction that follows an effective connection .

We now refer to fig. 5 of the accompanying drawing where a second variant of the device according to the invention has been represented. In this variant, the means for storing the instructions of the N tasks (N = 4) are constituted by N memories ROM 0 Ù ROM 3 in parallel, each assigned to the instructions of one of the tasks. Each memory is read only once every N clock phases which makes it possible to use slower memories than if a single memory was used to store the N sequences of instructions. As a variant, it is also possible to install quick cache memories between the ROM memory (fig. 1 and 3) or the ROM memories (fig. 5) and the microprocessor.

The device of fig. 5 comprises means for preloading ROMi controlled by preload signals PRi (i = 0, 1, 2, 3). It is further distinguished from the device of FIG. 1 in that it comprises four master registers Mi each associated with one of the program counters PCi. The task manager G controls access to read or write these registers. The incrementation, or the jump to a branch address, of the program counters is determined by a multiplexer Mux controlling the registers Mi. For the rest, the device of fig. 5 comprises two instruction registers RI 1 and RI 2 and a microprocessor conforming to that of the device of FIG. 1. Note that the RAM associated with the ALU unit to be addressed to each phase with double access (write and read) must be fast. We could also use smaller RAMs, specific to each task and addressed more slowly.

The device of fig. 5 is designed to execute up to four tasks, each instruction consisting of four phases 1 to 4, to be executed as follows in a four-stage pipeline: <tb> <TABLE> Columns = 2 <tb> <SEP> phase 0 <SEP> Pr charge ROMi (PRi active) <tb> <SEP> phase 1 <SEP> RI 1 <- ROMi (PCi) <tb> <SEP> phase 2 <SEP> ACi <- ALU (ACi, RAM, Mi <- (PCi + 1 or ad, RI 2 <- RI 1 <tb> <SEP> phase 3 <SEP> RAM <- ACi, PCi <- Mi, pr ROMi charge <tb> </TABLE>

For the execution of the instructions, the task manager G always gives the hand cyclically to the four tasks, even if one or more of them are inactive, in which case, there will be interposition of empty phases. With four active tasks, during the duration of a phase of the various instructions processed in the pipeline, the following operations are carried out by the device according to the invention, taking the example of the execution of an instruction from task 0 in stage 3: <tb> <TABLE> Columns = 3 <tb> <SEP> Stage 0 <SEP> Preload ROM 3 <SEP> tssche 3 <tb> <SEP> Stage 1 <SEP> RI 1 <- ROM 2 (PC2) <SEP> tssche 2 <tb> <SEP> Stage 2 <SEP> AC1 <- ALU (AC1, RAM) M1 <- (PC1 + 1) or ad RI 2 <- RT 1 <SEP> task 1 <tb> <SEP> Stage 3 <SEP> RAM <- AC0 PC0 <- M0 Preload ROM 0 <SEP> tssche 0 <tb> </TABLE>

Thus in this stage there is read selection of AC0 for the loading of the RAM, itself obviously addressed in writing, selection of reading of the register M0 master of PC0 for the loading of the latter and preloaded with ROM 0 (signal PR0 is activated).

Stage 2 is then occupied by an instruction from task 1. There is selection in writing of AC1 to load there the result of an operation executed in the ALU of which an operand comes from RAM, selection of PC1 in read mode to load the new address PC1 + 1 or the ad connection address stored in the register RI 1 and selection of MI, master register of PC1, in writing for loading the new address.

Stage 1 is occupied by an instruction from task 2. There is then a reading of the memory ROM 2 addressed by the counter PC2 and a loading of the instruction read in the register RI 1.

Stage 0 is occupied by an instruction of task 3, that is to say a preload of the memory ROM 3, prudant to the reading of an instruction in this memory during the next phase of the processing multitssches and pipeline ex cut by the device according to the invention.

We find the set of operations described above in the processing phases which follow that described, with a circular permutation (0, 1, 2, 3, 0, 1 ...) of the digital indices of the accumulators ACi, ROMi memories, PCi counters, Mi registers.

It then appears that the duration of execution of a task in the device of FIG. 5 is constant, regardless of the number of active tasks. It follows that if only one task is activated, the processing of instructions by pipeline does not reduce the execution time of this task. On the other hand, the sudden activation of other tasks does not slow down the execution of the current task. The designer will obviously optimize the performance of the device by programming the maximum number of active tasks at all times.

We now refer to fig. 6 which represents a third variant of the device according to the invention, designed to ensure that the pipeline treatment is never blocked by empty phases, even when the number of active tasks is less than the number M of pipeline stages. Found in the device of FIG. 6 the different organs of that of FIG. 5, with the exception of the master registers Mi of the counters PCi. On the material level, the device of FIG. 6 is further distinguished from that of FIG. 5 by the presence of a third register of instructions RI 3 downstream of the second, and upstream of the write entry of the RAM memory associated with the processing unit ALU, and by the presence of a second MUX 2 multiplexer controlled by the task manager (same as the MUX multiplexer). The multiplexer MUX 2 determines the supply to the arithmetic and logic unit ALU of a connection condition Fi, for a purpose which will be seen later.

We can obtain the result stated above (the absence of pipeline blocking), by a four-stage pipeline processing, with only two active tasks. In this case, and with four memories ROM 0 to ROM 3, the pipeline contains at any time, in two of its four stages, two instructions belonging to the same task. It is therefore necessary to manage the operation of the pipeline accordingly.

To this end, the sequence of instructions is modified as follows, relative to that described in connection with the description of the device in FIG. 5: <tb> <TABLE> Columns = 2 <tb> <SEP> extraction <SEP> RI 1 <- ROMi (PCi) <tb> <SEP> d coding <SEP> RI 2 <- RI 1; PCi <- Fi * (PCi + 1) or Fi ad, Prech ROMi <tb> <SEP> execution 1 <SEP> RI 3 <- RI 2; Fi, ACi <- ALU (ACi, RAM) <tb> <SEP> execution 2 <SEP> RAM <- ACi <tb> </TABLE>

This sequence is then composed as follows - an extraction phase to read an instruction and load it into RI 1, - a phase of "coding" during which the instruction slides into the register RI 2, while the program counter PCi attached to the active task i is updated and the memory ROMi is preloaded. The program counter is updated by calculating the condition Fi which can take the value 1 or 0. If Fi = 0, the counter is incremented. If Fi = 1 it is an ad branch address which is loaded into the program counter, - a first execution phase ("execution 1") during which the ALU unit calculates a result from the contents of the ACi accumulator and RAM memory. The unit also calculates the connection condition Fi which must be available at the next phase for the next instruction of the task, which is in the pipeline, without it being necessary to wait for the end of the ex cution of the instruction. During this first execution phase, the content of the RI 2 register slides into the RI 3 register, - a second execution phase ("execution 2") during which the contents of the ACi accumulator pass into RAM memory.

With such a sequencing, the reading of an instruction and the updating of the program counter are carried out in only two phases (extraction and coding). The execution of the instructions of the sequence then takes place according to the time diagram represented in fig. 7.

According to this diagram, the execution of task 0 or task 1 in the four-stage pipeline takes place in two successive phases: - a first phase during which an instruction from task 1 (for example) is executed in stage 2 of the pipeline (AC1 <- ALU (AC1, RAM)), the ALU also calculating the connection condition F1 , while the following instruction 3 of task 1 (a connection for example) is read in stage 1 of the pipeline, - a second phase in which this instruction decides whether to connect from condition F1 calculated during the first phase

PC1 <- F1 * (PC1 + 1 or F1 * ad

The two phases of the above diagram repeat themselves cyclically throughout the duration of the processing of the two active tasks 0 and 1. It can be seen that the sequence chosen and the sequential sliding of the interleaved instructions of the two tasks in the three registers RI 1, RI 2, RI 3 makes it possible to avoid any empty phase and therefore any blockage of the pipeline.

Of course the device of FIG. 6 also makes it possible to execute four active tasks without empty phases, like that of FIG. 5. On the other hand, in the presence of only one active task (task 1 for example, the task manager G must insert empty phases (by the instruction code "NOP" for example), in all the boxes of the diagram in Fig. 7 assigned to task 0.

Note that, in the presence of two active tasks, the instruction before a connection must provide the boolean variable F1 or F0, resulting from the calculation of a condition coming, for example, from a comparison, without waiting the end of its execution. In fig. 7, the variable bool enne F1 is calculated by an instruction from task 1 in stage 2 during the first phase and the arrow indicates that it is directly used by the following instruction from task 1, which is a branch instruction, during the second phase in stage 1. It is the task manager which, if there are only two active tasks, directs the value of this variable bool enne F1, by the MUX 2 multiplexer, to all the program counters.

It now appears that the invention does indeed achieve the set goals, namely providing a device for processing instruction sequences combining the advantages of "multitask" and pipeline processing, without presenting the drawbacks. This increases the speed of execution of the various tasks entrusted to the device relative to the speed observed in known comparable devices with low energy consumption, such as that described in the international patent application cited above. The invention provides in particular the architecture of a device which makes it possible never to block a pipeline with four stages processing at least two active tasks, by means of an appropriate phasing of the instructions.

Of course, the invention is not limited to the embodiments described and shown, which have been given only by way of example. Thus, the invention could also find application in multitssche devices not subjected to a constraint of low energy consumption.

Claims (13)

1. Multi-step device for processing instruction sequences, of the type which comprises: means for storing N sequences of instructions corresponding to N different tasks, means for activating any plurality of said tasks, and means for interleaving the executions of the instructions of X active tasks (X </ = N) so that the execution of an instruction of an active task follows the execution of an instruction of the task active previous, characterized in that it includes: means for processing in pipeline M successive phases of each of several interleaved instructions, and - A task manager (G) sensitive to events involving the activation of said tasks to control the processing means so as to ensure the execution in pipeline of the successive phases of the interleaved instructions of the active tasks. 2. Device according to claim 1, characterized in that the processing means comprise a microprocessor equipped with a set of accumulators (ACi) and a set of program counters (PCi) associated in pairs (ACi, PCi ) each of which is involved in the execution of one of the tasks, the task manager (G) selectively controlling the reading and writing of these accumulators and counters. 3. Device according to claim 1 or 2, characterized in that it comprises means for inserting inoperative instructions (NOP), when the number of active tasks is less than the number M of phases. 4. Device according to any one of claims 1 and 2, designed for the execution of a maximum of four active tasks, characterized in that the pipeline processing means process instructions in three phases, reading in memory (ROM) for storing instructions, performing an operation in an arithmetic and logical unit (ALU), and storing the result in memory simultaneously at an increment of counter of program or Ù loading a branch address (ad), respectively. 5. Device according to claim 4, characterized in that the processing means comprise two instruction registers (RI 1, RI 2), the content of a register (RI 1) being loaded in the other register ( RI 2) during the execution of the second phase of an instruction. 6. Device according to any one of claims 1 and 2, designed for the execution of four active tasks, characterized in that the processing means and the task manager (G) control the execution of instructions in two phases of extraction (F) and execution (E), respectively. 7. Device according to claim 2, designed for the execution of a maximum of four active tasks by instructions composed in four phases, characterized in that the processing means and the task manager (G) control the addressing of accumulators (ACi), program counters (PCi), random access memory (RAM) associated with the microprocessor and storage means (ROMi) of the four instruction sequences, so as to ensure the execution of an active task in a constant time, regardless of the number of active tasks. 8. Device according to claim 7, characterized in that each program counter (PCi) is controlled by a master register (Mi) itself controlled by the task manager (G). 9. Device according to any one of claims 1 and 2, characterized in that the sequence of M phases of an instruction is chosen so as to avoid any blocking of the processing in pipeline when the number of active tasks is greater greater than or equal to a predetermined number less than the number (N) of instruction sequences stored in memory in the storage means. 10. Device according to claim 8, characterized in that N = 4, M = 4 and the predetermined number is 2. 11. Device according to any one of claims 1 to 10, characterized in that the storage means comprise a single dead memory (ROM) divided into N sections containing as many sequences of instructions. 12. Device according to any one of claims 1 to 10, characterized in that the storage means comprise N dead memories (ROMi) each containing one of the N sequences of instructions. 13. Device according to any one of claims 1 to 12, characterized in that the means for activating any plurality of tasks include a token loop (B) controlled by events.