CH632615A5 - Method and device for controlling a DC motor - Google Patents

Description

The object of the invention is therefore to provide an improved method for digitally controlling the ignition of controllable rectifiers in the power supply line for a DC motor, and one for carrying out this method

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Suitable device with a programmed data processor, which device contains interface devices which can read the system input parameters and calculate the required motor voltage and use a value proportional to such a calculated voltage to select the ignition angle for an ignition pulse.

The above object is achieved according to the invention by a method which is characterized in that parameters are stored in the processor which are proportional to the desired engine speed and the desired ignition angles, and that a program request signal is sent to the processor that the processor responds to this signal reads an actual motor speed and a value proportional to the motor current and calculates a value determining the ignition angle, which is based on the differences between the nominal motor speed and the actual motor speed, as well as between the values last read and the previous one, proportional to the motor current, and the previously calculated value determining the ignition angle is dependent on the processor also selecting one of the stored ignition angles as a function of the program request signal on the basis of the calculated value, and an ignition pulse for a at the point in time corresponding to the selected ignition angle Rectifier generated, and for the repeated calculations of the value determining the ignition angle and the generation of the ignition pulse, the ignition pulse is used as a program request signal.

The new method allows the ignition angle to be fully calculated, the rectifier to be fired selected, and the mode of operation of the device and the direction of rotation of the motor to be determined and selected in a time period that is short enough for the processor to provide an ignition angle that indicates maximum power output enables the DC motor, can calculate.

The device used to carry out the new method contains a data processor which enables digital regulation of the rate of change of the motor current, the motor voltage and the motor speed.

The use of the ignition pulse as a program request signal for the processor enables, in particular, the calculations to be carried out in such a short time that a rectifier can be fired at the earliest possible point in time within a phase interval of the AC power source and a maximum power transfer to the DC motor can thereby be achieved.

Exemplary embodiments of the invention are explained in more detail below with reference to the drawings. Show it:

1 is a block diagram of a regulating and control device according to the present invention,

2 is a simplified block diagram of a representative data processor for use in the invention.

3 is a block diagram showing the regulator and the rectifier controller and the rectifier of the device according to FIG. 1, which are connected to the data processor and the load or DC motor,

4 shows a detailed logic circuit of the processor / system interface in the block diagram according to FIG. 3, which shows the connection between the data processor and the other logic blocks of the controller and the rectifier control,

5 is a detailed logic diagram of the block diagram of FIG. 3;

6 is a timing diagram useful for understanding the operation of the system clock and the regulation and control device according to the invention;

7 is a detailed logic diagram of the tachometer pulse counter and logic unit of FIG. 3;

Fig. 8 is a timing diagram for understanding the

7 is useful in operating the tachometer pulse counter and logic unit of FIG.

9 is a detailed logic diagram of the ignition logic of FIG. 3;

10 is a timing diagram showing the timing of the firing logic of FIG. 9 and helpful in understanding the operation of the present invention.

11A and IIB taken together, with FIG. 11A coming to rest on the upper edge of FIG. 11B, show a detailed logic circuit diagram and a schematic structure of the thyristor selection and drive direction logic, the rectifiers and the analog / digital converter of FIG. 3 and the interconnections,

12 curves useful for understanding the operation of the present invention;

Fig. 13 is a dashed bar flow diagram useful for understanding the sequence of operation of the invention; and

14 to 24 a flowchart for understanding the implementation of the regulating and control method according to the invention.

To describe the overall operation of the invention, reference is now made to FIG. 1 of the regulating and control system, which shows in the form of a block diagram the essential functional blocks of which the present system consists. 1, a data processor, generally represented as a microprocessor 10, contains a program for controlling the overall operation of the system, with parameter input signals from a conventional DC motor 12 being read into the microprocessor via a regulator and rectifier control unit 14. The program in processor 10 controls the reading of these various input signals and includes a program to calculate the firing angle for properly firing the rectifiers or thyristors, commonly referred to as SCRs, in a conventional three-phase bridge rectifier 16. The regulator and rectifier control unit 14 provides a common interface between the processor 10 and the rest of the control system. Under the control of the processor 10, the rectifier control unit 14 reads input signals from a speed reference unit 18 via a multiplicity of input lines, such signals being a digital reference signal according to which the motor is to run in revolutions per minute and an on / off power state of the motor , and identify user signals that are set and indicate the direction in which the motor 12 is to run. The latter signals are supplied via a plurality of lines 20, which are referred to as “speed reference”. Via the controller control unit 14, additional input signals go to the processor 10 via a plurality of lines 22 and represent speed signals from the DC motor 12, which come from a sensor on the motor 12 and identify the speed in revolutions per minute at which the motor is running. The motor current is also measured by the microprocessor via the regulating and control unit 14, for which purpose a current is supplied from the motor to the processor via a plurality of lines 24. The control unit 14, under the control of signals provided by the processor 10, provides control signals to the rectifier 16 and receives data from the processor to control the firing of the thyristors (SCR) in the rectifier at an appropriate time to thereby regulate the DC motor. As will be explained, the rectifier 16 is designed as a forward / reverse bridge rectifier which can be controlled in such a way that it reverses the direction of the voltage and the current through the motor 12 and in this way for speed control and for reversing the direction of rotation serves.

The microprocessor shown in FIG. 1 can be any of the many microprocessors programmed

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digital multipurpose computers currently available on the market. Such a computer, which is suitable for the application according to the invention, is the microcomputer Intel 8080, which is sold by the Intel Corporation. Another ideally suited microprocessor used in embodiment 5 of this invention is a general purpose digital microcoded computer sold by General Electric Comp as a model CRD 8 microcomputer system.

The digital micro program computer CRD 8 is shown in FIG. 2, the main components of this computer being shown io. The main control unit of the computer includes a microcode control read only memory, ROM, 26 which is programmed with a microcode consisting of microinstructions stored in the ROM. The microinstructions, referred to as register, memory and I / O 15 channel drive signals, carried on a plurality of lines 28 control the fetching and interpretation of the instructions stored in main memory or memory 30, wherein they first recognize the command and then jump to a sequence of microinstructions in the control ROM 20 that perform the operations invoked by the instructions. The address of the next command to be interpreted by the microcode ROM is contained in a program counter register (PC) 32. Before interpreting each instruction, the microcode ROM increments the contents 25 of the program counter PC to point to the following instruction.

The microcode in the microcode ROM interprets subroutine calls by placing the address of the subroutine in a program counter intermediate register PCS 34 and then swapping the role of the program counter PC with the role of the program counter intermediate register PCS. Subroutine back branches are again interpreted by swapping the role of the latter two registers, causing the 35 command following the subroutine call to be interpreted next. If an external interrupt occurs at the processor, the processor changes the role of the program counter PC 32, the program counter intermediate register PCS 34, and a page register (Page) 36 with an interrupt program counter 38, an interrupt program selector intermediate register (IPCS) 40, and a breaker page register (IPAGE) 42. Interruption branches are interpreted by the microcode in the microcode ROM by the roles of these registers being exchanged back to their original roles.

External interruptions provided to the processor may or may not be triggered under program control by setting or resetting an interrupt trip flip-flop (not shown). If an external device wishes to interrupt the processor, this device issues a request to the interrupt line. If this request is present and the interrupt trigger flip-flop is set and the processor executes an interruptible instruction, then processor 55 begins executing the interrupt upon completion of the current instruction. Once interrupt processing begins, the interrupt program is responsible for remembering the external input device to remove its request from the interrupt line. 60 The processor memory is divided into pages, with a certain number of words per page.

Using page register 36, a command can access data anywhere in memory by specifying only one address regarding the header of the current 65 page of data (the page pointed to by the page register).

Data in main memory 30 can also be accessed directly by placing an address of the data word in one or three general purpose registers labeled RI, R2 and R3. These registers can also be used to store data. The collection of the three general-purpose registers and the additional registers 32 to 42 is referred to as a scratch pad memory.

In addition to the buffer registers, the processor further includes an accumulator 44, an instruction register 46 and a memory address register MAR 48, the latter addressing the main memory 30. During the operation of the processor, the instruction register 46 always contains the instruction which the microcode ROM last fetched from the main memory and which is currently interpreted. The main memory address register 48 always contains the address in the main memory to which the next memory read or write commands give access.

Arithmetic and logic operations are carried out by an arithmetic and logic unit ALU 50. Input signals of the ALU 50 are supplied from the accumulator 44 and from a bidirectional data and control bus 52.

Data is transmitted along the bus 52 within the processor. This bus allows data to be transferred from main memory 30, a selected latch register 46, or an input channel 54 to a command register 46, memory address register 48, or ALU 50. If there is an input / output command in the command register and if there is Command specifies that an output operation is to be performed, the processor outputs the contents of the ALU unit 50 to the output data channel via an output channel 56 and holds the input / output device (I / O device) which is to receive this data .

When a read operation is specified, the processor remembers the I / O device in question and outputs data to input channel 54. As shown in FIG. 2, the input / output devices in the present system are in the regulator and controller 14 included, which was previously described and is also included in Fig. 2.

The processor 10 also includes a clock generator, which is referred to as the processor clock 58 and generates a basic clock signal with a characteristic repetition frequency of 4.167 MHz. As shown in FIG. 2, the basic clock signal is fed to processor 10 for controlling the timing of information and commands by the processor, and also to the system to serve as a basic synchronous pulse to supply information into and out of the regulator and rectifier control unit clock. Although processor clock 58 is used in the present invention to provide system clock pulses, it should be understood that a basic clock signal may also be supplied to the processor from an external source to perform the same function.

Reference is now made to FIG. 3, which contains, primarily in the form of a block diagram, the blocks that make up the regulator and rectifier control unit 14. For reasons of clarity and simplification, FIG. 3 contains various components previously described in connection with FIGS. 1 and 2 and has been given the reference numerals previously used. The processor 10 provides basic clock signals to a system clock generator in the controller 14. The system clock generator 60 also receives a three-phase 60 Hz line signal from an external line source, not shown, and provides clock pulses to the system for use in synchronizing overall system operation the 60 Hz three-phase network to control the firing of the thyristors or SCRs to regulate the motor 12.

The regulator and control unit 14 further includes as one

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Part of a program 62 which is connected to the processor 10 and controls the operation of the controller in the control unit 14 in order to ultimately deliver the correct firing pulses to the thyristors or SCRs for regulating the DC motor. Although program 62 may be included in main memory 30 of FIG. 2, it should be noted that program 62 is considered part of regulator and rectifier control unit 14 because it performs certain logic functions that are important for the operation of overall control of the system.

3, the already mentioned speed reference 18 is shown as a digital switch (RPM) and as an on / off and forward / backward switch 18 ', which supply input signals to the processor 10 via a processor / system interface 64 . From the switches 18, a digital speed reference is supplied via a plurality of lines 66, which corresponds to the desired engine speed in revolutions per minute and is read into the processor and stored in the main memory or program 62 under the control of the processor.

Similarly, signals identifying the engine on / off switch and a switch which determines the desired forward or reverse direction of the engine are provided to the process by the on / off and forward / reverse switches 18 'via the Processor / system interface 64 fed on lines 68. A connection between the processor 10 and the processor / system interface 64 takes place via a plurality of lines 70, which consist of data input / output lines and control lines. As will be explained, the clock pulses from the system clock generator 60 are also supplied to the processor via these lines during the operation of the system.

An ignition logic 72 is provided in the regulator and control unit 14 in order to obtain information which corresponds to a desired ignition angle for the ignition of the thyristors in order to regulate the engine. This information is provided by the microprocessor via processor / system interface 64 on lines 74. The firing logic 72 essentially provides three signals, one signal being an unbreaker signal which is fed to the processor 10 on the line 76. The interrupt signal can either bypass the interface 64 or pass through the interface 64. Another of these signals is a conversion signal on line 78 to an analog-to-digital converter 80 to trigger that converter to convert the analog three-phase motor current to a counter value proportional to the strength of the direct current, which is transmitted via line 24 and interface 64 is fed to the processor. In addition, the firing logic 72 generates an firing pulse on a line 82 that leads to a thyristor selection and drive direction logic 84.

The thyristor selection and drive logic 84 receives digital information from the processor 10 via interface 64 on a plurality of lines 86. This information represents words or addresses in order to make the correct choice of the thyristors to be fired and to provide a special bridge of two bridges ( forward or backward) in the rectifier 16 to control the motor direction. The operation of the firing logic and the thyristor selection and drive direction logic is discussed in more detail below.

The above-mentioned speed signals on the lines 22 are supplied by a tachometer pulse and logic circuit 88, see FIG. 3, which receives pulses from a conventional digital tachometer 90. A special tachometer used in the present invention is available as the Model K827 from Avtron Corporation. This tachometer generator is designed as an optical device and contains two rotating disks with slots, which cause the generation of 1200 pulses per engine revolution through each disk. The output signal from the two disks is essentially designed as a rectangular curve with 1200 counting pulses per revolution of the tachometer shaft. These pulses from the two disks are mutually offset in phase by 90 °, so that the motor direction can be perceived by determining the shift in the phases of the pulses which are fed from the tachometer on lines 92 to the tachometer pulse counter 88. The manner of detection or detection is described below in connection with the description of the tachometer counter logic 88.

The rectifier 16 mentioned in FIG. 1 consists, as can be seen from FIG. 3, of a block which is designated as thyristors (SCRs) 94 and forward and backward pulse amplifiers 96 and 98, respectively. Amplifiers 96 and 98 are supplied with a plurality of lines 100 from thyristor select and drive direction logic 84 to select thyristor or address signals and drive direction select signals. During operation of the system, the information provided by the microprocessor to the thyristor select and drive direction logic causes the correct amplifier of the forward or reverse amplifiers 96 and 98 to be selected to apply a firing pulse to the thyristors 94 when the firing logic carries the firing pulse on the line 82 generated. The output firing pulses from the forward and reverse pulse amplifiers 96 and 98 are supplied to the thyristors 94 via lines 102 and 104, respectively. The power for the operation of the thyristors and thus of the DC motor 12 is supplied to the thyristors 94 by a 60 Hz three-phase network 106. When the thyristors are triggered, pulses are supplied via the lines 108 to supply the DC motor 12 with current to the To drive the motor. An overall understanding of the operation of the present invention can best be obtained from a detailed description of all of the logic blocks described in the regulator and rectifier control unit 14 of FIG. 3. The first of these blocks to be described is the processor / system interface shown in FIG. As shown in the left part of FIG. 4, all input and output signal lines to the processor / system interface that run to the left of the dashed line collectively include lines 70 as previously described in connection with FIG. 3. The information transmitted by processor 10 into system interface 64 comes from output channel 56, as previously explained in connection with FIG. 2. Basically, processor 10 transmits two types of instructions or instructions to the system interface. These commands direct the system interface in such a way that it either writes certain data from the processor into special registers in the system, for example into the ignition logic and the thyristor direction logic, or that it reads information from various addressed input devices, which is shown in the right part of FIG. 4 are.

Command data is supplied to the system interface from the output channel 56 of the processor via lines 110, 112, 114 and 116. The signals on lines 112, 110 and 114 represent instruction register bits from processor 10. When the processor provides a read instruction to the system interface, instruction register bits IR1 through IR3 on lines 112 are decoded in a BCD / decimal converter that serves as a decoder generate a read pulse identified as READ from an output terminal 6 of unit 118. The read pulse is generated when the command register bit IR4 on line 114 is a binary zero and is converted to a binary 1 by an inverter 120 to trigger a NOR gate 122 when a READ command register signal (IR signal ) is supplied with the binary value 1 by the processor. When the gate 122 is triggered, there is a binary O clock pulse at its output, which is sent to the D input terminal of the decoder 118 and in this way

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generates a READ pulse as shown on line 124. the READ pulse or read pulse is applied to two logic elements in the interface, first a D input connector of a second BCD / decimal converter that serves as a decoder 126 and a trigger input connector (EN) of an 8-bit multiplexer 128.

Decoder 126 and multiplexer 128 receive instruction register bits IR5 through IR7 on line 110. When these bits are decoded by a decoder 126 as an O command for a reader, the decoder generates an RDVO signal at its O output port on line 130, as shown in FIG. 4. The RDVO signal is fed to the ignition logic 72, the task of which is subsequently explained. Further, when a READ instruction is issued by the processor, instruction register bits IR5 through IR7, which are provided to a SEL input of multiplexer 128, are decoded to share data from one of the input devices in the right part of FIG. 4 to lead time-shared collector line 132 to the data processor, the input information designated as IDO to ID7 being fed to the input channel 54 of the processor 10 (cf. FIG. 2).

When the processor issues a write command, the command is decoded in decoder 118 in the manner previously described for the READ pulse, and a write pulse is thus applied to output port 7 on line 134. The write pulse on line 134 is supplied to decoder 136 and logic driver 138. Decoder 136 also receives command register bits IR5 through IR7 on lines 110 and decodes these bits to generate an output signal from two output signals (WDVI or WDV3) according to the binary bit configuration. The latter two signals, designated WDV1, WDV3 for writing devices, are applied to the firing logic and the thyristor select and drive direction logic for reasons that will be explained. The write pulse applied to a C or clock input terminal of driver 138 allows data on a plurality of lines 140 to be supplied from processor output channel 56 to firing logic and thyristor select and drive direction logic as signals WDV0 through WDB7.

Reference is now made to the input device blocks 18, 60, 80, 88 in the right part of FIG. 4. It can be seen that each of these devices is provided with its own input device number, such as input device 1 for system clock generator 60. This device number corresponds to the address of the device in question, which the processor provides the system interface with, if desired, information through read multiplexer 128 from any of the devices into the processor. For example, if the data processor provides a read command to generate a read pulse on line 124, with an address on line 110 specifying the address for device 1, system clock input data bits IDI B0 through IDI B7 are cleared by multiplexer 128 the input data bus 132 is channeled or routed and transferred to the data processor memory. All transfers of input data from the input devices to the processor are handled in the manner just described for system clock 60, except that the special address provided to the 8-bit multiplexor 128 routes the information from the addressed device to the processor.

Referring now to FIGS. 5 and 6, FIG. 5 is a block diagram of device 1, system clock generator 60, and FIG. 6 is a timing diagram useful for understanding the operation of the system clock. The three-phase mains voltage is fed to three conventional square-wave amplifiers 142, the corresponding square-wave output signals with the designations 0 1.02 and 0 3

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generate lines 144, 145 and 146, respectively. The three signals - 01 through 0 3 are applied to the corresponding inputs of a D-connector of a conventional D-type flip-flop from three similar phase zero crossing logic or edge detectors 148, 150 and 152. Since the edge detectors 148 to 152 are constructed similarly, only the edge detector 148 is shown in detail in the dashed lines in FIG. 5.

The edge detectors all operate in the following manner as described with the edge detector 148. When the 0 1 signal on line 144 goes positive, the D input terminal of an FA0 1 flip-flop is energized to achieve a set state when the clock signal is applied from the processor to a CLK input terminal of that flip-flop. When the basic clock signal goes to a positive value, the FA0 1 flip-flop is set and causes the Q output terminal of this flip-flop to be binary

1 state transitions, producing an IDI B0 signal on line 154. The IDIBO signal is applied as an input signal to a negative exclusive OR gate 156 and to the D terminal of a second flip-flop, which is designated as FB0 1. When the next basic clock signal occurs, the FB0 1 flip-flop reaches a set state, the Q output connection going to a binary 1 and thereby causing the exclusive OR gate 156 to generate an output pulse 0 1ZR0X on line 158, see FIG. 5 The FA0 1 and FB0 1 flip-flops essentially form one

2-bit shift register, the outputs of which are fed to gate 156. The FA0 1 input synchronizes the square wave signal from the 0 1 input with the system clock. It can therefore be seen that the output 0 1ZR0X of the exclusive OR gate 156 generates a pulse with the width of the clock base pulse every time the sine curve at the input passes through a zero crossing with a period of approximately 2.7 milliseconds. The 0 lZROX signal is fed to the input of an OR gate 160 in connection with signals 0 2ZR0X and 0 3ZR0X from the corresponding edge detectors 150 and 152 on lines 162 and 164, respectively. The signals 0 1ZR0X to 0 3ZR0X correspond to phases A, B and C of the input mains voltage.

The output signal of the OR gate 160 is fed to a K input terminal of a ZROX-JK flip-flop 166. The flip-flop 166 receives the basic clock signal at the CLK input connection in order to trigger this flip-flop so that it is set or reset in accordance with the state of the input signal applied by the OR gate 160 to the K connection. The ZROX flip-flop generates a ZROX signal or zero crossing signal at its Q output terminal, which is fed to the tacho pulse counter and logic circuit and two counters 168 and 170. Referring to the timing diagram of FIG. 6, it can be seen that the ZROX flip-flop 166 generates a ZROX signal each time a phase voltage crosses the input voltage, or 6 pulses are generated on a 360 ° line cycle, the ZROX Signal has a pulse with the width of a basic clock width.

5 and 6 that the three signals ID1B0 to ID1B2 (which together form the lines 172) can be used by the data processor to define any 60 ° interval within a 360 ° phase cycle of the mains voltage . This is shown in Figure 6 with reference to the 0 3 rectangle (IDIB2), showing the different degrees of the sine input curve and the different zero crossings at the 60 ° intervals. As can be seen from the relationships between the IDI B0 to ID1B3 signals, it is relatively easy to decode these signals to determine which interval out of the 6 intervals of a 360 ° cycle is present at any given time . For example, if

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If the first interval runs from 0 to 60 °, this interval, if IDI B0 is a binary 1, IDI B1 is a binary 0 and ID1B2 is a binary 1, by decoding these 3 binary bits as the first interval of the 360 ° cycle. A similar decoding can be carried out for the 60 ° to 120 ° intervals, the 120 ° to 180 ° intervals etc.

Referring back to FIG. 5, the aforementioned counters 168 and 170 are shown in conjunction with a counter 174 dividing by value 45. The 4.167 MHz base clock is applied to the input of counter 174, which divides by 45, which divides the clock base pulses down to produce a signal on line 176 with a pulse duration of 11 microseconds. As shown in FIG. 5, the pulse on line 176 is applied to an AND gate 178 for a duration of 11 microseconds and further on line 180 to the ignition logic. As further indicated on line 180, the 11 microsecond pulse is approximately equal to a quarter of an electrical degree of the line voltage applied to square wave amplifiers 142. The 11 microsecond duration pulses are fed through an AND gate 178 to a counter 168 dividing by 8 to generate 88 microsecond duration time base pulses each corresponding to approximately 2 electrical degrees of the line voltage. The 88 microsecond duration pulses are supplied to the ignition logic, a NOR gate 184 and counter 170 via line 182. The counter is a counter dividing by the value 32, which divides the 88 microsecond duration pulses by the value 32. As long as counter 170 is not at a counter value of 31, NOR gate 184 provides a clock stop signal CT31 with a binary 1 on line 186 as a second input to AND gate 178 to allow the pulses to be 11 Microsecond duration through this gate to counter 168. When counter 170 reaches a counter value of 31, in conjunction with a binary 1 pulse (88 microseconds duration), NOR gate 104 is triggered to provide a binary 0 inhibit signal to gate 178, causing counters 168 and 170 are prevented from counting beyond the number 31. The counter consisting of counters 168 and 170 remains at a count 31 until the next zero crossing or ZROX signal is generated by flip-flop 166 to reset the counters to 0, as shown in the timing relationships of FIG. 6. It can therefore be seen that the counter counts from 0 to 31 between the individual zero crossings of the input voltage. As can be seen in FIG. 5, it can be seen that the output signals IDlB7bisIDlB3 from the counter 170 on the lines 188 determine the time within the 60 ° interval as defined by the signal IDI B0 to ID1B2. The IDI B3 through ID1B7 signals are combined with the ID1B0 through ID1B2 signals to form lines 190 that are fed to the 8-bit multiplexer 128 of the processor / system interface, see FIG. 4.

It can be seen that the processor 10, by reading the system clock, can determine the 60 ° interval of a 360 ° cycle of the input curve by looking at bits ID1B0 to IDI B2 while at the same time looking at the number of 2 °. Increments (pulses with 88 microseconds duration) of the line phase voltage determined, which have passed since the last zero crossing (ZR0X).

Referring now to FIGS. 7 and 8, FIG. 7 is a detailed block diagram of the tachometer counter and logic circuit and FIG. 8 is a timing diagram useful for understanding the operation of this logic circuit. As already mentioned in connection with FIG. 3, the tachometer used in the present embodiment generates two rectangular output signals, each output signal generating 1200 counts per revolution of the tachometer shaft. These two signals are carried on lines 92, see FIG. 7, as two input signals, the signal TACH input signal 1 is fed to the operational amplifier 192, and a TACH input signal 2 is fed to a D input terminal of a TACH Rev flip-flop 194. The temporal relationships shown in FIG. 8 show a 90 ° phase shift between the TACH input signal 1 and the TACH input signal 2. The TACH input signal 1 is connected via amplifier 192 to a D input terminal of an edge-triggered TACH flip-flop F / Fl from D-type supplied, which receives the basic clock signal from the processor at its CLK connection. As shown in FIG. 8, the TACH flip-flop F / Fl swings from the set to the reset state in accordance with the state of the TACH input signal 1 each time the basic clock signal is triggered by the processor of this flip-flop. The Q-output connection of the TACH-FI flip-flop F / Fl is connected to the D-input connection of a second flip-flop, referred to as TACH F / F2, which also receives the basic clock at its CLK input connection. These two flip-flops essentially represent a 2-bit shift register that functions in a manner similar to that of the edge detector flip-flops described above in FIG. 5 in the system clock generator. The output of the TACH flip-flops F / Fl and F / F2 is fed via lines 196 and 198 to a negative exclusive OR gate 200. The OR gate effectively differentiates the TACH input pulse 1, which is applied via lines 196 and 198, to generate a pulse with a clock width of the basic clock each time the TACH input signal 1 changes. Since the TACH input signal 1 generates 200 pulses per revolution of the tachometer shaft, the output of the exclusive OR gate 200 generates 2400 pulses per revolution of the tachometer shaft and generates a TACH input signal X2, which is shown on line 202 and in FIG. 8.

TACH input signal X2 on line 202 is fed to a CLK input terminal of a tachometer pulse counter 204 to cause the counter to accumulate the tachometer pulses read from the tachometer. The TACH input signal X2 is also fed to a presettable LSB input connection of the counter 204, the purpose of which is explained below. It should be noted that the ZROX signal from the system clock generator is also supplied to a presettable input connection of the counter 204 and also to a CLK input connection of a tacho pulse latch circuit 206. It should be remembered from the above description of the system clock generator that a ZROX signal is always generated when the input phase voltages have a zero crossing and pass through 0. In this way, it can be seen that the tachometer 204 is reset to a binary zero state when a zero crossing pulse occurs. In this way, it is evident that the tacho pulse counter 204 accumulates count values which are characteristic of the motor revolutions per 60 ° interval of a 60 Hz input signal.

As shown in FIG. 8, the tachometer pulse counter 204 is always reset to a zero state when a ZROX signal occurs. It is also important to note, as shown in FIGS. 7 and 8, that the content of the tacho pulse counter 204 is transmitted to the tacho pulse latch circuit 206 when a ZROX signal occurs. Although not shown in FIGS. 6 and 7, it should be noted that the content of the tacho pulse counter on the leading edge of the ZROX signal is transferred to the tacho pulse lock and that the tacho pulse counter is reset on the trailing edge of this signal.

Reference is now made again to the presettable LSB input connection of the counter 204. The purpose of the TACH input signal X2 being fed to the latter port

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is to set the least significant bit of the tacho pulse counter to a binary 1 or to set it in case a tacho pulse occurs at the time of a ZROX signal or a zero crossing. If a ZROX signal occurs simultaneously with a TACH input signal X2, the specification of the least significant bit ensures that every count value that occurs during a zero crossing is not ignored, but is stored in the tachometer pulse counter. Once the content of the tachometer pulse counter is loaded into the tachometer pulse latch 206, this information is available in the form of the signals ID3B0 to ID3B7 on the lines 22 for the processor to read out the motor revolutions per 60 ° when the processor addresses the device 3.

7 and 8, logic for determining the direction of rotation of the motor is also shown. The direction of rotation of the motor is determined by a flip-flop 194, also called a TACH-Rev flip-flop, which receives the TACH input signal 2 at its D input terminal. The operation of flip-flop 134 is shown in FIG. 8, which shows the operation of this flip-flop when the motor is running in the forward or reverse direction. It should be noted that the TACH input signal 1 is always 90 ° ahead of the TACH input signal 2 when the motor is running in the forward direction. When the motor is running in the forward direction, see FIG. 8, the TACH Rev flip-flop 194 never reaches the set state due to the fact

that the TACH input signal 1, which triggers the flip-flop 194 via the line 208, constantly goes into the set state before the TACH input signal 2 in each case reaches a binary 1 state. The edge triggered flip-flop 194 is therefore never set. In the reverse direction, however, compare the right-hand side of FIG. 8 that if the TACH input signal 2 leads the TACH input signal 1 by 90 °, the TACH Rev flip-flop 194 reaches a set state when the TACH Flip-flop 1 reaches a set state. When the Rev flip-flop reaches the set state, its Q output connector generates an ID0B4 signal with a binary 1 on one of the lines 22 to the processor / system interface. If the TACH input signal 2 leads the TACH input signal 1, the ID0B4 signal with a binary value 1 informs the data processor that the motor is running in the reverse direction.

Reference is now made to the ignition logic of FIG. 9, which shows this logic in the form of a block diagram. In conjunction with FIG. 9, reference is also made to FIG. 10, which shows a timing diagram that indicates the temporal relationship between the various signals within the ignition logic 72. As previously explained, the primary purpose of the firing logic is to provide firing pulses on line 82 to the thyristor select and drive direction logic 84, as shown in FIG. 3. In addition, the firing logic generates a conversion pulse to the analog to digital converter on line 78. Operation of the firing logic informs the processor of an interrupt signal on line 210 of FIG. 9 to begin the firing angle calculation process to generate an firing pulse. to fire a thyristor at the right time.

4, reference is now made to the description of the operation of the ignition logic. From the foregoing description, it should be remembered that the processor must generate a write command and address of a device to send a command to that device. For the ignition logic, decoder 136 generates a write signal for device 1, WDV1, which is shown in FIGS. 4 and 10. 10, the WDVl signal transitions from a binary 1 to a binary zero state when the WDVl signal on line 212 causes a load counter flip-flop 214 to receive the binary 0 signal at the CLR input terminal which resets this flip-flop. At the same time, the WDV1 signal is inverted into a binary 1 signal by an inverter 216, with a trigger signal being applied to an EN input terminal of a write data latch 218, whereby the data (WDB0 through WDB7) is supplied by the drivers 138 of FIG. 4 can be supplied on lines 220.

Referring now to FIGS. 9 and 10, it is noted that the appearance of the first 88 microsecond pulse appears on line 182 after the WDV1 signal clocks the load counter flip-flop 214, thereby causing that the counter now assumes a set state and generates a binary 1 signal on its Q output connection on line 222. The binary 1 signal on line 222 is supplied to an inverter input load terminal of a down counter 224. As shown in FIG. 10, the load counter flip-flop, when set and in conjunction with an 88 microsecond pulse, provides the down counter 22 with either a 20 second delay signal or TIMTGO signal. The TIMTGO signal is a binary arrangement of bits which are entered into the down counter by the data processor and which characterize or are proportional to the firing angle of the thyristors. If a TIMTGO signal is not given in the down counter, then a data word is entered which represents a delay of 20 °. A more detailed description of the task and purpose of the TIMTG0 and 20 ° delay signals or values is given below.

Reference is now made again to an AND gate 226 of FIG. 9. The AND gate 226 is triggered by an output signal with the binary value 1 from the Q output terminal of a first detector flip-flop 228. When flip-flop 228 is in the reset state, the first 11 microsecond pulse on line 180 applied to gate 226 causes the contents of counter 224 to be clocked or counted via line 230 and an inverter 232 to do so Feeds a pulse of 11 microseconds in duration to a CLK connection of the down counter. The timing for the down counter 224 timing is shown on the 11 microsecond line and on the down counter cell of FIG. 10. The down counter continues counting down to a specific value until a decoder 234 for a count 14 detects from the counter over a plurality of lines 236. At a count of 14 and a pulse of 11 microseconds from gate 226, decoder 234 generates a pulse to fire a monostable conversion multivibrator 238. The monostable multivibrator 238 generates a conversion pulse of 8 microseconds in duration on the line 78, which is fed to an analog / digital converter 80 of FIG. 3 at the time shown in FIG. 10. This pulse starts the analog-to-digital converter and lets it begin performing an analog-to-digital conversion of the motor current on lines 24 for subsequent use by the processor.

The down counter continues to count down to a special value zero, as shown in FIG. 10. When the down counter reaches zero count, which is determined by lines 242 from the down counter by a zero count decoder 240, zero count decoder 240 generates a pulse on line 244, which is a D terminal of the detector flip-flop 1,228. When the next basic clock signal occurs, which is fed to the CLK connection of the flip-flop 228,

this flip-flop goes into the set state and causes a binary 0 signal to be applied to the AND gate 226 to prevent the 11 microsecond clock pulses from reaching the down counter 224. this will

5

10th

15

20th

25th

30th

35

40

45

50

55

60

65

632 615 10

by the remark "stop down counter" in Fig. 10 acts ignition networks, which is shown to regulate a match. If the detector flip-flop 228 in a set current motor is known. Such a conventional state goes, the Q output connector goes to a binary 1, bridge is manufactured by General Electric Comp, and at the same time to energize an input of an AND gate 246 sold under the name Siltrol 1, which is integrated as a sta- and to supply a set signal with a binary value 1 to a table conversion and control element for adjustable rotary D connection of a second detector flip-flop 248. Number drives under the name IC3610 is known.

It should be noted, compare FIG. 10 that the AND gate 246 in three current transformers, 260, 262 and 264, is triggered one at a time when the flip-flop 228 is assigned 0 A to 0 C in the line phase voltage. Three transformers

set state, since the flip-flop at that time mators supply AC input signals to the three-phase

is reset. The output of the AND gate 246 now supplies io sen bridge summing amplifier 258 via corresponding lines

a trigger signal to a J input terminal of a break, the output signal of the rectifier to the device flip-flop 245, which is the generation of an interrupt converter 80, the average of the three input currents. How signals work for the data processor. The interrupt already mentioned, the analog-to-digital converter 80 has a signal that causes the data processor to operate in an interrupt-conventional fashion, with such a converter entering the processing subroutine to model the calculations of the ignition device 15 Analog Devices Inc. ADC-8QU manufactured kels to start firing the thyristors. becomes. This special converter is a complete 8-bit wall

It should be noted that the first basic clock signal, which follows the FJip-flop 28 with successive approximation and high, sets the flip-flop 248, speed that the input analog signal on the line

whereby its Q output terminal goes to a binary 0 device 256 upon receipt of an input command which, as a result, excites the AND gate 246. This causes the generation pulse on line 78 to be a short pulse that converts an INT flip-flop 250 to a digital value. In this particular converter, as shown in FIG. 10, the current magnitude and the eighth bit DET-FF1 and DET-FF2 signals are indicated by the overlap between the designated 7 of the 8 bits. The polarity of the current can also be designated. It is to the above explanations-

ner recognize that simultaneously with the setting of the interruption of the ignition logic according to FIG. 9, from which it follows that

flip-flops 250 the output signal from AND gate 246 25 that the ignition logic generates a conversion pulse of 8 microseconds

a monostable ignition pulse multivibrator 252 (FP) for the duration on line 78 to the analog / digital converter.

leads to an ignition pulse of 23 microseconds duration when the down counter reaches a count of 14,

on the line 82 of the thyristor selection and drive direction lo This conversion pulse starts to supply the analog / digital converter 84. The generation of the firing pulse is at 80 to convert the analog motor current on line 256 into one

10, at which time a thyristor 30 digital value for subsequent transfer to the data pro-

couple is fired simultaneously with the generation of the interrupt signal processor via the processor interface as data bits ID5B0 to. The ignition logic remains in the present or pre-ID5B7 to be converted on line 24.

given state until another WDV1 signal is on the line. As shown in FIG. 4, the transfer of motor current device 212 is received and causes new data to be performed on line 24 when the analog / digital

the down counter 224 in the manner just described 35 converter 80 (device 5) via the 8-bit multiplexer 128

will give. is addressed to the data via the bus 132

When the down counter is loaded with new data, feed the processor. The addressing of the analog / digital

If the decoder provides a reset signal converter for the count value zero, this is achieved in that the data processor on line 244 to flip-flop 228, whereby this flip-flop enters a correct address in bits IR5 to IR7 and this is now allowed to reach a reset state of 40 bits to the SEL terminal of the multiplexer 128 together with and at the same time to reset the flip-flop 248. When the flip-to-READ pulse on the trigger input signal of the multi

flop 228 resets, its Q output goes to the plexers. The correct binary bit configuration of the bits line 254 to the binary value 1, whereby the AND gate 226 IR5 to IR7 directs the motor current reading from the analog / digital

is triggered and the counter 224 is allowed to count, night converter 80 through the multiplexer on the bus line to which this counter has been loaded. As shown in Fig. 10, 45132 for transfer to the data processor.

IIB and the thyristor select and ristor pairs, an RDVO reader zero signal on drive direction logic 84 is now referred to. The primary

Line 130 to an erase input terminal CLR for the purpose of the dial and drive direction logic is one

Send break flip-flops 250 to transfer this flip-flop to the data word or address from the data processor

Preparation for the transmission of a further submissions 266 on the correct data lines 266 (WDB0 to refraction signal to the processor immediately after generation WDB7) from driver 138 of FIG. 4. This data

reset an ignition pulse to the thyristors. word represents a binary bit sequence that is generated by a WDV3 signal

Referring now to Figs. 1A and IIB, line 270 from decoder 116 of Fig. 4 into a thyri, with Fig. 11A at the top of Fig. IIB, for a figure to store control or select register 268 is loaded. When the probilde that the logic of the select and drive direction logic 84 55 sends a write command that addresses the writer 3 and an electrical schematic of the thyristor, the WDV3 signal on line 270 goes to a forward and reverse drive bridge in detail binary zero above and is shown by an inverter 272 to one. Also shown is the analog-to-digital converter 80, which inverts binary 1, and thus provides a trip charge analog motor current over line 256 from the signal to register 268 to add a thyristor pair address to the conventional three-phase bridge summing rectifier circuit 60 Load register. The outputs from all stages or bits of the 258 receive. In Fig. IIA, the three-phase 60 Hz mains voltage register 268 are up to one level with a corresponding voltage (also 50 Hz mains voltage) as 0 A, 0 B and 0 C on the AND gate from a variety of AND gates 274, 276, 278 and lines 106 are connected to the correspondingly assigned anodes and 280. The output signal from the individual AND cathodes of the forward and backward thyristor bridges gates is designated with a signal which is assigned in each of the pre-gates, each of which consists of 6 thyristors, with PI to P3 65 forward and backward bridges one of the thyristors ent and N1 to N3, see Fig. 11A. The company speaks. For example, an output signal PI from the forward and backward thyristor bridges is not described in AND gate 274 as the thyristor PI in the forward or backward details, since they are conventional brittle thyristor bridges. If desired, a special one

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To fire the thyristor pair in one of the bridges, a binary is shown on the right column as a FINVAL count.

The FINVAL table is triggered from the relationship AND gates 274 through 280 so that it sends its appropriate control signals to the appropriate forward / backward FINVAL = 245.8 Cos -1 (3VT / 7iVln) forward drive switching amplifier circuits (FWD / REV) supply. 5

These FWD / REV drive circuits have a conventionally calculated, where 245.8 is equal to the number of pulses of 11 positions and are designated with 282,284,286,288. Each microsecond duration is that the circuit fed to the down counter corresponds to an equal number thyristor to tough down the counter per electrical degree in the forward and reverse drive bridges. That's how it works. VLN is defined as the line earth voltage of the input line voltage, for example the PI-FBD / REV drive circuit 282 via line.

gen 290 and 292 connected to corresponding control electrodes of the thyristor PI in each bridge. Similar connections Table I exist from the drive circuit 284 to the P2 Torelek voltage against FINVAL counts and from the drive circuits 286 and 288 to the control electrodes N2 and N3. In FIG. IIB it can be seen 15 that only four of the AND gates which generate the PI to N3 signals and the drive circuits which are assigned to the thyristors PI to N3 are shown. For reasons of simplicity, the AND gate and the drive electronics for the thyristors P3 and N3 only come out of the selector register 268 as dashed 20 lines.

It is important to note that one bit of the firing register 268 sends an FWD / REV signal on line 294 to all FWD /

REV drive circuits 282 to 288 delivers. The drive circuits 282 through 288 are conventional driver or circuitry 25 of a known embodiment capable of receiving logic input signals to selectively switch their output signals between one of two lines leading out of each drive circuit. For example, when the drive circuit 282 is operating to activate or fire the forward bridge thyristor PI, a binary 1 signal is provided from register 268 as an input to gate 274 and when the firing pulse occurs on line 82 and the firing logic, gate 274 is triggered and passes pulses through the drive circuit PI to the forward thyristor PI. On the other hand, the drive circuit 282 is activated if the FWD / REV bit has the binary value 0,

to transmit the firing pulse on line 292 to the thyristor PI of the reverse thyristors. In the present embodiment, and when operating the thyristors of the rectifier 40, it is desirable to always pair the thyristors,

such as firing PI and N2 in the forward or reverse bridges. The word loaded into register 268 always has two binary bits that correspond to the thyristors to be fired. For example, binary 1, which is to fire the thyristor PI, activates the gate 274, and the binary 1, which is to fire the thyristor N2, activates the gate 280, the other gates not being energized or activated. In order to fully understand and appreciate the overall operation of the system according to the invention, it is considered advantageous to describe how the firing angle for firing the thyristor pairs in the system is derived.

Reference is now made to FIG. 12, which shows the connexion. FIG. 12 is again referred to, wherein the relationship between the three-phase mains voltages 0 A, 0 B shows the derivative of the TIMTGO equation, and and 0 C and a plot shows how the firing TIMTGO is a value proportional to the firing angle, the angle designated FINVAL, for the thyristor pairs is loaded into the down counter 224 of FIG. 9 to achieve the rich - is developed to generate a variable value that will fire for the right pair of thyristors at the right time. By definition, a signal TIMTGO is characteristic that is to be spread:

represents a calculated value that is proportional to the ignition angle. It is known that the ignition 6o TIMTGO = FINVAL - (NEWTIM + 1) • 8 - TP.

bracket for controlling thyristor rectifiers of the invented

The type or sequence used to measure the downward point to the ignition point of the thyristor pair. counter is loaded with the value TIMTGO, the value according to the invention is explained by the following steps:

VAL, to generate a motor terminal voltage that is equal to 65 1. The processor calculates the FINVAL value, which is the ignition VT, obtained by looking up the table at a specific angle, which forms the current output signal of the controller; rather with the representation or arrangement according to Table I 2. The processor then reads the system clock (on. The variable stored in the memory, the ignition angle, direction 1), as previously in connection with FIGS. 4 and 5

Motor terminal voltage

Counts

-272

715

-256

671

-240

640

-224

615

-208

592 -

-192

572

-176

553

-160

530

-144

519

-128

503

-112

487

-960

472

-800

457

-040

443

-480

428

-320

414

-160

400

0

386

160

372

320

358

480

343

40

329

800

314

960

300

112

284

128

269

144

253

160

236

176

218

192

199

203

179

224

157

240

132

256

101

272

57

632615

12

to establish or define the 60 ° interval in the input power cycle, and further to define a time within that interval, and then calculate the value of NEWTIM and TIMGO.

3. The processor then reads the system clock repeatedly until the value of the clock is NEWTIM, then the processor works to load the down counter with TIMTGO. NEWTIM is the processor calculated value that the program uses to indicate the time at which TIMTGO should be loaded into the down counter so that the down counter starts counting at the right time. Loading at the time specified by NEWTIM ensures that the program is synchronized with the firing of the thyristor pairs.

The aforementioned CRD8 processor uses a 300 nanosecond memory which allows step 2 to be carried out in approximately 120 microseconds. This period of 120 microseconds is slightly less than the duration of two 88 microsecond pulses developed by system clock 360 of FIG. 5. Therefore, if TCLOCK represents the time given by bits IDI B3 to IDI B7 of the system clock at the beginning of step 2 mentioned, and if NEWTIM is given by NEWTIM = TCLOCK + 2 (processor calculation time for NEWTIM and TIMTGO), step becomes 2 always completed in time to load the down counter 224 at NEWTIM + 1 before the system clock transition. Size +1, appended to NEWTIM in Figure 12, indicates the 88 microsecond clock period required to load the down counter from the processor. 5, counter 170 counts from zero crossing to zero crossing (ZR0X) from zero to 31. It is possible for the counter to remain at a count 31 for an interval equal to 32 counts, the last count of counter 170 being made longer than the previous counts. In this case, if NEWTIM is equal to or greater than 31, a fast pulse or 11 microsecond pulse must be added to the value Tp that the 31st interval of the system clock is longer. If NEWTIM is greater than 31, the system must also be corrected to reset the system clock at the next zero crossing (CR0X).

FINVAL = Tp + (NEWTIM + 1) + TIMTGO, see Fig. 12. In the present embodiment, FINVAL, Tp and TIMTGO are expressed in fast counts or 11 microsecond pulses, and NEWTIM + 1 is expressed in slow counts or 88 microsecond pulses. Therefore, to convert to equivalent values, FINVAL = Tp + 8 (NEWTIM + 1) -l- TIMTGO applies.

The multiplication factor 8 should adjust NEWTIM + 1 to Tp and TIMTGO, since it takes 8 fast counts (pulses of 11 microseconds in duration) for a slow count (pulses of 88 microseconds in duration).

Development of the TIMTGO equation continues and substitution of the value of TCLOCK for NEWTIM in the equation provides: TIMTGO = FINVAL - Tp -8 (TCLOCK + 3).

It should be remembered that it takes approximately two slow clock pulses to read the 360 ° system clock and to calculate NEWTIM and TIMTGO. This time must therefore be added in NEWTIM by adding +2. Therefore, if TCLOCK is the time read by the processor and if two slow clock pulses are added at dead time to compensate for the computation time, then: NEWTIM + 1 = TCLOCK + 3, as shown in the above equation for TIMTGO.

To calculate TIMTGO, since Tp is present in slow clock pulses, TIMTGO = FINVAL - Tp - 8 x TCLOCK

- 24. Note expression 8 (TCLOCK + 3) above, where three slow pulses equals 24 fast pulses.

Referring also to FIG. 12, Tp is defined as the angle from the phase / phase cross point that defines the zero firing angle for the thyristor to be fired to the next phase zero crossing. Another way to confirm this is to look at the next phase zero crossing in the 0 ° to 360 ° cycle and subtract the reference angle of the cell pair to be ignited from this angle, which gives the magnitude Tp. If, for example, the closest zero crossing is given by phase 0 C, which runs at 60 ° to negative values, see Fig. 12, and if the thyristor pairs P1 / N2 are to be fired, then the reference angle is 30 ° (60 ° -30 ° = Tp), where 30 ° is the angle between the 0

0 A / OC crossing point and the zero crossing of 0C is. If Tp + 24 = TABTP, then TIMTGO = FINVAL - 8 x TCLOCK - TABTP - CORR, where CORR is the correction for the aforementioned long 31st pulse of the system clock.

In running the program, the TABTP value is obtained from a lookup table, as shown in Table II. Referring to Table II, it can be seen that TABTP Table 11 contains entries in the fast counts that identify degree values that serve as an equivalent or offset in the TIMTGO equation to determine the actual time interval at the time compensate within which the system is read out by the computer.

6 and Table II, reference is made to the fact that the system clock bits ID1B0 to IDI B2, which represent the 3 most significant bits, can be decoded into 60 ° intervals, which are numbered 1 to 6 and are designated as KOCT in the left column of Table II, as shown in Fig. 6. Reference is now made to the second column from the left of Table II, and it can be seen that a table labeled TABPH, which indicates the number of zero crossings, is stored in sequential locations labeled PHA1 through PHA6 in memory where each of the locations corresponds to one of the phases in question, as is also shown in Table II.

During the time to read the system clock, the computer uses the KOCT number to address the corresponding one of the PHA locations in the TABPH, as shown in Table II. For example, it can be seen that KOCT5 of FIG. 6 and in the left column of Table II is equal to the phase zero crossing PHA1 or 0 A, that KOCT4 is equal to the phase zero crossing PHA2 or 0C etc.

The processor includes a thyristor pair firing counter, designated PH in a column of Table II. The PH counter is incremented or updated by a specific value each time a thyristor pair is fired during the program. The ignition process takes place in a special sequence. In order to get a correct TABTP value for the calculation of TIMTGO, the address developed from the difference between PHA and PH (PHA minus PH) values is used to develop an address for the TABTP table. The thyristor pair counter PH always indicates a special pair of thyristors to be fired. For example, if the thyristor pair counter PH is at the value

1, the pair of thyristors P1 / N2 is fired, while the pair P3 / N2 is fired when the counter is at the value 6, etc.

There are 6 address entries for each of the memory locations TABTP, each of these 6 addresses being representative of one of the 6 zero crossings in a complete cycle of the input voltage. It should be noted that each of the thyristor pairs is fired once every 60 ° or 6 firings per 360 ° cycle of the input sine5

10th

15

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25th

30th

35

40

45

50

55

60

65

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curve owns. It should also be noted that the PHAO zero crossing number does not always correspond to the PH count. This is due to the fact that any given pair of cells can be ignited at any 60 ° interval during a 360 ° cycle period. It is this difference between the PHA numbers and the numbers of the PH counter that allows the derivation of addresses for the TABTP table in order to obtain from the table the correct number of counters in fast counts for insertion into the TIMTGO equation.

Table II

60 ° - TABPH

SCR

FWD / REV

PHA-PH

TABTP

Inter 0 -Null-

Thyri-

Thyristor

TABTP

Table contents vall through

sturgeon-

pair, tongued

table

(fast gear pair counter det =

add

Counts)

KOCTPHA -

PH

5 1-0 A -

1

P1 / N2 =

0

-105 = 30 °

4 2-0 C -

2nd

P1 / N3 =

0

6 3-0 B -

3rd

P2 / N3 =

0

2 4-0 A -

4th

P2 / N1 =

0

3 5-0 C -

5

P3 / N1 =

0

1 6-0 B -

6

P3 / N2 =

0

-

2nd

P1 / N3

-1

-362 = -90 °

-

3rd

P2 / N3

-1

-

4th

P2 / N1

-1

-

5

P3 / N1

-1

-

6 1

P3 / N2 P1 / N2

-1

-

3rd

P2 / N3

-2

O

O

00

I.

II

<£> 1

-

4th

P2 / N1

-2

-

5

P3 / N1

-2

-

6

P3 / N2

-2

-

1

P1 / N2

4th

-

2nd

P1 / N3

4th

-

4th

P2 / N1

-3

667 = + 180 °

-

5

P3 / N1

-3

-

6

P3 / N2

-3

-

1

P1 / N2

3rd

-

2nd

P1 / N3

3rd

-

3rd

P2 / N3

3rd

-

5

P3 / N1

-4

410 = + 90 °

-

6

P3 / N2

-4

-

1

P1 / N2

2nd

-

2nd

P1 / N3

2nd

-

3rd

P2 / N3

2nd

-

4th

P2 / N1

2nd

5 1-0 A-

6

P3 / N2 =

-5

153 = + 30 °

4 2-0 C -

1

P1 / N2 =

1

6 3-0 B -

2nd

P1 / N3 =

1

2 4-0 A -

3rd

P2 / N3 =

1

3 5-0 B -

4th

P2 / N1 =

1

1 6-0 C -

5

P3 / N1 =

1

Before proceeding with a description of the program for controlling the overall operation of the regulating and control system according to the invention, reference is now made to FIG. 13, which shows the overall operation of the system in a simplified bar diagram in order to generate the value TIMTGO proportional to the ignition angle in order to to ignite the thyristor pairs in the rectifier 16 of FIG. 1. To understand the operation of FIG. 13, it is considered advantageous to first assume that any pair of thyristors in the rectifier has just fired. As already explained, the INT flip-flop 250 of FIG. 9 generates an interrupt signal to the processor when a pair of thyristors is fired. This interrupt signal causes the processor to jump to an interrupt subroutine which causes the analog / digital converter 80 to be read into the computer. As shown, the processor at this time loads the down counter with a count that is proportional to a 20 ° delay. The present invention is capable of operating in either a continuous or non-continuous power mode and the purpose for the 20 ° delay to be loaded into the down counter 224 of FIG. 9 is to give the processor time that he can determine the mode of operation in which the controller is to operate and that he can set the gains and constants correctly for either continuous or discontinuous operation. The manner in which this is done is described below in connection with the program.

Referring to FIG. 13, if the count in the down counter 224 is 14, a conversion pulse on line 78 is sent to the analog-to-digital converter to activate the converter so that the converter begins analog-to-digital conversion. When the 20 ° delay has ended, or when the down counter 224 reaches the predetermined count value 0, the INT flip-flop 250 again sends a second interrupt signal to the processor. Upon receipt of the second interrupt signal, the processor interrupt subroutine now performs the FINVAL firing angle calculations to develop the TIMTGO value. As can be seen from FIG. 13, the entire reading and calculation of the firing angle takes place between the firing of successive thyristors. Since thyristor firing takes place every 60 ° of the input sine curve cycle, the entire calculation for the firing angle for firing the next pair of thyristors is carried out in a 60 ° interval. The 20 ° delay selected represents the maximum value that gives time for the controller's calculations (i.e. time to calculate the ignition angle) and to produce a positive TIMTGO value when the phase lead rate is maximum.

The second current read by the processor is used to calculate the controller response. The advantages of performing the calculations in this way are:

1. The control time delay, as seen by the overall controller, is minimized, which maximizes the properties of the controller.

2. The second current reading always has a certain finite value in all practical operating rules of the regulator, so that the regulator can work during the discontinuous current operating mode. This results from the fact that the second current reading is carried out 20 ° after the first current reading.

3. As will be explained, a single down counter, such as the down counter 224 of FIG. 9, is required because the counting process is always started only after the previous pair of thyristors has fired.

13, when the calculations are complete, the processor loads the TIMTGO value into the down counter 224 of FIG. 9 and at that point this counter begins to count against the value 0. The program then branches directly to a READ-TACH counter subroutine RDTACH, in which the tachometer pulse counter 88 is read by the processor and a value of a back emf for forward feed (CEMF) is used for the calculation of the commanded motor terminal voltage (VT).

When the RDTACH subroutine ends, the program branches back to the interrupt subroutine, which subroutine calculates a rate of change of the power set value SPDESI. The program now enters a loop and waits until the firing counter reaches 0, as shown on the top line in Fig. 13, to this

5

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15

20th

25th

30th

35

40

45

50

55

60

65

632615

14

When the thyristor pair is triggered and an interrupt signal is again sent to the processor and the process just described is repeated.

Reference is now made to FIG. 14, which shows a high-level flowchart which shows the overall operation of the regulating and control system according to the invention in greater detail than just described in connection with FIG. 13.

When the system is first started, as shown in the upper left block of FIG. 14, the program provides an i pseudo interrupt to the system by loading a number 16 into the down counter 224 of FIG. 9. At this time, zero values are also loaded into the thyristor select register 268 of FIG. 11B. The down counter then begins counting against the value 0, and when the value 0 is reached, the INT flip-flop 250 of FIG. 9 generates an interrupt signal on line 210 to the processor. The purpose of having zeros entered in the thyristor selection register is to prevent any pair of thyristors from firing at that time. 20th

The processor now enters the interrupt subroutine upon receipt of the interrupt signal. The program enters a first read decision block, which determines whether this is the first or second current reading from the analog / digital converter 80 of FIG. 3. Assuming that this is the first current reading, the program goes through a yes branch into a block in which the first current is read by the analog / digital converter. The program also determines in this block whether the system is in continuous or discontinuous current operation, comparing the values 30 of the first current with a constant that is proportional to a given current. The program then continues and sets the aforementioned ignition angle for a 20 ° delay. The program continues and reads the system clock bits IDI B0 to ID1B7 on lines 90 of FIG. 5 and calculates the value of NEWTIM. After the calculation of NEWTIM has been completed, the program continues and calculates TIMTGO, whereby this variable includes a 20 ° delay at this time. The program then loops and continues to read the system clock 40 until NEWTIM equals the 5 least significant bits of the 32-by-32 counter 170 of FIG. 5, designated IDI B3 through ID1B7. If these two values are equal, the processor loads the TIMTGO value, which is proportional to the firing angle, into the down counter and 45 continues to set a flag for the second reading.

The program then continues to check for a new tachometer reading in the tachometer counter register. If a new read value is available, it is read out 50 and added to the tachometer read values which have already been accumulated in the memory (CACTI). The program then checks whether three consecutive readings or readings are accumulated. If this is not the case, the program does not branch and runs back into the main program until a further interrupt signal is received from the processor (that is, if TIMTGO is 0). At this point, the first read decision block is re-entered, and at this entry, since the flag for the second reading is set, the program exits through the no branch 60 of the last decision block and enters a block , in which the processor reads the second current from the analog / digital converter.

After the second stream has been read, the program now carries out controller calculations to calculate the sizes FINVAL and 65 TIMTGO. Upon completion of these calculations, the processor then writes the thyristor pair address to the thyristor select register 268 of FIG. 11B. At this point the processor loops again to continue reading the system clock until the values of NEWTIM and ID1B3 through ID1B7 are equal. If these values are the same, the processor is informed if TIMTGO is to be loaded into the down counter, which is happening at that time. The processor then continues to update the thyristor pair address in the aforementioned PH counter and then sets a flag for the first current reading, so that a first reading is made the next time the program is run. The program then returns and reads the tachometer again to determine if a reading is available and then checks to see if three consecutive tachometer reads have accumulated. If 3 read values have not yet been accumulated and a speed controller request flag flag (SPDFLG) is not set, the program continues through the loop just described and runs back through the first read decision block, out of the yes branch and continues with the current controller calculations continues, as was just described during the second readout. If three consecutive readings are available after the aforementioned check for a new tachometer reading, new values for engine speed (CACT), steady-state engine acceleration (TACSMD) and counter electromotive force (CEMF) are calculated. The cruise control flag (SPDFLG) is set to zero to cause a cruise control calculation to be performed. Upon completion of these calculations, a flag is set for a second current reading, indicating that the first reading has just been made, and the program branches back to the main program with an interrupt signal from INT firing logic flip-flop 250 of FIG. 9 as previously described. However, if no flag is set for the second reading, a yes branch is taken to a block to check the time for the speed controller calculation to be carried out, the size SPDFLG is increased by 1 and then checked for the value 2. When this test goes through, the cruise control calculation starts. If not, the main program is entered again, as before. This procedure ensures that controller and continuity calculations between firing the thyristors are not performed in the same interval. This was done to avoid overloading the computer. When the speed controller calculations are completed, the program runs back to the main program when the interruption signal from the ignition counter is pending.

On the broad background of the description of the system operation in connection with FIGS. 13 and 14, reference is now made to FIGS. 15 to 24, which show in the form of detailed flow diagrams the execution of the current regulator program for controlling and regulating the regulating and control system according to the invention. Reference is first made to Fig. 15, which is a flow chart depicting the main program of the invention. Not included in Figure 15 is a standard trigger routine that normally runs through each program to prepare all of the various registers and locations in memory for a program run. Since this type of triggering is known, it is not shown in FIG. 15, rather it is assumed that the program begins at an entry point that is designated BEGIN. When the system starts first, starting at the BEGIN entry point, the processor first reads the device 3, the tachometer pulse counter 88, as shown in FIGS. 4 and 7. The bits read by the computer are bits ID3B0 to ID3B7 on lines 22. These bits are determined by the 8-bit multiplexer 128 of FIG. 4 depending on a read address which is represented by bits IR5 to

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IR7, and a READ-P pulse on the trip-mentioned speed reference switch, which reads out a speed reference line that leads to multiplexer 128. Mark the value of the motor in revolutions per minute

The processor then checks in a decision block (bits ID6B3 through ID6B7 and ID7B0 through ID7B7) in a TACH COUNT = 0 to determine whether the engine is storing memory in the processor program 62 that is rotating. If the tacho count (ID3B0- s CHALF) is designated and the storage space for the rotary ID3B7) is not 0, the processor indicates that CEMF is not 0 is the setpoint.

and the motor turns, and the program takes a no- the program now continues, the sign of the place branch from this decision block and runs in the CHALF according to the setting of the FWD / REV switch to loop back to BEGIN until CEMF or Set TACH COUNT 0, whereby a "reader 0" signal is first. If TACH COUNT is 0, the program enters through a to system interface and bit ID0B5 from the one-yes branch into the next action block, in which direction 0 is read out. If ID0B5 indicates that the processor is reading device 0 (18 'of FIG. 4). If ID4B0 is the motor to run in the forward direction, the CHALF place is read by the processor at this point in order to not change the on / on, however if ID0B5 indicates that the direction of the switch is read and to determine whether the motor is on Motors should run in the reverse direction, then that has been switched. In addition, the processor sends a “read 15 binary complement (2s complement) taken from CHALF device-0” command to the processor / system interface, and consequently substituted for CHALF.

the RDVO signal on line 130 to the INT flip-flop. The program now continues to determine if the ON / 250 is being generated, thereby resetting this flip-flop. OFF switch is in the OFF position. If the INT flip-flop 250 is now in a state with the switch in the OFF position, the program exits by giving an interrupt signal at the right time during 20 yes branch and goes back to BEGIN, the operation of the System. which repeats the operations just described

The program now runs into a decision block. However, it is assumed that the ON / OFF switch

ON / OFF SWITCH ON. If, in this decision is not in the OFF position, the program comes out of the block, the ON / OFF switch, which was just read from the last decision block 0 by means of a No branch, is not in the switched-on state , takes 25 and returns to the START entry point, as shown in Fig. 15 the program takes a no branch back to the beginning of the. The program now runs through the program and runs in the program until the ON / loop from the START point down to the ON / OFF-OFF switch is switched on. It is now assumed that the switch OFF (OFF> decision block continues until a sub-ON / OFF switch is switched on, in which case the break signal from the data processor exits the INT flip-flop program through a yes branch and into one 30 250 is obtained in the ignition logic 9.

Action block occurs in which the processor writes a «As already in connection with the ignition operation of the logic

Device-1 'command along with data bits WDB0-WDB7, the INT flip-flop 250 is set to transmit to the processor / system interface of Fig. 4 to send the INT signal on line 210 to the processor, Generate the WDV1 signal on line 212 when the down counter reaches a count of 0. It is wanking to be sent to the firing logic of FIG. 9 and by 35 to indicate that the interrupt signal from the count 16 into the write data latch and firing logic is at all times during the execution of this last down counter 224 load in the manner previously described. called loop (that is, between the START-On-The purpose to jump the count 16 into the down counter 224 and the ON / OFF-SWITCH-OFF decision

is a pseudo interrupt to the process block) can occur. When the interruption occurs, sor to deliver so that when the 40 is executed, the processor jumps from the main program of FIG. 15 to a main program and all subsequent subroutines starting point INTPT of FIG. 16 to begin the start of the interrupt an entry from the main program. As can still be seen, it returns upon completion. the interrupt program when all calculations

At this point, the down counter that is completed starts back to the main program of FIG. 15, down counting, while the program immediately goes to 45 at the point at which the interrupt occurred. START entry point continues, see Fig. 15. It is now assumed that the processor is the sub

The processor sends a “Read 6” command to the process break signal on line 210 which causes the sor / system interface to read the speed reference program into the START INTPT of FIG. 16. The change switch to be carried out by bit ID6B0 on the first operation by the processor is to draw the current lines 66, see FIG. 4. The state 50 values of the various processor registers, in particular that of bit ID6B0, is now queried by the processor. in order to determine whether the speed change switch is in the on-state, as previously described in connection with FIG. 2. This represents a standard procedure for everyone located. The speed change switch is shown as being one of the user operating programs when a switch controlled by a subroutine or processor is formed on one console, the program is jumped to another so that these values are not shown, and forms part of the speed reference 55 can be saved again later if a reset switch 18 (input devices 6 and 7) that occurs from a return to the program from which the jump was made

Users can be operated when the user desires that has been.

To change speed reference input to the data processor, then the processor continues to run a "Read Setup-0" -

to change the speed of the motor. As long as this switch sends the command to the processor interface of FIG. 4, which is in the on state, the program continues and passes through 6o bit ID0B0 of the ON / OFF switch to read out and at the same time the yes branch of the decision block CHANGE SPEED SW Reset or clear interrupt flip-flop, ON off and returns to the START point in the program. the RDVO signal from decoder 126 of FIG. 4 to the ignition

It is now assumed that the speed change logic is sent in the manner previously described. The switch is not in the on state, and the program ON / OFF switch is now checked to determine whether it enters the action block by a no branch, is in the OFF or OFF state. If the switch is in the OFF state that the processor has commands to the processor / system interface state, which indicates that power is being sent by the device 6 and 7 to the motor 6 via lines 66, the program is read by the processor. At this moment, the previously a yes branch is made, and the previously saved registers are

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which is now restored to its original values, and the program returns to FIG. 15, in which the operations take place, as has already been described. However, it is assumed that the ON / OFF switch is not in the OFF state, and the program then enters a first CURRENT-REA-DING decision block (CURFLG = 0) by a No branch. A test is performed in the latter decision block to determine if this is the first current reading. The test is carried out here with a variable flag in the memory, which is called CURFLG for the first current reading flag. If D'CURFLG is 0, this indicates that this is the first current reading, if CURFLG is a binary 1, it indicates that it is the second current reading.

Assuming that currently CURFLG is 0, the program exits with a yes branch and enters an action block in which the processor sends a “Read Setup 5” command to the processor / system interface, which instructs that the analog / digital converter 80 reads the bits ID5B0 to ID7B7 through the 8-bit multiplexer into the processor on the input data lines IDO to ID7. The value specified by bits ID5B0 to ID5B7 is stored in a location in the memory designated CRNT, this location being a location for the measured motor current. The program then continues to a decision block in which a constant value CURTOL stored in the memory is compared with the absolute value of CRNT. The value of CURTOL is proportional to a value of 1 to 2 percent of the nominal motor current and is used to carry out a test regarding discontinuous current operation. If CURTOL is smaller than CRNT, the program exits with a yes branch and goes into discontinuous operation, while if CURTOL is larger than CRNT, continuous operation is present and the program exits with a no branch.

It is first assumed that the engine is operating in a discontinuous mode. If the Yes branch is used, the processor sets a mode flag MODFLG in the memory to a value of 1, which indicates that the system is now operating in discontinuous current mode. Four constants are stored in the memory, which are designated G1 and G2. There are two constants Gl and two constants G2, one pair being used when the system is operating in a batch mode and the other pair of sizes Gl and G2 is used when the system is operating in a continuous mode. These constants, which are used for continuous and discontinuous current operation, are gain constants chosen to provide the overall gain required by the motor drive loop when the motor is operating in one or the other mode. In discontinuous operation, for example, the program selects the correct Gl and G2, which have gains of 32 and 0, respectively. In the latter action block, negative and positive upper and lower limit values (VRLIMN and VRLIMP) are also read from the memory and brought into the interrupt subroutine to be used in the construction of upper and lower limit values for the motor voltage, which are calculated by the current controller.

Upon completion of these last operations, the program enters port B of FIG. 17. With reference to FIG. 17, it should be noted that the connection point A from FIG. 16 also runs into FIG. 17. As already described, there is an entry at connection point A in FIG. 17 if the system is operating in continuous mode. When entering junction A, the operations taking place in the first action block are the same as those in the last

Action block of the actions described in FIG. 16, except that MODFLG is set to 0 for continuous operation. The program also selects the correct Gl and G2 for continuous current operation (an example of these gain values is Gl = 15 and G2 = 11).

When entering connection point B in FIG. 17, the processor sets the firing angle in such a way that an interruption of 20 ° is effected after the firing of the last thyristor pair. This is achieved by setting the ignition angle FINVAL in the memory equal to FINVAL minus a number that is proportional to 40 °. If 40 ° is subtracted from the size FINVAL, an interruption is caused at the right time for the second current reading. If TIMTGO were calculated using the old FINVAL value, the thyristor pair would be triggered 60 ° later. By subtracting 40 ° from the FINVAL value, the down counter value is set in such a way that it generates an interruption 20 ° after the ignition of the last pair of thyristors. The program now continues in an action block, in which a memory location DESI, which identifies the desired current setpoint, is set equal to itself plus a calculated value SPDESI, which indicates a desired rate of change of the current setpoint

The program now runs into a connection point E of FIG. 20 and enters an action block in which the processor now sends a “read device 1” command to the processor interface in order to read the system clock bits ID1B0 to ID1B7 on the lines 190 , as shown in Figs. 4 and 5. In the next action block, the 60 ° interval, which is identified by bits IDI B0 to ID1B7, is stored in place KOCT (see Table 2), and the time within the interval, is identified by bits ID1B3 to ID1B7,

is stored in a memory location called TCLOCK.

The processor now continues to calculate the value of NEWTIM and sets this memory location in memory to TCLOCK plus 2, which represents the delay time previously described for calculation in deriving the TIMTGO equation. At this point, the long clock counter corrector CORR is also set to 0. The program now enters a NEWTIM> 30 decision block. If NEWTIM is greater than 30, the program exits with a yes branch and sets the CORR bit to the value 1. The program then runs in a further decision block NEWTIM> 31. If NEWTIM is 32 or greater, the program executes a yes branch in an action block at the top right of FIG. 20 in which NEWTIM is either set to the value 0 or 1 by setting NEWTIM = NEWTIM-32. If NEWTIM has the value 32, this quantity is set to the value zero, whereas NEWTIM is set to the value 1 if this quantity is 33 (that is, TCLOCK = 31 + 2 = 33).

Reference is now again made to the decision blocks NEWTIM> 30 and NEWTIM> 31 of FIG. 20. If one of these decisions is negative, the program exits by no branching the decision block in question and enters an action block in which the zero crossing number PHA in memory is used to calculate TIMTGO, the value of KOCT being an address for PH table (TABPH) is used in which PHA is set to TABPH (see Table 2). The processor now continues to calculate TIMTGO by making TIMTGO equal to FINVAL (the firing angle) minus TABTP (the offset correction of Table 2, addressed by the difference between PHA and PH) minus 8 x TCLOCK (the time interval just read) minus that Value is set by CORR. CORR is either 0 or 1 at this time, depending on whether NEWTIM was greater or less than 31. The processor kicks

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then into a decision block CURFLG = 0, in which a test is again carried out to determine whether this is the first current reading. If CURFLG is not equal to 0, which indicates that it is the second current reading, then an entry in FIG. 21 takes place at connection point F, whereby an action block is entered in which the processor sends the thyristor pair and bridge address to device 3 11B, in which a WDV3 command is sent over lines 270 and the thyristor pair and bridge address over lines 266 as write data bits WDBO through WDB7 from driver 138 of processor / system interface 64 sent fyird. The thyristor pair and bridge addresses come from an OCTF table in memory that contains 12 separate address entry points, 6 for the forward thyristor bridge and 6 for the back thyristor bridge. The locations in the OCTF table are addressed by the content of the PH counter, which specifies the thyristor pair to be fired and the directional flag DIRFLG, which is a flag flag in memory that indicates whether the forward or reverse bridge is to be fired.

It should be remembered that the firing of the thyristors actually takes place after performing the calculation of TIMTGO (i.e. after reading the second current), it is therefore necessary to change the thyristor pair and bridge address in order to get the correct thyristors ignite. If, on the other hand, it is a first current reading, it is not desirable to change the thyristor pair and bridge address, since no firing takes place at this time. If it is not the first current read value, an entry in FIG. 21 takes place at point G from FIG. 20, and the update of the thyristor pair and bridge address is bypassed.

The program now runs into a decision block TIMTGO <16. If TIMTGO is less than 16, the program exits by a yes branch and enters an action block in which the processor writes the number 16 for device 1, the down counter which a WDVl signal is generated by the processor / system interface together with the number 16 on the write data bus WDBO to WDB7, as previously explained. The reason for the TIMTGO> test is that there is a minimum limit on the value of TIMTGO to ensure

that there is always at least a 4 ° delay before the interrupt signal is generated to the data processor so that a conversion command is sent to the analog-to-digital converter 80 to cause a new conversion to be performed.

If TIMTGO is not less than 16 in FIG. 21, the program branches off by a No branch and enters an action block READ DEVICE 1, in which the processor reads the system clock bits IDI B0 to IDI B7 again. The program then enters a loop via a decision block ID1B3 to IDI B7 = NEWTIM, which leads back to action block READ DEVICE 1 by a No branch, and the program continues in this loop until the system cycle is equal to NEWTIM. If these two values are equal, it is time to load the down counter and the program takes a yes branch and enters an action block in which the processor now writes TIMTGO to the down counter 224 of FIG. 9.

As already described, the down counter starts to count TIMTGO down to 0 when the next 88 microsecond clock signal (see Figs. 9 and 10) occurs following the loading of the down counter. When the down counter reaches 0, the processor again generates an interrupt signal on line 210 of FIG. 9, thus generating another interrupt for the processor, as previously described. Immediately after the size TIMTGO has been transferred to the down counter, the processor goes from connection point H in FIG. 21 to connection point H in FIG. 22 and enters a decision block CURFLG = 0.

A test is then performed in this decision block to determine if this is the first current reading. If it is the first read value, the processor exits through a No branch and enters an action block in which the place CURFLG, the current read indicator is set to the value 1, to indicate that the second read value in the next pass through the It's the turn of the program. If it is the first read value, the program exits the decision block CURFLG = 0 by a yes branch and enters an action block in which the sequence counter or sequence counter PH is set equal to PH + 1, whereby the Thyristor pair address is increased so that the correct thyristor pair is fired the next time TIMTGO is calculated.

20 The processor now enters a decision block PH> 6. If PH is greater than 6, the program exits with a yes branch and enters an action block in which PH is now set to the value 1 25 in preparation for the ignition of the thyristor cell pair, which corresponds to PH address 1. If, on the other hand, PH is not greater than 6,

PH is not changed and the program exits with a No branch and enters an action block in which the CURFLG position is set to 0, in preparation for the first current reading on the next pass through the program. The interrupt subroutine now calls a subroutine called RDTACH, see FIG. 24.

Referring now to FIG. 24, the processor enters a START RDTACH entry point to the READ tachometer routine. In the subroutine RDTACH the processor first reads 35 the input device 1, the system clock, in which the first most significant bits (IDI B0-ID1B2) of this clock are read. It should be remembered that these bits define a 60 ° interval of the input voltage when the reading is done by the processor. The processor now enters a decision block PHOCT = ID1B0 to IDI B2. A test is performed in this decision block to determine if a phase zero crossing has occurred since the subroutine was last passed. This is accomplished by comparing the three most significant 45 bits of the 360 ° system clock (IDI B0-ID1B2) with the location PHOCT, which contains the reading or value of the 60 ° interval from the previous pass through the subroutine. A change in ID1B0 to ID1B2 means that a zero crossing has occurred and that a new value should be stored in PHOCT in order to update this storage space for subsequent tests. This is carried out in an action block in which an entry from a no branch of the decision block PHOCT is ID1B0 to ID1B2 occurs, in which PHOCT is set to ID1B0 to 55ID1B2. On the other hand, if there has been no change in the zero crossings, the program exits with a yes branch and returns from the point to Fig. 22 it had left to enter a decision block CURFLG = 1.

60 Referring back to FIG. 24, it is assumed that there was a change in the zero crossings, thereby changing the value from ID1B0 to ID1B2. As a result, the program exits decision block PHOCT = ID1B2, where PHOCT is set in the manner previously indicated, and enters an action block in which the processor now reads device 3, the tachometer pulse counter, in which it reads reads bits ID3B0 through ID3B7 and ID0B4 into the processor. Referring to Fig. 7

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Recall that bit ID0B4 was identified as the bit indicating the direction of the motor. In this action block, the value of the tachometer pulse counter is read into the processor and the sign of this value is set according to the state of ID0B4. As such, the value of the tachometer pulse counter is either a positive or negative number, indicating that the motor is running in either the forward or reverse direction. In the present system, the addressing of the input device 3 by the 8-bit multiplexer of FIG. 4 also has the effect that the bit ID0B4 is read by this multiplexer and is simultaneously input into the processor with the bits ID3B0 to ID3B7.

In FIG. 24, the processor now enters an action block in which the tachometer read value is added to the sum of the previously read values, in which ID3B0 to is ID3B7 is added to a location CACTI which is defined as a tachometer accumulator in the memory. It can therefore be seen that with each pass through the RDTACH subroutine, the tachometer values from the tachometer pulse counter 88 are accumulated 20 as a sum in the memory location CACTI. The processor then proceeds to the next action block in which a number of the read value counter CKNT in the memory is updated or increased by the value 1, with CKNT = CKNT + 1 being set. The purpose of the CKNT counter is to keep track of the number of reads accumulated in CACTI 25. This is indicated by a decision block CKNT = 3 in the upper right part of FIG. 24, which carries out a test to determine whether 3 read values have been accumulated. If CKNT is not equal to 3, the speed continuity calculations are not carried out, the program therefore exits with a No branch and returns to the interrupt subroutine that it left to enter decision block CURFLG = 1 in FIG. 22, as explained.

It is now assumed in FIG. 24 that three read values 35 are accumulated, in which case the program exits through a yes branch and enters a decision block in which an inconsistent engine speed is calculated. This is achieved by setting the TEMP location in the memory equal to the sum of the tachometer pulses accumulated over the last two passes. This is the average engine speed. The sum is realized by TEMP =

CACT is set, where CACT represents a memory location that stores the old sum of the tachometer speed readings with the memory location CACTI, which contains the sum of the new 45 tachometer readings. In this action block the memory location CACT is also set equal to CACTI so that it reflects or reflects the sum of the old read values. Furthermore, CACTI is set equal to the value 0, so that CACTI can be triggered in subsequent passes in order to accumulate the sum of the next read values. Furthermore, a speed indicator SPDFLG is brought to a binary 0. SPDFLG is used, as will be explained, to tell the processor whether speed controller calculations should be performed or whether the speed controller calculations should be omitted. If SPDFLG is zero, this indicator indicates to the program that the speed controller calculations should be omitted. The program then proceeds to the next action block of FIG. 24, in which a constant speed is calculated. This is achieved by setting a memory location TACSMD = location TEMP-TAC-SUM. In addition, a storage location TACSUM is set equal to TACSUM + TACSMD in this action block. The TACSUM location contains a value that is proportional to the steadier speed, and TACSMD is the speed rate that is a derivative of TACSUM. The program now continues to calculate the counter electromotive force CEMF, which is subsequently used in the calculation of the motor terminal voltage VT. CEMF is calculated by setting a location CEMF in the memory equal to KV multiplied by the memory location TEMP. KV is a constant that is stored in memory and has a value derived from the formula KV = CEMF (VOLTS) divided by revolutions per minute.

When the speed calculations are now connected, the interrupt subroutine processor in Fig. 22 returns and enters decision block CURFLG = 1. In this decision block, the program does not perform current speed controller calculations when CURFLG is 1, indicating that this is the second current reading. The program then takes a yes branch which enters position J at the top of FIG. 22, where the latches are restored as described, and the program returned to the main program at the point of interruption in FIG. 15. However, suppose that CURFLG is not 1, indicating that this is the first current reading, and the processor then enters port I of FIG. 23 where the speed indicator SPDFLG is set to SPDFLG + 1 . A test is now carried out in a decision block SPDFLG = 1 "in order to determine whether the speed indicator is set. If the speed indicator is set, speed controller calculations are carried out by the program, which exits by a yes branch of this decision block and enters an action block, to calculate a speed error.

The speed error is calculated in that a place ERRACT in the memory, which is the same as the memory location for storing the speed error, is equal to the content of the place CHALF, the speed setpoint, minus the content of the place CACT, the old sum of the speed read values or the speed before Steadiness, is set. When the program continues, the processor now triggers the calculation of the current setpoint, whereby the following is set: Storage space ERRACT = G3 x ERRACT -G4 x TACSMD. G3 and G4 are controller gains that are set according to the special drive motor to give the desired speed response. In this embodiment values G3 = 1 and G4 = 16 were used.

The processor now continues to calculate the current setpoint, setting a value TDESI = TDESI + ERRACT. The program now continues to a decision block TDESI> CURLMP at the top of Fig. 23. In the present drive system, a maximum limit for the motor current is set, so a test is performed to determine if the value of TDESI, the calculated motor current , are larger or smaller than the specified current limit values CURLMP and CURLMN. CURLMP is the positive current limit and CURLMN is the negative limit as indicated in a decision block TDESI> CURLMN of FIG. 23. If TDESI is greater than CURLMP, the program exits with a yes branch and enters an action block in which TDESI is set equal to the maximum current limit value CURLMP. If, on the other hand, CURLMP is not greater than TDESI, the program exits with a No branch and enters a decision block TDESI <CURLM. If this test is positive, the program exits with a yes branch in which TDESI is set to CURLMN. If, on the other hand, the test is negative, the program exits through a No branch and enters an action block in which the current change setpoint is now calculated. The current change setpoint is calculated by setting a location in memory called SPDESI (current setpoint change) equal to TDESI (the calculated current setpoint) minus DESI (current setpoint) and the difference

divided by 3. Divisor 3 is used to consider averaging the current change setpoint over 3 passes through the current controller calculation program for each speed controller calculation.

A current rate limit is also set for the current change setpoint SPDESI. This is caused by the program now entering a decision block SPDESI> RTLMP, in which a test is carried out to determine whether SPDESI is greater than RATLMP, which represents a positive change limit. If it is larger, the program enters an action block SPDESI = RATLMP by a yes branch, which defines the maximum positive change limit for SPDESI. On the other hand, if SPDESI is less than RATLAMP, the program exits with a No branch and enters a decision block SPDESI <RATLMN. In this decision block, if SPDESI is smaller than RATLMN, the program exits with a yes branch, whereby SPDESI = RATLMN is set and a minimal change limit is established. If SPDESI is not less than RATLMN, the program exits through a No branch and enters point J of FIG. 22, in which the previously saved processor registers are restored and the program at the point of interruption back to the main program returns as previously described.

Reference is further made to decision block SPDFLG = 1 in FIG. If SPDFLG is 1, this indicates that the speed controller calculations should be omitted so that the program exits from this block with a No branch and returns to location J of FIG. 22, as just described.

Referring now to FIG. 16, the first current read decision block CURFLG = 0 is performed in which a test is performed to determine whether the program takes the first or second current read value. If CURFLG is not zero, this indicates that the first current reading has just been taken, as previously explained, that the second current reading is to be taken, and that the current controller calculations have been performed. Under this condition, the processor now exits through a no branch at connection point C and enters in FIG. 18.

The first operation taking place in Fig. 18 is for the processor to send a "Read 5" command to read the analog-to-digital converter 80 and store bits ID5B0 through ID5B7 in the CRNT location, which space is used for Storage of the actual motor current or the actual value of the motor current is used. The processor now enters an action block and calculates the current error by setting the memory location IDIFF equal to the memory location DESI, the current setpoint, minus CRNT, the actual motor current. A test is carried out in a decision block IDIFF> + IDLIM to determine whether the current error is greater than a positive current error limit value, which is given by the constant + IDLIM. If IDIFF is greater than + IDLIM, the program branches off with a yes output and enters an action block in which an IDIFF is set to + IDLIM. If, on the other hand, IDIFF is not greater than + IDLIM, the program exits with a No branch and enters an IDIFF-IDLIM decision block. The same type of decision is made in this block to determine whether IDIFF is less than a negative or minimum current error limit. If this is the case, the program exits with a yes branch, in which IDIFF is set to -IDLIM. On the other hand, if IDIFF is not greater than —IDLIM, the program exits with a No branch and enters an action block in which the motor terminal voltage passes through

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the controller is calculated.

The motor terminal voltage is calculated by setting a memory location VR, which represents an average value in the calculation, equal to (Gl x IDIFF) to (G2 x IDIFFO). Gains G1 and G2 were defined above. Gain 1 (Gl) for discontinuous current operation is normally 2 to 3 times the value for continuous current operation, and gain 2 for discontinuous current operation is 0. The term IDIFFO represents a memory location in memory that corresponds to the old value from IDIFF stores. The program then proceeds to a decision block DIRFLG = 0. In this decision block, a test is made to determine whether the forward bridge should be fired, testing the state of the DIRFLG variable, which is a flag in memory that indicates which bridge should be fired. If DIRFLG is not zero, indicating that the reverse bridge thyristors are to be fired, the output is a no branch and VR is set to VRO-VR, where VRO comes from a location in memory that has the old value from VR stores. If DIRFLG is 0, which indicates that the thyristors of the forward bridge are to be fired, the program enters an action block with a yes branch in which VR is set to VRO + VR.

When the calculation of VR is completed, the program enters a decision block VR> VRLIMP. There are two constants (VRLIMP and VRLIMN) that are stored in memory and give positive and negative limits for the maximum and minimum of the calculated voltage. If VR is greater than VRLIMP, an exit from this decision block takes place by a yes branch to an action block in which VR is set to VRLIMP. On the other hand, if VR is not larger than VRLIMP,

a no branch is taken and a decision block VR <VRLIMN is entered. In this block, a yes branch is taken, in which VR is set to VRLIMN, provided that VR is less than VRLIMN. If this is not the case, a No branch is taken and VRO, the space for storing the old value of VR, is updated by setting VRO = VR.

The program now enters position D, leaving FIG. 18 and entering position D of FIG. 19. Upon entering FIG. 19, the processor enters a decision block MODFLG = 0, in which a test is performed to determine whether the system is operating in continuous or discontinuous current mode. If MODFLG is not 0, this indicates that the system is operating continuously. The processor then exits a no branch and enters a decision block DIRFLG = 0. In the flowchart of Fig. 19, the decision is made as to whether it is appropriate to reverse the direction of the motor. The criterion for reversing the direction of the motor is that the system must operate in discontinuous current mode and the sign of the current setpoint (DESI) must be opposite to the direction indicator (DIRFLG). This determination of the current reversal is explained as follows. If the decision test MODFLG = 0 is positive, the processor exits with a yes branch and thus indicates discontinuous operation in a sign of the decision block DESI OPP DIRFLG. In the latter decision block, a determination is made as to whether DESI is opposite the DIRFLG size. If DESI is not opposite, a No branch is taken and the program enters decision block DIRFLG = 0, as already described. However, if DESI is opposite the DIRFLG size, the program takes

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20th

a yes branch and enters an action block in which the direction indicator DIRFLG is reversed from the current state. As shown in this action block, when DIRFLG is set to 1, it indicates that the current flows in the reverse bridge and 5 does not flow in the forward bridge. If DIRFLG is set to 0, the forward bridge is fired. The program now continues in decision block DIRFLG = 0 in order to determine the relative polarity of the variable CEMF and the voltage from the bridge. If the reverse io bridge is to be fired, the no branch is taken from this decision block and an entry is made into an action block in which the desired terminal voltage VT is calculated by subtracting VT = CEMF (the back emf) VR (the motor voltage because the polarities are opposite) is set. If the forward bridge is to be fired, as indicated by DIRFLG = 0, then the yes branch jumps into an action block in which the desired motor terminal voltage VT is calculated by setting VT = CEMF + VR 20 to the to provide correct polarity.

In the present system, positive and negative limit values are imposed on the motor terminal voltage, so the tests immediately following the calculation of VT must determine whether VT is equal to or less than the positive and negative 25 limit values. The content of the first decision block after the calculation of VT is VT> VTLIMP. If VT is above the positive limit, a yes branch is placed in an action block in which VT is set equal to the maximum positive limit VTLIMP. If, on the other hand, VT is less than VTLIMP, a No branch is taken and a similar test is carried out for VT <VTLIMN. If VT is less than the minimum limit, a yes branch is taken and VT is set to VTLIMN. If this is not the case, a no branch is taken from the decision block VT <VTLIMN and a jump is made into an action block of FIG. 19, in which the ignition angle FINVAL for generating the desired VT is taken from the value table which is based on the previously specified relationship 40

FINVAL = 245.8 COS-1 (3VT / 7tVLN)

is calculated as indicated above. It should be remembered

that these values of the size FINVAL are described above and shown in Table 1. This type of entry into a table is known and represents a straightforward way of addressing the table with an address which is indicated by the value of VT, and the value of the addressed space is used as the ignition angle FINVAL. 50

The program now leaves FIG. 19 at connection point E and enters connection point E of FIG. 20, in which the system clock is read out by the processor in a manner already described. The program does not continue its execution in FIG. 20 and finally returns to the point of interruption of the main program in the manner already described.

Having described the invention in detail, it can be appreciated that the overall structure and method of the present system includes a main program that continuously loops to read the speed reference switches and motor direction switches and calculate the speed setpoint for the motor. The interrupt program receives the speed setpoint data from the main program and reads the motor speed, the armature current and the time measured by the 360 ° system cycle. The interrupt program also calculates the desired firing angle of the thyristors and controls the processor to send this data, the value of which is proportional to the firing angle, to a counter in the system and an address word to a thyristor selection and direction of rotation logic in order to generate the control pulse generators for the direct digitally trigger the thyristors selected by the address data to regulate and control a reversible three-phase motor drive system. The program is synchronized with thyristor firing by generating an interrupt on each thyristor firing cycle to start the controller calculations to load the counter at the correct time to control the firing time for a next thyristor to be fired.

The system processor reads the armature current twice per 60 electrical degrees. A first armature current reading is carried out at a predetermined time (for example 4 degrees) before the next thyristor is to be fired. This first current reading or current reading is used to determine the type of current regulator operation (continuous or discontinuous). A second current reading or current reading is carried out and the controller calculations are started approximately 20 ° after the previous ignition of a thyristor. The second current reading is used by the current regulator program as current feedback to control the overall current regulator.

A regulating and control system for regulating a load, for example a DC motor, has been described, which takes advantage of a processor, for example a microcomputer, and far exceeds the possibilities of known analog regulating and control systems, with only limited additional expenditure being required .

G

25 sheets of drawings

Claims (4)

632 615 2 Rectifier, as well as with the rectifier 1. Method for controlling the speed of a direct current cooperating selection devices (84) which receive the addresses determined by the motors with a control and regulating device (FIG. 3), the processor (64) and the one for calculating the ignition angle of the Select ignition pulse for igniting rectifier (94), and devices at least one controllable angle connected between an alternating current source (106) 5 (72) for receiving the ignition selected by the processor and the direct current motor (12) by the calculation for the external Transmission rectifier (94) contains the provided data processor (64), fixed point in time, each selection device having a count, characterized in that the processor contains parameters 1er (124, 224) for counting the clock signals and storing them in proportion to the target engine speed of a predetermined counter reading, an ignition pulse and the target ignition angles are that the processor has a pro i o for the selected rectifier and an interrupt program request signal that the processor generates as a signal for the processor. In response to this signal, one reads the actual engine speed and a value proportional to the motor current, and calculates a value determining the ignition angle, which of the Differences between the target engine speed and the actual engine speed and between the last read and the previous read, proportional to the motor current. The invention relates to a method for controlling a value and the previously calculated, the ignition angle DC motor with a control and regulating device, determining value is dependent that the processor further selects one of the stored controllable direct ignition angles connected to the direct current motor in the one for calculating the ignition angle of the ignition pulse as a function of the program request signal on the 20 for at least one between an alternating current source and the basis of the calculated value and contains the data processor provided to the selected ignition inverter, the corresponding point in time generates an ignition pulse for an engine control system of the type described here, generates rectifiers and, for the repeated calculations, often power amplifiers with control rectifiers that change the value determining the firing angle and the generation of electrical energy flow between an alternating current source of the firing pulse, the firing pulse as a program request and a drive motor. Control or control DC signal is used. judges are known and they consist of a family of 2. The method according to claim 1, characterized in that, with respect to the electrical energy flow, that for generating the ignition pulse represent a relatively high impedance to the selected one until they are fed into a counter by an ignition angle corresponding number 30 signal biased in the forward direction which counts, the counter content is applied at a predetermined speed - a control electrode. Counted during the conductive speed and when the stored number of states is reached, the control rectifiers normally have an ignition pulse generated. very low impedance to current flow and conduct 3. The method according to claim 1 in a device with normally the current until it in reverse rectifier-several rectifiers, characterized in that the device 35 are biased and / or the current level through the processor when feeding the program request signal rectifier below a minimum Hold level is reduced, one derived from the AC power source and a time required to keep these rectifiers in a conductive state within the period of the AC power condition. The family of the discussed control rectifying information signal reads out, as well as the one generally includes semiconductor components, such as calculated value, stored ignition angle and 40 thyristors and other components, such as ignites, for example, the trons and thyrotrons to be ignited designated by the information signal . Rectifier searches and to determine the next one to ignite. In the systems explained here, the amount of power supplied to a terminating rectifier is the value of the information system load read or to a DC motor. signals changes by a set amount. power regulated by the duration of the conductive state 4. Control and regulating device for executing the process of the 45 controllable or controllable rectifier is changed. The rens according to claim 1, characterized by means of the duration of the conductive state of the controllable rectifier (10) for generating a basic clock signal and by clocking a function of the point in time within the alternating current course directions (60) which is connected to the alternating current source (106). connected course in which the rectifiers are in the conductive state and respond to the basic clock signal to be brought with. This point is referred to as the ignition angle-AC source synchronized information signals to 50 net. Generate, which define a first characteristic, the proportional- In the past, systems for regulating the nal to the period duration of the alternating current derived from the determined zero crossings of the alternating-state of the controllable rectifiers of alternating current were implemented using analog regulating devices. and a second characteristic value that illuminates a period of time in order to carry out the required control functions, the period was defined, with the zero point of this time being 55 with the analog signals converted into digital values with the zero crossing of the AC period in order to ignite the rectifiers. With this type of coincides, means (80) for generating a first, systems operate the ignition circuits in dependence on a parameter proportional to the motor current, means input signal indicating the power to an ignition pulse (18) to generate a second, the target engine speed pro at the appropriate ignition angle. Generally spoken proportional parameters, devices (90) for generating 60 chen, the ignition angle is directly proportional to the input a third parameter signal proportional to the actual engine speed. Analog systems of the known type generally work in ters, a data processor (64) which, when a program appears, depends on an input signal, the size of which indicates the parameters and information-desired ignition angles to the program request signal. selectively reads signals and from the amount of them. In recent years, with the development of the digitally determined target motor voltage, the interest of the engineers in the technology and hardware has been sought. The second characteristic value has grown from digital circuits in such control systems to use time for the external transmission of the ignition angle. The use of digital technology in such calculations and from the first characteristic value the address of the control system is particularly advantageous where the system requires a level of accuracy, reliability or drift-free operation that can only be achieved with digital circuit technology. It is therefore quite common to replace elements of an analog system with functionally equivalent digital circuits. Such a known digital regulating and control system for regulating the line status of controllable rectifiers is disclosed in US Pat. No. 3,601,674. This patent discloses a digital control system to control the flow of power through controllable rectifiers from a multi-phase AC source to a load. This system contains an ignition circuit for each phase, each ignition circuit containing a reversible counter and a digital comparator. A phase sensing logic is provided which checks the three phases of the AC source in order to synchronously trigger a control interval for a suitable rectifier by presetting a predetermined positive or negative digital number in the reversible counter which is assigned to the relevant phase. The reversible counter then counts down during the control interval if the preset number is positive, it counts up if the preset number is negative. During the counting process, a digital speed error signal obtained from a previous comparison of a digital command with a digital feedback signal and indicating the motor speed is continuously compared by the digital comparator with the content of the reversible counter. If the error exceeds the content of the reversible counter, an ignition pulse is generated which is fed to a positive or negative polarized rectifier and ignites the correspondingly polarized rectifier according to the positive or negative number. Another known digital design system has been described in two publications, the first being by R.D. Jackson and R.D. Weatherby comes from and bears the title "Direct Digital Control of Thyristor Converters" in "IFAC Symposium on Control and Power Electronics and Electrical Drives", October 1974, held in Düsseldorf, Germany, Vorabdruck, Volume I, pages 431-441, and being the second publication by F. Fallside and RD Hackson comes from and bears the title "Direct Digital Control of Amplifiers" in Proceedings of the Institute of Electrical Engineers, with the title "Control and Science", Volume 116, No. 5, pp. 873-878, May 1969. In the publications mentioned, the authors describe an investigation of a laboratory system of the direct digital control type in order to show the feasibility of the direct digital control of the controllable amplifiers, such as thyristors. In this system, a programmed digital computer is used to regulate the ignition of the rectifier by means of a connection device (interface device) in order to regulate a resistive capacitive load by generating ignition pulses which are generated by the computer. The digital computer calculates the ignition angle, which defines a point in time in order to ignite a special rectifier. The system is synchronized with the zero crossings of the AC source phase voltages, which phase crossings generate command signals to a sample and hold circuit of an analog / digital converter that measures the output voltage of the system load. At the end of the analog / digital conversion, a pulse is generated by the converter as a program request signal for the computer. This pulse starts the ignition angle calculation. Following the triggering of this signal, the computer reads out the analog / digital converter a certain time after the time of the phase zero crossing. The computer then calculates the ignition angle or ignition timing for the rectifier, using a “given ignition law” designated by the authors. With this calculation 632615 a control signal or control value is developed which is continuously compared with a linear look-up table which contains values defining the ignition law until there is a match between the control signal and the content of the table. When a comparison value is reached, an ignition pulse is generated in which the address of the rectifier to be ignited is set and an ignition signal is supplied to the rectifier. While the authors demonstrated the feasibility of direct digital control of controllable rectifiers, they also identified various practical difficulties that arose in creating such a system. This was evident in the most striking set-up within these experiments, the use of look-up tables, which require significant computation time and severely limit the amount of additional computation that can be done by the computer when operating a real-time system of this type. It must also be noted that direct digital traction control systems must sample the load output voltage at a given time related to a determined phase interval of the AC source, that such systems subsequently perform the required ignition angle calculation and select a rectifier within the determined interval early enough must fire within the specific interval to accurately and fully control the retard of the firing angle to obtain maximum power transfer to the load. The systems mentioned did not work as an overall control system for regulating the motor speed of a reversible drive motor with variable speed. In analog systems, the manner in which the speed of a DC motor operating in either continuous or non-continuous current mode is controlled, as well as the manner in which the motor reverses direction, is well known. It is also known that a criterion for reversing the direction of a DC motor is that the motor current must be zero at the time of the reversal. In order to perform this reversal, analog systems must first determine if the current is zero and then wait a given safety interval before the direction of rotation of the motor can be reversed. It is also known in analog motor drive systems that such systems require two feedback loops in the system, a feedback loop regulates the motor when it is in a continuous current mode and a feedback loop regulates the motor when the motor is operating in a discontinuous current mode. These two circles produce different gains depending on the operating mode of the system. This method of operation in analog control systems has to some extent been found to be not entirely satisfactory in DC motor drive systems, particularly when it is desired to achieve a very high level of motor speed consistency under very light load conditions. It is therefore desirable to provide a drive and control system for the speed of a DC motor that improves the overall operation of the system by providing a controller that measures the system parameters and accurately calculates the motor speed that determines the operating mode of the system and which detects the direction of rotation of the motor and changes in the direction of rotation of the motor immediately and without delay, if desired.