CH629347A5 - Method and device for converting a binary input data stream into an output data stream and for the later reconversion of the output data stream - Google Patents

Description

The invention therefore provides in methods of the type mentioned at the outset, which is characterized in that if ss a signal change in one data cell from a signal change in the adjacent data cell would not have the minimum distance, these two signal changes are replaced by a single signal change, at least has the minimum distance from each of the adjacent signal changes.

A device according to the invention for carrying out the method is characterized in that, for converting the input data stream into an output data stream, look-back and forward-look circuits combine circuits in a coding circuit, which combine circuits do the coding circuit with the content of at least some of the bit positions in the preceding and subsequent

To supply data cells, it is provided which combining circuits each replace two signal changes which would appear in the output signal with less than the minimum distance by a single signal change which is at least the minimum distance from the adjacent signal changes.

An embodiment of the invention further relates to a device which is characterized in that means are provided for converting the output data stream back into a data stream corresponding to the input data stream, in order to cyclically decode the coded data lines, these means having a read signal shift register for the coded data cells serially received and in each decoding cycle to include an encoded data cell and one or more signal changes from the previous data cell, gates that process the contents of the read signal shift register in parallel to decode each encoded data cell and separate previously merged signals and the decoded data cells to the read information -Supply shift register, and means for delivering the information contained in the read information shift register in series.

The invention is explained in detail below on the basis of preferred embodiments with reference to the accompanying drawings. Show it:

Fig. 1 encoded signal waveforms, which represent various hitherto common codes, and the code with reference to the usual binary data which occur with a predetermined frequency of 1 / T;

FIG. 2 shows a table in which special features of the known code shown in FIG. 1 are shown for a data bit frequency of 1 / T;

3 shows a table in which the special features of the code for a data bit frequency of 1 / T are shown;

Fig. 4 is an illustration of a data cell, showing the selected signal transition points used in the code;

5 shows a binary data pattern and the associated coded signal waveform;

6 shows a circuit for coding data, partly in the form of a block diagram and partly in logical form;

FIG. 7 shows a function table that can be used to understand the coding method; FIG.

Fig. 8 is a function table for the circuit of Fig. 6;

9 shows a circuit for decoding data, partly in the form of a block diagram and partly in logical form;

Fig. 10 is a function table for the circuit of Fig. 9;

Fig. 1 la and 1 lb timing diagrams to explain the operation of the circuits in Fig. 6 and 9;

Fig. 12 shows a recording and recovery arrangement with the circuits of Figs. 6 and 9 for recording and recovering encoded binary data; and

13 is a table in which a different arrangement of code signal locations according to the coding method is included, each data word corresponding to two successive data cells with three signal locations per cell.

A binary data pattern used to describe the operation and structure of the invention with respect to the known codes is shown in Fig. 1, with each data bit represented by either a one or zero if it occurs in an interval T with uniform distance between the bits is reproduced, as is usually generated by a clock generator. The interval T represents a time unit or a corresponding length unit on a storage medium. The various known codes shown in FIG. 1, namely the codes NRZI, FM, Gabor and MFM, are each for coding the

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Binary data used. As can be seen, the various codes are shown on a common scale, which corresponds to the specified binary data frequency. In the case of the NRZI code, the binary data is encoded so that a signal change or a transition in the encoded waveform occurs in the middle of an interval T to represent a one-bit while there are no signal changes for the zero bits.

2 shows various special features of the known code shown in FIG. 1. The NRZI code has the advantage of a relatively wide recovery window (± 0.5 T), which is obtained due to the fact that the next, adjacent signal transitions are arranged at a distance which is equal to T. In other words, a transition controlling pulse or a so-called recovery window located in the middle of each data bit interval and having a width of approximately ± 0.5 T only senses a transition that occurs in the associated Inverali. However, the NRZI code also has serious disadvantages, since self-clocking is not possible and, moreover, it has a very wide bandwidth, as shown by the ratio Smax to Smi ", where Smin and Smax represent the minimum and maximum distances between coded signal transitions . This is because there is no signal change in the event of a long sequence of zero bits. The distance Sma! T does not have to be too large in order to obtain self-clocking since, as stated above, the phase-locked oscillator of the recovery system is controlled by the reproduced signal transitions. If the distance Smax exceeds a predetermined interval, the oscillator runs without a clock (i.e. without synchronization), and consequently the recovery window created by the oscillator cannot track the reproduced signal transitions as it does for recovery of binary data is required.

With the FM code, there is a signal change or transition in the encoded waveform at each boundary between adjacent data bit intervals T and in the middle of each interval at which a one bit is present. Transitions in the middle of the T intervals are data transitions, while the transitions that occur at the border areas are clock transitions that are precisely introduced to ensure self-clocking, and since the maximum distance between the signal changes is T, one becomes Self-clocking easily achieved. In addition, the system bandwidth compared to the NRZI code is significantly smaller, as indicated by the ratio Smax and Smin. The clock frequency 2 / T indicates that a full period of the recovery window signal occurs in every interval T, with half a period being required to place it in the middle of the T interval to distinguish between data and clock signal transitions; consequently, the recovery window for the FM code is reduced to half the window for the NRZI code. The reduction in Smjn has an unfavorable influence, as shown in FIG. 2, since the number of data bits per Smid. H. is encoded per transition, reduced to half of what can be obtained with the NRZI code.

The Gabor code, which is described in US Pat. No. 3,374,475 and invented by A. Gabor, is characterized by coded signal transitions that occur either at the edges of the T interval or at one third and two thirds between the edges . The Gabor code creates certain improvements over the FM code, since the number of data bits which are coded per Smin is larger and the recovery window is enlarged due to a larger minimum distance between the signal transitions, which means that the binary data packing density with regard to the FM

Code is enlarged, but not as much as is possible with the NRZI code.

The MFM code is characterized by coded signals either in the middle or at the edges of the data bit interval and consequently has the same clock frequency as the FM code, since a recovery window is located both in the middle of each data bit interval T and on the edges of the data bit intervals must be generated in order to feel all coded signals for a self-clocking and to distinguish between one and zero bits, which are represented in the coded signal by transitions that occur at unique locations, for example ones in the middle of the T- Intervals and zeros on their edges. With respect to the Gabor code, the MFM code has the advantage of larger or amplified data bits which are coded per Smin, this being the same as the NRZI code, as shown in FIG. 2, while a corresponding recovery window and Smax are retained to have a way of self-clocking. Because of the increased minimum distance between the encoded signals, the binary data packing density obtainable with the MFM code is better than that which can be obtained with the FM or Gabor codes, and is actually essentially double that of the FM code. In other words, if T / 2 is the acceptable minimum distance between signal transitions for an allowable bit shift with respect to the width of the recovery window, then the binary data for MFM coding can be represented at a frequency that is approximately twice the frequency for the FM code is permissible, that is, the interval T of the binary data can be reduced to T / 2 in the case of MFM coding. As a result, the MFM code has many advantageous properties for binary data encoding.

The method according to the invention and the device for carrying it out are briefly described below, but for the time being the essential, eye-catching advantages of the invention are described with reference to FIGS. 1 to 3. According to the invention, a new code, which is referred to as 3 PM (three-digit modulation or three-phase modulation) code, is created which, compared to the MFM code, in particular with regard to the minimum distance of the signal transitions of the coded waveform and the number of Data bits encoded per minimum distance between the transitions is improved, as can be seen from a comparison of FIG. 3 and FIG. 2. Particularly in view of the increased minimum distance between signal transitions, it can be seen that the binary data packing density is increased to 50% with respect to the MFM code. As a result, if T / 2 is the minimum acceptable distance between adjacent transitions, the 3 PM code enables compression of the binary data by a factor of three with respect to FM coding and 50 percent with respect to MFM coding.

It can also be seen from Fig. 3 that the recovery window for the 3 PM code is obtained equal to that for the MFM code, and although Smax as well as the ratio Smax to Smin are larger, the parameters obtained are nevertheless for circuits which are current are sufficient for self-recovery or self-recovery. Since transitions occur both in the middle and at the edges of the intervals T in the 3 PM code, the clock frequency is 2 / T, which corresponds to the clock frequency for the FM and MFM codes.

The above-mentioned features of the 3 PM code are achieved in that the binary data are divided into binary data words and each data word is encoded in such a way that it is represented by a signal transition or by a combination of signal transitions that are at least at a prescribed minimum distance are arranged and in a data cell with a length of 5

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come, which is equal to the sum of the number of intervals T, which correspond to the number of bits in each data word. The generation of the code is also based on determining when signal transitions in a data cell are arranged at a distance from one another which is smaller than the prescribed minimum distance from signal transitions to an adjacent data cell and that in such a case, i.e. that this occurs, it is provided that such signal transitions arranged at too short a distance are replaced by a smaller number of transitions.

The preferred coding circuit, which is shown in Fig. 6 and described somewhat later, divides the binary data into groups of three data words, each data word having three data bits, each data word again being any of eight possible data words, i.e. each data word corresponds to one of eight possible combinations of data bits in a word. Each data word in turn corresponds to either a single code signal or a combination of code signals which relate to a signal transition point in a data cell of the storage medium or to a combination of signal transition points in the data cell which are arranged at least a prescribed, minimum distance Smin = 3T / 2 from one another are, as shown in Fig. 1. 4 shows the position of the signal transition points PI to P6, which are arranged at a constant distance T from one another in a data cell which has a length equal to 3T in the case of three data bits per data word, the positions P6 with respect to the edges of the Data cell are aligned.

The third and fifth columns in FIG. 7, which are overwritten with binary data word or transition point in a data cell, reflect the assignment of the eight possible data words with respect to the six data cell transition points. Other assignments of the data words and transition points can be used if necessary, as long as the coding criteria of the invention in the manner as will now be described are satisfied. In the assignments shown, a single transition point is used for binary data words 000,001,010,100 and 101, while two signal transition points are used for binary data words 011,110 and 111. It can also be seen that in the cases in which two signal transitions are used, the transitions are arranged at a distance of at least three places, which, as is to be understood from the preceding explanations, is equal to 3T / 2, the prescribed minimum distance, are. It can be seen from this that where transitions occur at point P5 in a data cell and at a point PI in an immediately following data cell, the distance between the transitions is only an interval T and consequently the prescribed minimum distance is not maintained. Thus, where such transitions are required, it is contemplated that they will not actually be created, but instead be replaced with a single transition at location P6 midway between the prohibited transitions.

In particular in a case where the present binary data word to be coded corresponds to a signal transition which is to be generated at position P5 in the present data cell and which is followed by a binary data word which is associated with a signal transition which is located at position PI in the the following data cell is to be generated, the signal transition at location P5 in the present data location is prevented and replaced by a signal transition at location P6, which is defined at the rear edge of the present data cell. If, in addition, the present binary data word to be coded corresponds to a signal transition which is to be generated at position PI in the present data cell and which is preceded by a binary data word which is associated with a signal transition which is to be created at position P5 in the previous data cell (and which was replaced by a transition at position P6 under the assumed conditions),

then the transition at point PI in the present 5 data cell is prevented. This ensures that coding signals do not occur at distances that are less than three digits apart. In other words, it is a principle in the coding method according to the invention that a transition that is to be generated at the point P5 in a data cell that is present is followed by a signal transition that occurs at the point PI in the immediately following data cell is merged into a single signal transition that is generated at location P6, which is defined at the edge between the present and the immediately following data cell. This is achieved if each binary data word is encoded one after the other by simultaneously looking at the immediately preceding and the following data words, as will be described in detail with reference to FIGS. 6 to 8. First, a binary data pattern and the corresponding coded signal, which are created in accordance with the coding method according to the invention, will now be described with reference to FIG. 5.

As shown in FIG. 5, the first binary data word 001 generates a signal change or a transition at the position P4 in the first data cell ZI. The binary data word 111 of the second binary data group generates signal transitions at the points PI and P4 in the data cell Z2, the data transition taking place at the point PI in the data cell Z2, since a data transition at the point P5 in the previous data cell ZI is not occurs. The third binary data word 010 creates a signal transition at the point P2 in the data cell Z3. The fourth binary data word 110 corresponds to signal transitions that are to be generated at points PI and P5 in the data cell Z4, but only the signal transition at point 35 PI is actually generated. The signal transition at location P5 in data cell Z4 is prevented since the following binary data word 101 is assigned to a signal transition at location PI in cell Z5. In this way, in accordance with the coding rule according to the invention, a signal transition is not created at a point P5 in the data cell Z4, but instead a signal transition at the position P6 which corresponds to the edge between the data cells Z4 and Z5 at point P5 in data cell Z4 has been replaced by a signal transition at point P6, no signal transition is created at point PI in data cell Z5 which corresponds to binary data word 101.

6 and IIa, a signal which corresponds to the binary data to be encoded is applied to the data input terminal 14 of a shift register 15 for data writing, which thus has a sufficient capacity to store three binary data words, each having three data bits and corresponding to them current location in the register may be referred to as the present, previous, or subsequent data words. For example, the binary data signal may have a series of pulses obtained by representing each one-bit by one pulse and each zero bit by the absence of a pulse in certain discrete time increments. A series of bit clock pulses which occur at the data frequency are applied to the bit 60 clock terminal 16 to shift the binary data into a register stage corresponding to each such pulse. At this point it should be pointed out that a state without data in the register is equivalent to a lack of pulses in the corresponding register stages or with e? in other words, equivalent to a sequence of zero bits. It can be seen from FIG. 7 that the binary data word 000 corresponds to a signal transition at location P5, which is actually transmitted to location P6, as described above

is. As a result, it is assumed that the encoding begins when the first binary data word to be encoded is aligned with a binary octal encoder 17. This state is obtained when the sixth bit clock pulse occurs after the application of binary data to the input terminal 14, namely the bit clock pulse 18a, at which time the three stages of the register 15 on the right are not loaded with data. In particular, the sequence of processes that begins after the fifth bit clock pulse 18b, that is to say after the first five data bits have been loaded into the register 15, is now considered. First, the recording signal applied to the recording terminal 19 of the write signal shift register 20 changes from a high to a low level, putting the register 20 in readiness so that signals can be loaded into its corresponding stages SI to S6, which correspond to the positions PI to P6 of a data cell. However, actual loading of signals into the stages of the register 20 does not occur until the point at which the leading edge of the word clock pulse 21a applied to the word clock terminal 22 changes from a high to a low level. In any event, the signals entered in stages of register 20 are only temporary at this moment and are not stabilized for writing until the sixth bit clock pulse 18a occurs, at which point the sixth bit of data is loaded into register 15 and the first data group to be encoded is aligned with respect to the binary octal encoder 17. In this way, if the data word 001 in FIG. 5 is the present binary data word to be encoded, for example, a signal is supplied from the terminal B1 of the encoder 17 as shown in FIG. 7 and through an OR gate 23 transferred to stage S4 of register 20. The signal at the output of the OR gate

23 is the code signal for the present data word 001.

At the same time, the three zero bits run in the previous ones

Levels of register 15 related to the binary octal encoder

24 are aligned via a logic circuit 25, which has an OR gate, an inverter 27 and an AND gate 28, in order to prevent a signal from being stored in stage S1 of the register 20 in the event that a signal is present at the terminal B5, B6 or B7 of the encoder 17 is to be provided, but this is in reality not the case for the present binary data word 001. At the same time, the following data word, which at this moment is 111 and which is defined at the following three stages of the register 15, which are aligned with respect to the binary octal encoder 29, runs via a logic circuit 30 which has an OR gate 31, one Inverter 32 and an AND gate 33 and 34 to prevent storage of a signal of stage S5 and to cause storage of a signal of stage S6 in the event that a signal at terminal B0, B3 or B6 of the encoder 17th is provided, but this is not the case again for the present binary data word 001. As a result, the result is

that data word 001, which is currently to be encoded, generates a signal in stage S4 of register 20 but not in any of the other stages of register 20. At the trailing edge of the word clock pulse 21a, a signal is also blocked, which is to be entered in stages SI to S6 of register 20.

During the time between the trailing edge of the word clock pulse 21a and the trailing edge of the next word clock pulse 21b, a total of six digit clock pulses 35a to 35f occur at a frequency which is twice the frequency of the bit clock pulses and slightly ahead in time with respect to the bit clock pulses. When each position clock pulse is applied to a position clock terminal 36 of register 20, the contents of the corresponding register levels are shifted by one level. As a result, when the position clock pulse 35a occurs, the signal in the register stage S1 becomes an input trigger pulse

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applied to a bistable flip-flop 37, the signal in the register stage S1 is shifted to stage S1 and so on, the signal in stage S6 being shifted to stage S5.

For the assumed binary data word 001, only stage S4 contains a signal with a high level and, as a result, flip-flop 37 does not switch to a state until the signal originally stored in stage S4 is applied to the flip-flop input. This switching of the flip-flop 37 can be used to generate a magnetic flux transition in a magnetic storage medium, which is obvious to those skilled in the art and is subsequently explained with reference to FIG. 12. When the leading edge of the digit clock pulse 35f occurs, the signal originally stored in stage S6 is applied to the input of flip-flop 37, and shortly thereafter the bit clock pulse 18e is applied, with the result that new code signals enter stages S1 to S6 of register 20 may be applied in view of the fact that the word clock signal is low again at this time, as indicated by pulse 21b. Since position clock pulses 35a to 35f have been applied during this time, bit clock pulses 18c to 18e are also present, as a result of which the signals in register 15 are shifted by three places, with the result that the data bits originally present in the previous stages are shifted out of register 15 and the data bits originally present in the present stages are now shifted to the previous stages. Similarly, the data bits originally present in the subsequent stages are shifted to the present stages where they are ready to be encoded, and the next binary data group 010 (Fig. 5) is loaded into the subsequent stages. The small time delay of the bit clock pulse 18e with respect to the position clock pulse 35f ensures that the signals for a data word are transferred from the register 20 to the flip-flop 37 before the signals corresponding to the next data word are loaded into the register 20.

As stated earlier, the bit clock frequency is equal to the data frequency and the digit clock frequency is twice the bit clock frequency. As a result, it is self-evident that it is the location clock frequency that determines the recording speed and the associated minimum distance between signal changes on the recording medium. Consequently, once a required minimum distance between signal transitions is established, the job clock frequency must be set appropriately according to the relative speed between the recording medium and the recording head, and the bit clock frequency must then be set accordingly to half the job clock frequency.

The coding of successive binary data words continues in the manner described above. As a result, as soon as the binary data word 111 is in the present coding stages of the register 15, a signal is generated at the connection B7 of the encoder 17, as shown in FIG. 7, and is sent via OR gates 23 and 38 to the stages S1 and S4 of the register 20 transferred. The signals at the outputs of the OR gates 23 and 38 are the code signals for the data word 111. Similarly, if the binary data word 010 is in the present coding stages of the register 15, a signal is created at the connection B2 of the encoder 17, which in turn generates a code signal at the output of an OR gate 39, which is connected to the stage S2 of the reitter 20. Next, data word 110 creates a signal at connection B6 of encoder 17, which in turn generates code signals at the outputs of OR gates 38 and 40, which are connected to stages S1 and S6 of register 20. At this time, however, no signal is loaded into the stage S5, but instead a signal is loaded into the

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Step S6 introduced because a signal was generated by the encoder 29 from drawing, through the register step by step.

is supplied and acts via the logic circuit 30. In particular. The stages SI to S6 of the register 42 each correspond in particular to FIG. 5, that the data word 101 at the positions PI to P6 in each data cell of the recording memory can be seen.

data word 110 follows, which is currently encoded. diums, and stage S6 'corresponds to location P6 of the data

Since the encoders 24 and 29 correspond exactly to the encoder 17, which immediately precedes the present data cell, the encoder 29 creates according to which data it is to be recovered from. The data becomes a binary data word 101 applied to a signal at the connection C5 read out from the storage medium in the same order. The signal at terminal C5 is transmitted via a sensor in which they have been recorded or written, OR gate 31 and an inverter 32, thereby and consequently a low level signal at the input of an AND gate, 0, for data recovery purposes a pulse corresponding to a transition that is generated at the rear 34, which blocks the passage of the signal, the edge of the data cell that is present - applied from the encoder 17 to the AND gate 34 of the data cell is in stage S6 'of register 42. At the same time, the one from the terminal is also stored, while a transition which transmits the signal supplied from the rear edge C5 to an AND gate 33 where the present data cell is recorded, in step S6 it with the high level signal is summarized, the 15 of the register 42 is included in order to be ready for a data return received from the connection B6 via the OR gate 40. 5 is now used, and as a result loads a signal into stage S6 of the regi recovery of the first binary data word, which has been esters 20. This method of operation corresponds to the current combination, namely data word 001 . The number twelve of Fig. 8. Finally, when the binary data word creates a signal transition at location P4 word 101, the present coding stages of register 15 20 during the coding and recording process, and now generated, the binary data word is reached 110 a higher level signal is shifted to the previous more during recovery, and another (not shown in FIG. 5 at stage S4 and a low level signal at all tes) word is moved to the subsequent stages of register 15 gela remaining stages of the register 42 after the reading of the. first data cell of the storage medium has ended, which at this time then the encoder 17 creates a 25 the position clock pulse 44a occurs. Shortly before the signal at terminal B5, which generates a code signal at the output of the position clock pulse 44a, the reading-controlling OR gate 38 is generated, which is connected to the AND gate 28 signal, which is connected to the corresponding 45 of the shift register 46, in order to apply a signal to the stage S1 of the register 20, from a high to a low level, but this process is changed by a signal at the connection so that the register signals at its connections DO, Dl A6 of the encoder 24 according to the binary 30 and D2 created there, which prevents the corresponding stages of the data word 110. The signal at connection A6 corresponds to register 46. When the front is applied via the OR gate 26 and the inverter 27, the edge of the word clock pulse 47a, which is applied to the word clock signal at a low level at the input of the AND gate 48 of the shift register 46, becomes gate 28 generate to thereby block any signal through signals actually loaded at the connections DO, Dl and D2. This mode of operation corresponds to the current 35 and these signals are in a temporary, combination number nine of Fig. 8. The mode of operation of the coding non-steady state and does not stabilize until the rer 17,24 and 29 and the associated logic elements of the leading edge of the position clock pulse 44a is present. As for FIG. 6 for the various other possible combination recordings, the frequency of the bit clock pulse is equal to that of the binary data words in the present, previous half frequency of the position clock pulse, and the bit clock in and subsequent stages of register 15 are also in «Pulses are somewhat delayed with regard to the position pulses. Fig. 8 reproduced. As a result, when bit clock pulse 49a is applied to bit clock terminal 49 'of register 46 before the recovery device is described, it should be noted in conjunction with Fig. 8 that the run signal is at the stage associated with terminal DO of the register 46, the combination numbers 9, 11, 13 and 15 points in time, is assigned, from the register to a binary data - to which a signal transition, which shifts at the point PI in a line 50, and the signals in stages D1 and D2 data cell should be performed, in reality not shifted accordingly one step to the right since a transition at the P6 location in the ben. The word clock pulse 47a is then changed and goes back as was done immediately before the data cell returned to a high level for another signal. This is an important feature that must be prevented at the appropriate time from the connections DO, Dl and D2, and appropriate attention must be paid if the 50 shift afterwards until the word clock pulse is applied to recover binary data from the encoded signal, 47b bit clock pulses 49b and 49c the original signals in the binary direction as can be seen from the following description of the recovery stages of the connections D1 and D2. 9 and 11, the coded 44g to be reproduced will shift the coded signals corresponding to the transitions of the following signal pulse stream from which the binary data is to be withdrawn 55 into the register 42.

are to an input terminal 41 of a shift register. The logic which is used to recover the original sters 42 for signal readout. The signal pulse stream to be reproduced, binary data words from the pulses used in the register 42 is converted from the analog signal, will now be explained with reference to FIGS. 9 and 10. If received, the first binary data word 001 read from the magnetic storage medium. which has received a pulse on which the originally encoded signal, 60 of stage S4 of register 42, is generated, a signal via which represents binary data, in the form of a sequence of magnetic flux OR gate 51 is applied to terminal DO- Since a pulse transitions were recorded, each of which a signal - not simultaneously at stage S1 or S6 of register 42

Transition of the encoded signal, and consists of is generated, the signal level at the output of the OR-

a sequence of pulses, each one of a signal transition gate 52 low, and consequently the signal from is prevented from corresponding to the encoded signal. Position clock pulses which at stage S4 via the AND gate 53 to an OR gate 54

the clock connection 43 of the register 42 are created. As a result, the result of a pulse is only in the coded signal pulses with the same frequency, with the stage S4 of the register 42 an output 001 (or 010) on which the coded signal transitions during the up on the binary data line 50, as by the continuous Combina-

tion number 3 of Fig. 10 is displayed. The next binary data word 111 creates signals in stages S1 and S4 of register 42. The signal in stage S4 is again applied via OR gate 51 to terminal DO of register 46 and also to an input of AND gate 53, while the signal at stage S1 is transmitted via OR gates 52 and 56 to terminal D2 of register 46. The signal at the output of OR gate 52 is also applied to an input of AND gate 53 where it is combined with the signal from stage S4 to provide a signal through OR gate 54 at terminal D1 of register 46 create. The result is then a signal stored in each stage of register 46, thereby reproducing binary data word 111 corresponding to the signals in stages S1 and S4 of register 42, as indicated by sequence number 14 of FIG. 10.

A signal is stored in stage S2 of register 42 when the next binary data word 010 is to be recovered. The signal in stage S2 is transmitted via the OR gate 54 to the terminal D1 of the register 46, and no further decoding takes place during the reading out of this cell, so that the data word 010 is immediately reproduced on a binary data line 50. The following binary data word 110 is represented by signals at stages S1 and S6 of register 42. The signal at stage S1 is transmitted via OR gate 52 to an input of AND gate 57 and via OR gate 56 to terminal D2 of register 46. At the same time, the signal at stage S6 is transmitted via the OR gate 58 to one input of an AND gate 59 and to the other input of the AND gate 57, a signal via the OR gate 54 to the terminal D1 of the register 46 is created. In this way, word 110 is created on data line 50 in accordance with the signals at stages S1 and S6 of register 42, as indicated by serial number 13 of FIG. 10. When the last binary data word 110 is finally to be recovered, a signal is only stored in stage S6 'of register 42. This is the same signal that was stored in stage S6 when the previous binary data word is to be recovered. The signal at stage S6 'is transmitted via OR gate 52 to an input of AND gate 55 which at the same time has a high level signal at its other input from inverter 60 in the absence of a signal at stages S5 and S6 of register 42,

whereby a signal is applied via the OR gate 51 to the terminal DO of the register 46. In this way, the signal at stage S6 'of register 42 results in signals at the stages associated with terminals DO and D2 of register 46 to create word 101 on binary data line 50, as indicated by serial number 9 of the combination number 9 Fig. 10 is displayed. The binary data words that are recovered in the stages of register 46 by means of the circuit of FIG. 9 corresponding to the other signal combinations are shown in FIG. 10, which, which should be noted, corresponds to the coding function table of FIG. 8.

Some other features of the code, apart from those already mentioned, are of interest and should be mentioned here. It can be seen from FIG. 10 that a total of 23 ones, which represent signal transitions, are generated at different locations for all possible combinations. Sixteen of these ones (including the dashed lines) appear in double windows, that is, either at positions P6 'or PI or at positions P5 or P6, which are redundant positions, as indicated by the combination logic, which is shown in logical equation form as follows: in terms of mass:

DO = P4 + P2 • (P5 + P6) + (PI + P6 ') • (P5 + P6)

Dl = P2 + (PI + P6 ') • (P5 + P6) + (PI + P6') • P4

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D2 = (P1 + P6 ') + P3 where a dot means AND, + OR and a dash NOT. In this way, about% of the transitions are arranged so as to alleviate a time tolerance. Furthermore, the consecutive combination numbers 5, 6, 10, 14 and 15, for which the double window condition exists, are correspondingly more crowded than the other combinations, so that there are only three or four digits between the ones of such combinations. A total of ten transitions exist under these relatively more crowded states and of this total number six or again about% occur in double windows, whereby a time tolerance is further alleviated.

A data recording and recovery system with the encoding and decoding circuits of Figs. 6 and 9 is shown in Fig. 12, with the coding circuit 61 corresponding to Fig. 6 and the decoding circuit 62 corresponding to Fig. 9. The timing control unit 63 provides various clock signals, as well as the record and read signals used for data recording and recovery. As previously explained with reference to FIGS. 1 a and 11 b, the position clock frequency determines the data recording and reading speed. During the recording, the position clock signal supplied by the timing control unit 63 is obtained from a write clock generator 64, which can be, for example, a constant frequency crystal oscillator or an oscillator which is synchronized with the speed of the magnetic storage medium on which the data are to be recorded. The binary data to be recorded is applied to the coding circuit 61, which generates the 3 PM-encoded signal, as stated above. The encoded signal is then transmitted via a write signal processing circuit 65, a write control device 66 and a read / write switch 67 to a magnetic head 68, which records each signal transition of the encoded signal in the form of a corresponding magnetic flux transition on the storage medium 69. The write signal processing circuit 61 may have signal processing circuits which cooperate with the write driver to improve the quality of the magnetic recording.

When recovered, the magnetic head 68 outputs a signal corresponding to each magnetic flux transition on the storage medium 69 so that it is transmitted to the input of the decoding circuit 62 via a preamplifier 70 and a read signal processing circuit 71. The signal supplied by the magnetic head is in analog form and has positive and negative parts that represent the successive flow transitions on the storage medium. The analog signal is converted into an encoded signal pulse stream by means of the read signal processing circuit 71, each pulse corresponding to a flow transition on the storage medium. The time of occurrence of the individual pulses of the encoded signal pulse stream is not identical to the signal transitions of the recorded, encoded signal due to a bit shift and other distortions in the recording and recovery process. For this reason, the encoded signal pulse current is applied not only to the decoding circuit 62, but also to a read clock generator 72. For example, the read clock generator may include a phase locked oscillator that is synchronized by the encoded signal pulse current to run at a frequency that is a harmonic of the frequency that corresponds to the period of the minimum interval between signal transitions, or more precisely, to run at a frequency that is the same 2 / T is what is equivalent to the digit clock frequency. When the position clock frequency is controlled in this manner by the encoded signal pulse stream, the decoding circuit 62 operates in the manner described above to do the

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reproduce original binary data at their output. Summarize and merge in the case of binary

Although the preferred embodiment of the invention requires data words 000,011 and 110, for which an over described with reference to an encoding scheme occurs at location P2 of cell 2, if it is one in which each binary data word consists of three bits of words 101, 110 or 111 follows, for which a transition occurs at and through signal transitions at one or two selected 5 of the PI location of cell 1.

Positions of a total of six places in a data cell are shown. In addition to changing the data row arrangement with regard to positions, other logical forms of a data word can of course also be used, as is used in the preceding paragraph men within the scope of the invention. As an example, each binary data word can of course also be used in another way by means of a transition in the coding circuit. For example, one or both of two adjacent data cells may have shift registers for writing data that are only set to one, each having a length that is equal to 1.5 T, responding to the bit clock signal, and having a capacity of only and where each cell has one and a half bits of binary data a data word, in conjunction with coding and logic corresponding shafts are used, which are characterized by a word clock

A coding scheme of this kind is shown in Fig. 13. nal operated to the data word from the data shift

It can be seen from this that in this case the data cell registers are recorded and the code signals are generated.

which match the signal transition points P3. To which in turn are applied to a modulator that has the required minimum distance of 3T / 2 between the signal-modified shift register, which is to be maintained by means of a multiple transition, the insits at the positions P2 phase clock signal are controlled in order to summarize and and PI from cell 1 or from cell 2, which corresponds to the binary data merging according to the invention together with a word 100, to a transition at point P3 of the 20 storing and shifting the shift register to single cell 1, i. H. on the edge between cells 1 and 2, to carry out signals.

quantified and merged. Similarly, one is

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8 sheets of drawings

Claims (10)

629347 2 PATENT CLAIMS that the input group is an information shift register (15) 1. A method for converting a binary input data, which receives the input signal in series and has three streams in an output data stream with predetermined successive groups of outputs, the minimum and maximum distances between signal change to the flashback circuit (24), the coding circuit (17 , 20, 23, and for later reconversion of the output data (5, 25, 30, 38, 39, 40) and pelt to the forward gaze circuit (29) into a pelt corresponding to the input data stream, and that each coded output signal data cell from data stream, wherein when converting the input data - an output signal shift register (20) the coding switching current is divided into words of equal length and these words are read. into corresponding data cells of the output data stream. 11. The device according to claim 10, characterized in that each of a number of spaced-apart numbers that the information shift register (15) has a capacity arranged from one another a signal change of nine bit positions has that the coding circuit can gate-th, which number is greater than the number of in a circuit (23,25,30,38,39,40), which bit positions contained in the one-word, and the positions at which ahead - Gears of an octal encoder (17) are connected to receive a signal change, by comparing the fourth, fifth and sixth bit positions of the information shuffling arrangement of the data bits in the present word with the '3 registers (15), and that the look-back and the arrangement of the data bits in the preceding and following look-ahead circuit are determined as an octal encoder (24, 29), and wherein be i of the reverse conversion are those whose inputs to the first to third or the seventh to data cells generate a ninth bit position of the information shift register (15) corresponding to the input data stream, characterized in that when are closed and that the outputs of the two the latter - a signal change (e.g. B. P5) in a data cell (FIG. 5: Z4) 20 th octal encoder (24, 29) at the corresponding union of a signal change (for example PI) in the adjacent data circuit (25 or 30 ) of the gate circuits (23, 25, 30, 38, 39, cell (Z5) do not have the minimum distance (Fig. 1: 3 / 2T) 40), which would have six bit positions of the output, these two signal changes (P5, PI) Supply in parallel using a single-signal shift register (20). zige signal change (P6) are replaced, the at least the 12th device according to any one of claims 8-11, thereby Minimum distance from each of the adjacent signal changes & marked that for converting the output data back (e.g. PI to Z4). stream into a corresponding to the input data stream 2. The method according to claim 1, characterized in that data stream means are provided in order to cyclically decode the coded data — that said only signal change at the boundary (P6) cells, said means being a read signal between two data cells (e.g. Z4, Z5). nal shift register (42) to the coded data cell 3. The method as claimed in claim 1 or 2, characterized in that it receives serially and in each decoding cycle a net that each data word has three data bits. encoded data cell and one or more signal changes 4. The method according to any one of claims 1 to 3, characterized to include the preceding data cell, Gatterschaltun-characterized in that each data cell has six possible genes, which has the contents of the read signal shift register (42) change parts (PI to P6). Edit in parallel to decode each encoded data cell 5. The method according to any one of claims 1 to 4, thereby to separate 35 and earlier combined signals and the decoded characterized that one (P6) of the possible signal change data cells to the read information shift register (46) to deliver the boundary between two data cells (z. Z4 and Z5) lead, and forms the means in the read information shift register. (46) to deliver the contained information in series. 6. The method according to any one of claims 1 to 5, characterized 13. Device according to claim 12, characterized in that the data bits in the input data stream, that the read signal shift register (42) has a capacitance and the signal changes in the output data stream are clock-controlled has seven bit positions to be ert in each decoding cycle. a six-bit coded data cell and the last bit of the previous 7. The method according to claim 6, characterized in recording going coded data cell. that data bits have half the clock frequency of the signals generating the signal changes in the output data stream. 45 8. The device for carrying out the method according to claim 1, characterized in that for converting the input data stream into an output data stream, look-back and forward-look circuits (24, 29) are combined. The invention relates to a method for converting a circuit (25, 30) in a coding circuit (17, 20, 23, 25, 30, thus binary input data stream into an output data stream, for example 38, 39, 40), which combination circuits use the coding circuit for the purpose of transmitting or registering the data, and for handling the content of at least some of the data Bit positions in the later reconversion of the output data stream into a data stream corresponding to the outgoing and subsequent data cell, pre-input data stream corresponding to which combination circuits (25, 30) are each two of the conversion of the input data stream into words of the same signal changes, which in the output signal is classified with less than ss length and these words in the corresponding Minimum distance would appear to be converted by a single data cell of the output data stream, replace signal change which has at least the minimum distance in which there were a number of spaced from the adjacent signal changes. a signal change can occur at 9. The device according to claim 8, characterized in that the number is greater than the number of bit positions in a word that contain the coding circuit (17, 20, 23, 25, 30, 38, 39, 40), and the locations at which it is likely to encode each data cell so that all signal and signal changes occur, by comparing the arrangement of changes within the data cell at least by the minimum of the data bits in the present word with the arrangement of the time spacing , and that the merge switch data bits in the preceding and following word determinations (25,30) operate so that they become two signal changes in, and in the reconversion, the data cells adjacent data cells, which by less than the minimum one the input data stream corresponding data stream would be spaced mum apart by a single signal. at the border between the data cells. The invention is particularly in transmission systems 10. The device according to claim 9, characterized, and in magnetic storage and recovery systems 3 629347 applicable for digital data. Recovery window is made narrower, the size of a In the course of the development of magnetic memory and bit shifting, which can be permitted proportional recovery systems for binary data, the skin's eye is reduced. A phase comparator in the phase locked has been aimed at, the data acquisition and fiber oscillator is used to increase the phase of the reproduced, from the system's capacity to as much data as the storage medium read signal transitions with a possible in a predetermined time interval or a (pre-compare signal given by the phase locked oscillator) length of the recording and recording medium is applied to accommodate a signal for controlling the oscillator such as a disk or a tape. This has been done in order to achieve the reproduced signal transitions by encoding the binary data so as to follow signals. A filter circuit of the phase-locked oscillator is to bring together or bring changes or transitions which the respective ones and are provided so that the oscillator represents the average, time zeros of the binary data, as close as is practically possible to fixed positions of the reproduced signal save. Can follow through pasts, while he comes to their current different, such systems own conditions, changes remain insensitive. In this way, however, in practice, limitations, as far as this affects the recovery window, generally in terms of data packing density, are kept in relation to accurate is reproduced signal transitions. When recording and playing back the data. Such an unexpected bit shift that occurs via a previously Restriction is a phenomenon that generally goes beyond a bit-tuned value, if the reproduced signal shift is called, which in the course of the re-transition would lie outside of its recovery window, binary data would occur from an encoded signal, which would result in an error in the Detect and a faulty has been recorded on the storage medium. She is 20 data recovery results. characterized by shifting the reproduced from the above, it can be seen that Signal transitions with respect to their nominal or nominal positions require a bit shift to be reduced in order to improve the data and is the consequence of being too close or of being recovered, and that of reducing an urging of the neighboring bit shift on the storage medium itself depends on a disorderly drawn transitions. In particular, bit crowding of adjacent transitions in the shift occurs as a result of the interfering or mutually encoded data signal. In order to meet this and other flow of each reproduced signal transition with regard to criteria which are given below for the reproduced signal transitions which are adjacent to one another, if these open up, various coding methods have been proposed and signals taken out from the storage medium have been developed. Some of the required properties will be one. The magnitude of a shift, which occurs with 30 corresponding coding methods at each point of each reproduced signal transition, is given by the briefly and later in connection with the description of packing density and the degree of asymmetrical arrangement of the invention and selected, known codes which are described in that of the transitions on both sides of each figure shown are explained in more detail. One of the required signal transitions is fixed, the size of a variety of properties being, of course, that the coding must be carried out in a manner corresponding to a higher packing density and in a way in order to avoid an inadmissible bit shift which is proportionally larger to the asymmetry of the respective signals. This is achieved by having an adequate (DT-OS14 99 930). Distance between successive, on the memory A bit shift is of considerable importance since it is created directly in connection with the recorded signal transitions, but the binary data exactly need not be at the expense of a reduction in the recording reproduce how to be made from the following remarks on 40 density. Another required hen is. If data are to be recorded, they are encoded, as is the property of a coding method that one of the above has already been carried out and, as in the following, is carried out in the individually large distance between recorded signal transitions, and is then avoided in a clock-controlled manner on the gene, so that the possibility of excluding storage medium is applied so that each signal transition becomes self-clocking during data recovery to achieve a prescribed interval or segment of storage 45. In the case of self-clocking, the encoded, medium is recorded. Recording on a signal recorded beforehand on the storage medium and the timebase that is matched therewith is essential in order to be able to determine the corresponding read-in signals or the reproduced signals of such and zero data bits if they have properties for the purpose of the required control of the phase playback of the binary data stream from the storage-rigid oscillator for data recovery to be read out medium. Usually, one is carried out as stated above. If the possibility of the so-called controlled oscillator or preferably a phase-locked oscillator called self-clocking is missing, a separate clock capacitor must be used in order to provide a time-oriented window for the channel on the recording medium, and this is recovery of the binary data from the reproduced and . a. not wanted for the reason, because then an alignment To create signal transitions. The phase-locked oscillator of the read / write head of the clock channel with respect to the ones worked, for example, usually how the heads assigned to the person skilled in the art must be kept 55 data channels. is known so that it runs at a nominal frequency, which is a harmonic of the frequency selected as the requirement for a sufficient minimum distance, which is the fundamental between successive signal transitions on the one hand period of the encoded data signal, and thereby generates an unacceptable bit shift , and blanking window signal associated with each reproduced signal - the request for a limited maximum distance between the transition to see the binary data from the encoded 60 successive transitions on the other hand so as to recover data signal. In this context, self-clocking is to be achieved, it is essentially equiva-self-evident that the recovery window is linked to the criterion that the number of taken in is characterized by a peculiarity, which is generally reduced to a minimum by time-control transitions per data bit becomes. or vice versa that the number of bits of data from each on If the signal transitions are more tightly packed, the transition taken must be shown to be narrowed to a maximum fixed-recovery window in order for a feel to be placed. a reproduced signal transition in a window that is not assigned to the various coding methods currently used. Of course, if those are generally in one way or another in terms of 629347 insufficient view of the properties shown above. The so-called NRZ (no return to zero) or NRZI (no return to inverted zero) codes are, for example, in the case of a succession of several one or zero bits due to long gaps between recorded signal transitions marked in order to exclude self-clocking. Frequency modulation (FM) and phase modulation (PM) codes, on the other hand, although they provide self-clocking, are characterized by a small spacing of the recorded signal transitions and consequently limited in data pack thickness and timing tolerance, which is required by to avoid an impermissible bit shift and to guarantee an exact data recovery. The small spacing between the transitions in the 15 FM and PM coding methods is due to the periodic insertion of clock transitions in the data transition stream to achieve self-clocking, and in this way these codes become the number, criterion required minimizing recorded transitions per 20 data bits. In a recently developed code called Modified Frequency Modulation (MFM), the limitations of the FM, PM and NRZ codes have been overcome to some extent and have resulted in it having been widely used in the past 25 years it is self-clocking and essentially has twice the packing density of the FM and PM codes, without the difficulty becoming more difficult due to a bit shift or the timing tolerance being reduced. In the 30 MFM coding method, no additional clock transitions are used, but instead the data transitions are used for clock control and in this way an improvement with regard to the criterion of reducing the number of coded transitions per data bit to a minimum. Still, the binary data packing density which can be achieved with the MFM code is limited by the minimum distance which it creates between the successive signal transitions recorded on the storage medium. This limitation of the MFM code with respect to the invention will be understood in detail from the following description of the preferred embodiment of the invention. According to the invention, therefore, an encoding method and an associated recovery method are to be created which create a self-clocking action, while at the same time an essentially 50 percent or higher improvement in the data packing density compared to the currently customary methods is achieved. The invention is also intended to provide a method for encoding binary data, in which the number of data bits which are represented by each transition of the encoded data signal is increased in relation to the number which is achieved with the encoding methods currently customary.