CH628761A5 - Method of speech encryption by time scrambling - Google Patents

Description

The invention relates to a method for voice encryption according to the preamble of patent claim 1.

The mode of operation of devices which are operated using the aforementioned method is shown in FIG. 1. The main components of such a device are the key modulator SM and the key transmitter SGI on the transmitter side, or the back modulator RM and the key transmitter SG2 on the receiver side. The transmitter-side clear signal Kl is in the key modulator SM with that of the key transmitter SGI

coming key signal SI processed to the encrypted signal VS and finally transmitted to the receiver. In the back modulator RM, the encrypted signal is converted back to the clear signal K2 with the key signal S2 from the key transmitter SG2.

As shown in FIG. 2, the modulator and back modulator essentially consist of a number of speech memory cells 0, 1, 2,... 7, in which speech segments of e.g. B. 40 ms length (segment length T) can be stored. With the aid of the key transmitters SGI and SG2 and the associated key signals, a decision is then made, after a time interval of length T has elapsed, by setting the synchronous switches W1 and W2 which transmitter or receiver-side voice memory cell is to be filled next. When a new voice segment is read into a voice memory cell, the previous content of this cell simultaneously leaves the modulator SM or back modulator RM (change of content of a voice memory cell) and is added to the encrypted signal VS or the clear signal K2. In this way, the segments of the clear signal Kl in the key modulator M are delayed by different whole multiples of the segment length T. If a speech segment in the key modulator SM has now been delayed by the time p * T, the key transmitter SG2 ensures that this segment experiences a further delay by q • T in the back modulator (p and q natural numbers). The key signals S1 and S2 are correlated in such a way that the total delay experienced by a segment in the modulator and back modulator results in just 2n-T. Here, n means the number of speech memory cells in the modulator or back modulator; in the example given, n = 8. The following applies to each language segment: p + q = 2n. The clear signals Kl and K2 therefore differ only in that all segments of K2 have experienced the delay 2n • T compared to those of Kl. In the special case that a speech segment in the modulator has already experienced the delay 2n-T, the memory-free circuit D (FIG. 2) is provided on the receiver side.

Through the patents CH-PS 237 094, CH-PS 232 786 and CH-PS 518 658, voice encryption devices have become known which operate according to the time-scrambling method. There may be differences. a. in the mode of operation and structure of the key transmitter SGI and SG2. In the first two documents, key transmitters are used, which call the voice memory cells of the modulator SM using the key signal S1 according to a fixed program in a constantly recurring sequence. An unauthorized third party who knows the mode of operation of the device and who has the encrypted signal available therefore has good indications for decryption.

The third of the publications mentioned brings an improvement. A pseudo-random generator is used in the key generator SGI to generate the key signal S1. The order in which the voice memory cells are called up one after the other for a content change thereby essentially becomes a random sequence, roughly comparable to the sequence of throwing results in a dice game. Here, however, the encrypted signal can still contain plain text or places similar to plain text, because it is not excluded that the key transmitter SGI calls the same or a similar sequence of voice memory cells at a later time as at an earlier time. If an unauthorized third party has recognized such plain text passages, the rest of the decryption work will be made considerably easier for him, since the number of segments exchanged is lower.

DT-OS 2 455 477 has disclosed a key transmitter which contains a code corrector which checks whether the content of those voice memory cells of the key modulator SM which are generated with the aid of the pseudo-random generator for

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the next change of content is provided, together with the previously transmitted language segments would result in sequences similar to plain text. If the result of this check is positive, the transmission of the corresponding language segment is prohibited and another cell is selected according to a certain program. The test is then repeated with this cell. Only when sequences similar to plain text are excluded is a voice memory cell of the modulator released for a change of content.

This process also has imperfections. It has been found that certain delays in the speech segments - in particular the delay T and 2n • T - occur preferentially. An unauthorized swapping back of the speech segments of the encrypted signal is now possible with justifiable effort if this swapping is carried out by a systematic search for related speech segments.

The invention has for its object to provide a method for voice encryption using the time scrambling method with the aid of a pseudo-random generator, which makes systematic exchange of the voice segments of the encrypted signal much more difficult.

This object is achieved according to the invention in that instead of the forbidden voice segment, the segment is transmitted which has been delayed longest in the sender's voice memory and does not form a sequence similar to plain text with the segments already transmitted.

With the aid of the figures, the method according to the invention and the aids necessary for this purpose are to be described, for example.

The upper part of FIG. 3a schematically shows an example of a marking register M which is contained in each of the two key transmitters SGI and SG2. It is designed as a shift register and consists, for. B. from sixteen addressed in the following positions cells PI to P16. The associated address is indicated above each position in FIG. 3a. In addition to the 'marking register, each key generator contains a pseudo-random generator as an essential component. The processes which relate to the marking registers and the pseudo-random generators in the following description are the same on the transmitter and receiver side and run synchronously. The synchronization can e.g. B. be carried out according to the method described in DT-OS 2 455 477.

After the devices have been enabled to start, the addresses of the 8 receiver-side and 8 transmitter-side voice memory cells, or voice memory addresses for short, divided into numerical part a and code bit part b, are read into the marker register in an agreed sequence. Addresses with the identifier bit 0 belong to the transmitter-side and addresses with the identifier bit 1 to the receiver-side voice memory cells. The change of content of a speech memory cell in the modulators is triggered by a clock cycle - here called frame clock. The frame clocks have the time interval of a segment length T. Between two frame clocks, the key transmitters determine, in a cycle consisting of several method steps, that voice memory address whose associated transmitter or. the receiver-side speech memory cell is next in question for a content change. The determination of these voice memory addresses is first to be explained on the basis of the changes in the status of the marking registers without any further details. In this context, state means the sequence of the addresses stored in the marking registers.

3a shows an initial state of a marking register M, it is the state in which the marking registers are located shortly before the occurrence of a frame clock. The initial state is characterized by the fact that you get a plain text sequence if you look at the content of the voice

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I put them together in the same order in which the associated addresses from position 16 to position 1 are in the marking registers.

The lower part of FIG. 3a shows the content of the voice memory cell, the address of which can be found in the position above it. For the sake of simplicity, the plain text consists of the alphabet, with a language segment comprising exactly one letter.

All voice memory cells of the transmitter and receiver-side voice memory are filled with one of the letters io from a to p. The first letter a is now added to the clear signal K2. This letter is the content of the speech memory cell, the address of which is in position 16. Therefore, when the frame clock occurs, the key transmitter SG2 transmits the address (7/1) to the reverse modulator on the receiver side, whereupon the latter releases the associated voice memory cell for a change of content. At the same time, according to a selection method which will be explained later and is dependent on the pseudo-random generator, a transmitter-side voice memory address, e.g. B. the address (60) selected in position 8 and transmitted to the key modulator by the 20 key generator SGI. This also releases the associated voice memory cell for a change of content. The speech memory cell with the address (60) then takes up a new speech segment of the clear signal Kl, namely the letter q, while its previous content, 25 the letter i, is sent to the receiver as part of the encrypted signal and there in the speech memory cell with the address (7/1) is saved. 3b shows the new conditions.

So that a further change in the content of the voice memory cells 30 can take place in the same way at the next frame cycle, the status of the marking register M is now carried out: the contents of positions 8 and 16 are interchanged and the entire content of the marking registers is then cyclically shifted by one position. The result shows 35 Fig. 3c. The new state is clearly an initial state in the sense explained above.

Consequences similar to plain text should be avoided in the encrypted signal. Such sequences are to be understood as time-sequential speech segments of any number, which either have the same chronological order as before the encryption - that is, form pure plain text - or have been changed only slightly by the encryption process compared to the plain text sequence, such as: B. the mere exchange of the chronological order 45 of two successive segments. In order to avoid such consequences, no letters belonging to the neighborhood of the letter i, namely the letters h, j and k, may be sent in the next frame clock in the present case. Positions 7, 8, 9 and 10 50 are therefore marked as prohibited. As a result, the transmitter-side voice memory cells, the addresses of which can be found in these positions, are excluded from a change of content at the next frame cycle. The forbidden positions are ticked in FIGS. 3c and 3d. Since the prohibitions 55 remain effective even after the frame after the next but one, it is ensured that in the encrypted signal at least one letter i follows that does not belong to the neighborhood of i before the h is sent and at least two letters before j or k are sent. 60

The initial state shown in FIG. 3c represents a frequently occurring case: a speech segment - here the letter b - has already experienced the maximum permissible delay in the modulator SM. This case can be recognized from the fact that a sender's voice memory address - in FIG. 3c the address 65 (00) - has reached position 16 of the marking register. The voice memory cell belonging to the address (00) is now read out unconditionally, otherwise the correct insertion of the

Letter b in the clear signal K2 is no longer possible. For the same reason, there is no additional delay on the receiver side. The back modulator, controlled by the identification bit 0, selects the memory-free circuit D and feeds the transmitted letter b directly to the clear signal K2. When the letter b is read out on the transmitter side, a new segment, namely the letter r, is read in at the same time. In order to establish the next initial state, the content of the marking register now only needs to be shifted cyclically by one position. The result is shown in Fig. 3d.

If the case exists that a receiver-side voice memory address is in position 16 (cf., for example, FIG. 3a), it is determined in which position the transmitter-side voice memory address is that which was generated by the pseudo-random generator. If the determined position is not prohibited, all further steps take place in the manner already described. However, if the determined position is marked as forbidden, then that sender-side voice memory address is sought which is stored in a non-prohibited position and whose associated voice memory cell contains the longest delayed voice segment. This voice memory address can be found by going through the marking register in the initial state from position 16 to position 1 and asking for the first position which is not prohibited and which contains a transmitter-side voice memory address. According to Fig. 3a that would be z. B. position 15 with the address (00). Once the position sought has been determined, all further steps are carried out in the manner already mentioned.

The measure outlined for selecting a transmitter-side voice memory address in the event that the address proposed by the pseudo-random generator is stored in a prohibited position results in an approximately equal distribution of the relative frequencies of all occurring delays of voice segments in the key modulator. The equal distribution results in a significant complication of the decryption work for an unauthorized third party who can no longer rely on prevalent frequencies with the shortest and longest delays - as in known methods.

4 and 5 serve to explain the technical details and other components which are required to carry out the previously mentioned method steps. The process cycle lying between two frame cycles is implemented in 32 work files with a cycle frequency of z. B. 750 Hz. The 32 work cycles are divided into two main sections, of which the first comprises 17 and the second 15 work cycles.

If a voice memory consisting of n voice memory cells is generally used, that is to say with a marking register M of 2n positions, exactly 4n work cycles are required to implement a method cycle in accordance with the information given below. The two main sections are then divided into a 2n + 1 bar and a 2n - 1 bar section.

In the first main section, after the occurrence of a frame cycle, all 16 positions of the marking registers are combined in a ring (see FIG. 4). With each work cycle, the content of the marking register is cyclically shifted by one position. Accordingly, at the end of the first main section, the voice memory address, which was initially found in position 16, is in position 1. The content of position 1 is written into an auxiliary memory Y and a readout memory X (both not shown).

During the circular circulation of the content of the marking register, a sender-side voice memory address is searched for, the associated cell of which is suitable for the next change of content. 4 shows the components,

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who are involved in the search, namely the pseudo-random generator PZG, the comparator VGL, a NOR gateGl, an OR gateG2, an AND gateG3, a 5-bit counter Z, a flip-flop FF1 and a 14- and 16-bit shift register SR14 or SR16. The two shift registers are used to set and check 5 prohibitions. If a cell of the two shift registers contains a “1”, the position of the marking register above it is considered prohibited (cf. FIG. 4). Further explanations on the setting of the prohibitions follow below.

During the first main section, the output c 10 of the shift register SR14 remains connected to the input of the register R16. The outputs c and d of the shift register SR 14 or SRI6 and the characteristic bit output b of the marking register M are led to the three inputs of the NOR gate Gl. The digit output a of the marking register M leads to comparison I5 rather VGL. When a frame clock occurs, the flip-flop FF1 is in the reset state and the counter Z begins to count the work cycles. It contains an erase pulse and at the same time the flip-flop FF1 a set pulse if the following two conditions are met20:

1. A binary “0” is present at each of the three inputs b, c and d. According to what has been said so far, this means that position 16 currently contains a sender's memory address 25, which was stored in a non-prohibited position in the initial state.

2. The flip-flop FF1 is in the reset state or the comparator VGL determines whether the digits at the digit output a of the marking register M match the digit offered by the pseudo-random generator PZG.

Within the first 17-cycle main section, at least one, but at most two, erase pulses are sent to counter Z and as many set pulses are sent to flip-flop FF1. 35

As follows from the conditions for triggering an erase pulse, either the non-forbidden transmitter-side speech memory address that was generated with the aid of the pseudo-random generator or the one in whose associated cell the .0 language segment that is also not prohibited. This address is later transferred to the read-out memory X (not shown).

Fig. 5 shows the components which are required for the second 15-stroke main section of a cycle. There is no longer any connection between the 45 components shown and those that were only required for the first main section.

In addition, position 1 of the marking register M is separated by the switch S from the remaining positions, which in turn are connected to form an annular shift register. The following operations depend on whether in position 1, i.e. H. at the beginning of the first main section in position 16, a sender's voice memory address is or is not. Because of the connection of the characteristic bit output from position 1 via the inverter I to the counter Z, the latter receives an additional erase pulse immediately if position 1 contains a sender address. In this case, the counter Z can no longer reach level 16 in the next 15 cycles. The result of this is that the switch S remains in the position shown 60 until the end of the second main section and the contents of positions 2 to 16 are therefore only shifted in a circle until the original starting position is restored. This takes into account - taking into account the processes in the first main section - a cyclical shift of the entire contents of the marking register by one position at the end of the second main section. At this time

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the content of position 1 is transferred to the readout memory X (not shown).

If there is a receiver-side voice memory address in position 1, the connection between position 1 and counter Z is immediately disconnected. The counter continues to run and reaches level 16 when the sender's voice memory address, which triggered the last delete pulse in the first 17-stroke main section, is again in position 16. Depending on the level 16 of the counter Z, the following processes are triggered: The flip-flop FF2 outputs four binary ones to the shift register SR14 and the switch S is flipped for one working cycle. The one-bar flip of the switch S has the effect that the content of position 16, namely the address of the voice memory cell provided for a content change on the transmitter side, reaches position 1, while the content of position 1, namely the address of the voice memory cell provided for a content change on the receiver side , reached position 2. At the end of the second main section, the contents of positions 2 to 16 therefore have the same position as at the beginning, with the difference that the position which was initially occupied by the address of the voice memory cell intended for a content change on the transmitter side now has the corresponding address on the receiver side contains. Once again taking into account the cyclical shift of the entire contents of the marking register resulting from the first main section, the new initial state is reached at the end of the second main section. In this case too, the content of position 1 is now transferred to the readout memory X.

The four binary ones, which the flip-flop FF2 outputs to the shift register SR14 when the count 16 occurs, are shifted to the right up to the fifteenth clock in parallel with the content of the marker register, in such a way that a binary one of the address of that memory cell (e.g. B. leads the address (7/1) in Fig. 3b), which is provided on the receiver side for the next change of content, one facing it and two others following it. Any address that appears in the first major portion of the next cycle at the output of the marker register at the same time as a one at the outputs of registers SR14 and SRI 6 is considered prohibited. The ones act as prohibitions in that they prevent the triggering of an erase pulse on the counter Z. Since the shift registers SR14 and SRI6 are connected in series in the first main section, a set binary one takes effect in two successive cycles. The first time at exit c and the second time at exit d. The ones coming out of the shift register SR16 are lost. In this way, the prohibitions set are deleted.

In the previous description, the identical processes on the transmitter and receiver side were described. The explanations show that at the end of the second main section, the read-out memory X contains the address of the speech memory cell provided for a content change on the transmitter side, while the auxiliary memory Y at this time either contains a corresponding receiver-side speech memory cell or the address of the transmitter-side cell, the content of which is the highest permissible delay in the modulator. If the device which works according to the described method is used as a transmitter, the characteristic bit of the speech memory address stored in the readout memory X is first set from «0» to «1»,

before it is passed on to the modulator. Because triggered by the "0" code bit, a memory-free connection is selected in the modulators, but this may only be effective for the receiver. On the receiver side, the content of the memory Y can either be transferred directly to the modulator or after a temporary storage in the readout memory X.

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Claims (13)

628761 PATENT CLAIMS 1.Procedure for speech encryption by swapping speech segments of the same length in time in the transmitter and swapping back in the receiver, the swapping by reading the speech segments into a speech memory 5 with n speech memory cells and differently delayed reading, and the swapping back with a similar speech memory is carried out in such a way that a voice segment in this memory is additionally delayed until an overall delay io that is the same for all voice segments is reached, and the reading of the segments from the voice memory in the transmitter is controlled by a pseudo-random generator and in the receiver by a synchronously running pseudo-random generator is dependent and the transmission of a speech segment provided by the pseudo-random generator is prohibited in the transmitter if this segment results in a sequence similar to plain text with the segments already transmitted, characterized in that instead of the prohibition In the case of a voice segment, that segment is transmitted which has been delayed longest in the transmitter's voice memory and does not form a sequence similar to plain text with the segments already transmitted. 2. The method according to claim 1 with a marker register of the same type in the transmitter and receiver, in its 2n continuously addressed memory cells, hereinafter referred to as positions 25, the addresses distinguished by a characteristic bit, hereinafter referred to as voice memory addresses, of the n transmitter-side and n receiver-side voice memory cells The sequence agreed at the beginning of the transmission is stored, characterized by a cycle of the following procedural steps that is identical in the transmitter and receiver: a) storing the voice memory address in position 2n in a readout memory and an auxiliary memory, b) check whether the stored address is 35 a transmitter-side voice memory address with identification bit “0” and, if so, continue with step h), c) determining the position k in which the transmitter-side voice memory address is located whose associated voice memory cell is provided by the pseudo-random generator for the next 40 content changes, d) checking whether the determined position is marked as forbidden and, in the affirmative case, determine the highest position k which is not forbidden and contains a sender's voice memory address, 45 e) storing the content of the position k determined according to step c) or d) in the readout memory, 0 Mark positions k ± 1, k and k + 2 as prohibited, g) swap contents of positions 2n and k, h) cyclically shifting the entire contents of the marking register by one position, i) deleting the items marked as prohibited in the penultimate cycle, j) Check whether the device used is used as the receiver and, in the affirmative case, bring the contents of the auxiliary memory to the readout memory in 55, in the negative case set the code bit of the address stored in the readout memory to «1». 3. The method according to claim 2, characterized in that / ier said cycle is carried out in 4n cycles. 60 4. The method according to claim 3, characterized in that the 4n-cycle is divided into two sections, the first comprising 2n + 1 and the second 2n-1 cycle and that different assemblies are effective during these two sections. 65 5. The method according to claim 4, characterized in that during the first (2n + 1> cycle section, the marking register is connected in a ring and its content is cyclically shifted by 2n +1 cycles. 6. The method according to claim 5, characterized in that two shift registers are provided for marking and checking prohibitions, of which the first 2n-2 bit and the second 2n bit are long and that during the first> (2n + 1) clock Section, the two shift registers are connected in series and with each cycle via a first for. Flop a binary "0" read in and the common content of the 'shift register is shifted by one position. 7. The method according to claim 6, characterized in that a counter is provided which is at the beginning of the first (2n + 1) -clocked section at «0» and which is incremented by one stage with each clock. 8. The method according to claim 7, characterized in that a logic circuit - consisting of a comparator, a second flip-flop and three gates - is provided, which outputs an erase pulse to the counter and a set pulse to the second flip-flop if a ) there is a transmitter-side voice memory address at the output of the marker register and b) both outputs of the shift registers intended for marking and checking prohibitions are at “0” and c) the second flip-flop mentioned is in the reset state or the comparator identity between that of the random number generator intended address and the address pending at the exit of the marking register. 9. The method according to claim 8, characterized in that for the entire second (2n-1) clocked section said logic circuit is separated from all other components and that said 2n-bit shift register from the first (2n-2) bit Shift register and is separated from the clock generator. 10. The method according to claim 8, characterized in that at the beginning of the second (2n-l) -clock section, position 1 is separated from the remaining positions by a switch and that these remaining positions are combined to form an annular register and with the clock generator stay connected. 11. The method according to claim 10, characterized in that at the beginning of the (2n-1) clocked section said counter receives a delete pulse from position 1 if it contains a transmitter-side voice memory address. 12. The method according to claim 11, characterized in that position 1 and the remaining positions are connected to one another by the switch mentioned for one cycle when the counter has reached state 2n and that for this time all positions are connected in a ring and that also triggered by the level 2n of the counter, via which the first flip-flop reads four ones instead of zeros into the (2n-2) bit shift register. 13. The method according to claim 2, characterized in that the enumerated method steps are carried out with the aid of a microcomputer.