CH616290A5 - Method of transmitting information in remote control systems, and device for implementing the method - Google Patents

Description

The invention relates to a method for telecontrol systems for transmitting information from one or more transmitters to one or more receivers, in which the information at the output of a transmitter is converted into digital data in an input unit and fed to one or more output units via a transmission link which they are converted into the encryption required for the recipient, as well as a facility for carrying out the method.

Telecontrol systems record and transmit information from often distant parts of technical facilities and evaluate them for monitoring, controlling, measuring or influencing the functions of unmanned devices or machines. The term remote control thus includes remote control, remote reporting, remote measurement and remote control.

In general, the data to be transmitted are supplied by an encoder to an input unit and are brought into the form suitable for transmission via a transmission link, the telegram word, and transmitted via the transmission link to an output unit, from which the telegram word is converted again a taker is given.

If data are to be transmitted from a plurality of transmitters to the subscribers assigned to them, either several transmission links or multiple use of one transmission link must be provided, which can be achieved either by carrier frequency transmission or by time-division multiplex transmission. If the information at the output of a sensor is converted into digital data in the input unit, it can, if it is present in parallel at the output of the input unit. Either be transmitted in parallel or serially over the transmission link using a parallel-series converter. The conversion to the serial form has the advantage of a lower line requirement. In order to keep the line requirement for the transmission path low, it has also become known to connect to the transmission path in each case the input unit from which information about this is to be delivered to the assigned output unit. Since this can only take place if the transmission link is not occupied by another input unit, i.e. is free, it is necessary that the input unit from which a transfer is to be carried out must query the transmission link to determine whether it is free or 10 not. In the case of a plurality of input units, to which a plurality of output units are also assigned, the case often arises that several input units wish for a transmission at the same time, but cannot carry it out because of the occupied transmission path and therefore have to wait for it to become free. In order to be able to connect the waiting input units to the transmission link in any order, it is necessary to assign priorities to the individual input units, so that the input unit with the highest priority is connected to the transmission link. In order to be connected to the desired output unit, it is necessary that the input unit in question also delivers the destination address in addition to the information.

Conversely, it can also happen that information is requested from a slave unit from a specific transmitter unit. In this case, a device must be provided in the transmitter unit with which it can determine whether the transmission link is free. Accordingly, a priority sequence must also be provided for the slave units.

3o It can be seen that the structure of the transmitter and receiver units to ensure proper functioning is relatively complicated, since each of them must take into account the condition of the other units. The consequence of this is that the known telecontrol systems are always only suitable for a limited number of input and output units and that an expansion by adding further input and output units is hardly possible, especially as each newly added input and output is added as part of such an expansion Output unit will affect the function of the existing overall system 40.

The aim of the invention is to provide a method and a device for carrying out the same, by means of which or with which any expansion is possible by merely adding input and output units.

According to the invention, this is achieved in that after release by a central unit, the input unit receives control criteria from it via a control bus common to all input units, with which the respective input unit converts the information offered by the encoder into a telegram word that is structured the same for all input units which also contains the destination address, converts the telegram word to a data collection line that is common to all input units when a control criterion “read” is enabled and a control criterion “read” is applied. The telegram word is sent to the input unit when a control criterion “takeover” supplied by the central unit is created takes over for further transmission and feeds the output units or parallel-series converters, 60 the output units or parallel-series converters, when released by the central unit, a separate central unit on the recipient side with a control provided by the latter Criterion "Accept" accept the telegram word for further processing.

Every existing and every newly added input and output unit has access to both the control bus and the data bus. Has an input or output unit registered with the central unit and has been assigned to it

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the release is given, so your information is supplied with the destination, which the delivery of an address in the parallel-series converter to the data collection line. test words obtained from the pending telegram word

As a result of the method, the telecontrol system is not only without intervention in the central unit, which is common to all parallel-series converters, and without influencing the test word bus to the test word inputs of the input function of the overall system by adding new units and 5 units which does this Check word with an easily expandable in the input / output units; Even without a check word obtained from the telegram word influencing the entire system, the input and output units and the result can be configured as desired via the criteria collector line. In this way, a central unit on the encoder side can be fed, which then the central unit either outputs several input and output units as a control criterion “takeover”. A transmission must be connected, whereby the input units with the outputs only take place if there is no malfunction on the part of the encoder, which may be configured as a long-distance line. After the control criterion has been submitted, the data collection line is expediently used as a transmission path in connection with "takeover" and can stand over a manure after the takeover. The outputs of one or acknowledgment query line, the released output unit or several outputs connected to a central unit - the released parallel-serial converter units can also be connected to a long-distance line that asks whether there is a circuit between parallel series - Converter and any distance leads to input units, which in turn has been a data-exchange between serial output converter or between output unit and together with other output units to a separate recipient. Are connected through this central unit. It is not only possible to ascertain whether the relevant information

Advantageously, the encoder-side that was transmitted in the input unit, but also whether the transmission

is converted into digital data in parallel and is free again over 20 lines.

a data collection line on the encoder side to the inputs of an informator supplied to the device between the series-parallel converter or several parallel-series converters and the output unit or between the input unit in serial form and parallel to these parallel-series converters Serial converters can be tested after a standard series-parallel converter, which if the variant of the invention is released before the control criterion is supplied by a central unit on the subscriber side with one of these 25 to "take over" the series-parallel converter or the submitted control criterion "read", the telegram word in the input unit and the output unit or the parallel-serial-parallel form to all converters to serial-to-serial converters, a control criterion "check" is supplied, the common data collection line on the subscriber side, of which the delivery of a from the pending telegram word when it is released by the central unit on the subscriber side d results in the test word obtained at the test word inputs of the zentra unit - a control criterion “takeover” supplied by it, which compares the test words and, if overwritten by the output unit, issues the “takeover” criterion if necessary by means of a further agreement. Data collection line adopted for further processing In order to ensure the proper functioning of the transmission. route can be checked before the control criterion is

This measure ensures that the serial parallel converter or the input

a simple input unit from the central unit on the customer side

Telegraph line is sufficient. Tax criterion «Check» are applied to the levy

Appropriately, before the control criterion “Over- take one in the serial-parallel converter or the input unit except” from the central unit on the transmitter side via a test word obtained from the pending telegram word

Output units or parallel-series converters jointly causes the test word inputs to the output unit to be sent to the same query collecting line, the released output unit 40 which outputs this test word with a test word obtained in the output unit or the released parallel-series converter for the telegram word compares and queries readiness for delivery, whereupon the excess results in the central unit on the recipient side,

Willingness to take these over all output units or an analog test can also be done by:

Parallel-series converters common criteria collectors- the addition of the control criterion “acceptance” of the input

communicated to the central unit and the control criterion 45 unit from the central unit on the transmitter side a control criterion

"Takeover" is fed from the central unit of the output unit terium "Check", which is fed to the delivery of one in the parallel-series converter. Input unit from the test word obtained from the telegram word

This ensures that only then creates a connection or word and check word inputs of the parallel series

Transmission between an input unit and an output converter that supplies this test word with a parallel

unity comes about when the relevant output compares the test word obtained and that is ready for the transfer of the information. Result of the central unit on the encoder side.

According to a further development of the invention, the method for carrying out the method according to the invention is implemented

A large number of known devices are suitable for supplying the “takeover” control criterion, provided that the control steps indicated are possible with a unit from the central unit on the recipient side.

The test device is characterized in that the central on-check word is also provided via a common control collecting line and a through all output units common test word line to the test word inputs common criterion line with the input unit of the series-parallel converter which causes this test word with the output units, the parallel-series converter and one in the series-parallel converter from the telegram word 60 with series-parallel -Converters is connected, the criteria-obtained test word being compared and the result being connected via the bus line to the data inputs of a takeover-criteria line of the subscriber-side central unit memory or a counter, the execution of which is then carried out with the control criterion “takeover” the data inputs of a programmable. On the basis of this measure, a matrix is only connected to the outputs of which the control group transmission is carried out if there is no fault on the recipient side. 65 line is connected.

Advantageously, before the control criterion is fed in. Further details emerge from the drawing,

rium's “takeover” of the parallel series converter from the u. a. some embodiments of the invention are shown

central control unit provides a control criterion «check».

1 shows a basic circuit diagram to explain the method according to the invention,

2 is a detailed illustration of the same;

3 shows a basic circuit diagram of the central unit with an input unit connected to it,

4 shows a variant of the central unit,

5 shows a simplified circuit diagram of a central unit with an input unit connected to it,

6 shows a circuit diagram with input units having AND logic circuits,

7 shows a variant of an input unit,

8 shows a detailed circuit diagram to explain the mode of operation of a device according to the invention, but which is considerably simplified, and

9 shows a program diagram for the example according to FIG. 8. The basic circuit diagram shown in FIG. 1 shows a central unit 1 on the transmitter side and a central unit 2 on the slave side. The three transmitters 3 interact with the central unit 2 on the slave side, each of which over each an input unit 4 are connected to the central unit 1, to which a parallel-serial converter 5 is also connected, from which a transmission link 6 leads to a serial-parallel converter 7, which, like the output units 8, leads to the central station on the subscriber side Unit 2 is connected. The outputs of the output units 8 each lead to a slave 9. For feedback from the slave side to the transmitter side, a parallel-serial converter 10 is connected to the central unit 2 on the slave side, which is connected to a series-parallel converter 12 via a transmission link 11 , which is connected to the central unit 1 on the sensor side. In addition, an output unit 13, which is connected to a slave 14, is connected to the central unit 1. An input unit 16 connected to an encoder 15 is connected to the central unit 2. The information can be transmitted from the input units 4 to one of the output units 8 or 13, from the input unit 16 to one of the output units 13 or 8.

Each of the input units 4, the parallel-to-series converter 5, the series-to-parallel converter 12 and the output unit 13, when released by the central unit 1, receive release lines 17 assigned to them via them, and the output units 8, the input unit 16, of the series Parallel converter 7 and the parallel-series converter 10 when released by the central unit 2 via release lines 18 from the assigned central unit via common control bus lines 19, 20 control criteria, which via common criteria bus lines 21, 22 from the various subunits by the central unit 1 or 2 can be requested. With the help of the control criteria, the released input unit 4 or 16 converts the information offered by the transmitter 3 or 15 into a telegram word structured in the same way for all input units, which not only contains the information but also the destination address, the telegram word when a control criterion is enabled and applied « Reading »a data collection line 23 or 24 is supplied, which takes over the telegram word when inputting a control criterion" takeover "supplied by the central unit 1 or 2 and to the input unit 4 or 16 and to the output unit 13 and the parallel-series converter 5 sets.

If a control criterion “takeover” is supplied by the central unit 1 to the output unit 13, the information transmitted is taken over by it and passed on to the recipient 14, processed accordingly.

Since the information from the encoder 3 converted by the relevant enabled input unit 4 into data present in parallel and located on the data collection line 23 is also present on the parallel-serial converter 5, this in turn takes over when enabled by the central unit 1 and

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A telegram word is present from a control criterion “acceptance” supplied by this during the control criterion “reading” and feeds it in serial form to the series-parallel converter 7. When the serial-to-parallel converter 7 is released by the central unit 2, the latter sends the telegram word in parallel form to the data collection line 24 from a control criterion provided by the central unit 2, from which it is sent after the addressed output unit 8 has been released and after delivery a control criterion “takeover” supplied by the central unit 2 is taken over by the addressed output unit 8 for further processing.

Analogously, a transfer from the input unit 16 via the parallel-serial converter 10, the transmission link 11, the serial-parallel converter 12 to the output unit 13 can also take place.

The basic circuit diagram shown in FIG. 2 is essentially the same as the basic circuit diagram according to FIG. 1, but only input units 4, a parallel-series converter 5 and a series-parallel converter 12 to central unit 1, to central unit 2 only Output units 8, a series-parallel converter 7 and a parallel-series converter 10 are connected. Deviating from the example according to FIG. 1, in the basic circuit diagram according to FIG. 2, each input unit 4 is assigned registration lines 25 which serve to register with the central unit 1, so that an input unit is only released after registration.

In the exemplary embodiment according to FIG. 2, a query collecting line 27 is also provided, via which the released parallel-serial converter 5 or connected output units (13 in FIG. 1) can be queried for readiness for takeover by the central unit 1 before the control criterion “takeover” . An analog polling line can also be provided for the output units 8. If readiness for takeover is given, which is communicated to the assigned central unit via criteria collecting line 21 or 22, the control criterion “takeover” is fed from central unit 1 or 2 to parallel-series converter 5 or output unit 8.

In order to be able to supply a control criterion “test” to the output unit 8 before the control criterion “takeover” is applied, which causes a test word obtained in the output unit 8 from the pending telegram word to be output to test word inputs of the serial-parallel converter 7, a test word collecting line 28 is provided . In the series-parallel converter 7, a test word is also obtained from the telegram word, whereupon both test words are compared with one another. The result is fed via the criteria collecting line 22 to the central unit 2, which then outputs the control criterion “takeover” via the tax collecting line 20.

A check word collecting line 29 is also expediently provided on the encoder side, so that before the control criterion “takeover” is supplied to the parallel series converter 5, a control criterion “check” can be supplied by the central unit 1, which controls the delivery of a parallel series converter -zer 5 of the test word obtained from the pending telegram word is fed via the test word manifold 29 to test word inputs of the input units 4, which compare this test word with a test word obtained from the telegram word in the input unit 4 and feed the result to the central unit 1 via the criterion manifold 21, whereupon this passes the tax criterion “takeover”.

In order to query whether a data exchange has been carried out in the circuit between the parallel-serial converter 5 and the serial-parallel converter 7, an acknowledgment query line 30 is provided, via which, after the control criterion “takeover” has been given and after the takeover has taken place, the released parameter allel series converter 5 issue the relevant receipt

5

5

10th

15

20th

25th

30th

35

40

45

50

55

60

65

616290 D

can. An analog acknowledgment query line 31 is also issued, both the registration unit 41 and the server side being provided, via which the relevant output unit also enables the release unit 38. By 8 the receipt for the delivery of the information to the actuation of the switch 39 of the input unit 4 can be given in a slave 9. Registration memory 59 stores a registration signal, which can also apply to the serial-to-parallel converter 7 or the input units before the respective delivery of the control criterion “over 5 for all further receipts connected to the central unit 1”. In the course of advancing the registration unit 4 and the output unit 8 or the parallel series unit 41, a control criterion “check”, the priority encoder 42, the decoder 43 and the release, will be supplied for the input unit 4 of the highest priority via converter 5 -that the delivery of a test word obtained from the pending telegram word unit 38 via the associated release line 17 to test word inputs of the associated 0 release signal and via the query bus leads to a central unit which compares the test words and 27 queries which controller For the input unit 4, the control criterion “takeover” is only desired if it matches. This is delivered. For this comparison, the data collection line 23 is connected from the input unit 4 to the central unit 1 or 2 via the criteria collection line 21 or 24. communicated to the central unit 1 by the fact that in the example shown in FIG. 2 it is also possible to bring 15 criteria to the take-over memory 32 by the matrix 33 being coded in such a way before the control criterion “take-over” is supplied, that the relevant serial-to-parallel converter 7 is supplied with a control process by the central unit 2 via the control manifold 19 of the control-control criterion “check”, which is fed to the output of a circuit 37 of the input unit 4, in which thereupon in series-parallel - Converter 7 from the telegram word effects the information supplied by the encoder 3 into the test word obtained and test word inputs to the 20 address of the requested (not shown) output input / output unit 8, which converts this test word with a telegram word contained in the unit in parallel form Output unit 8 from the test delta obtained from the telegram word and placed on data collection line 23 t, from which it compares the word and, if necessary, feeds the result to the central unit 2 via parallel series converters and series par. allel converter, transmitted to the called output unit

Finally, before the control criterion is entered, which can be used by the

to take over an input unit 4 from the central central unit.

Unit 1 via the control manifold 19 a control criterion. Fig. 4 shows a variant for the formation of the central «check», which is the delivery of one in the input unit. In this example, the control bus 19 unit 4, the test word obtained from the telegram word, and the query bus 27 are not directly connected to the causes and test word inputs of the parallel-serial conversion 3 ° outputs of the matrix 33, but are fed through an intermediate decoder 5, which feeds them Compares the test word with a test word obtained in the parallel circuit of a query multiplex circuit 44 and a serial converter and feeds the gear multiplex circuit 45, the latter for the delivery of the result to the central unit 1. 3 to explain the interaction of the center line 19. For the criteria line 21, an input data unit 1 with an input unit 4 a basic circuit diagram 35 multiplex circuit 46 is provided. The multiplex circuits are shown in which all the details 44,45,46 which are not essential for the explanation, like the registration unit 41, are omitted from the details. In this example, the zen matrix 33, to which they are connected, is controlled.

central unit 1 a takeover memory 32, for example in this example, the outputs of the input multi-

D flip-flop, or a counter, whose outputs to the tiplex circuit 46 (in Fig. 4 is only one for simplicity

Data inputs of a programmable matrix 33 connected - 40 output shown) to inputs of AND gates 47, 48,

are. Part of the outputs of the matrix 33 is via a 49, the second inputs of which are connected to the outputs of a decoder 50

Feedback bus 34 with data inputs of which are connected to, the inputs of which are connected to a clock generator 35, a take-up memory 51 connected to outputs of the matrix 33 via a bus. The outputs of the AND

32 connected. At further outputs of the matrix 33 there are also gates 48, 49 leading to the take-over memory forming the control bus 19 and a query bus 27 45 flip-flops 52 and 53, which are connected on the one hand via the feedback. The control bus 19 leads to the control bus 34 with the matrix 33, on the other hand with a circuit 37, the query bus 27 are connected to the release switching device 54, the outputs of which are connected to circuits 36 of all input units 4, the inputs of the inputs of the matrix 33 being connected are. The control unit of the input units 4 is connected to an encoder 3. gang of the switching device 54 is connected to the output of the To the outputs of the control circuits 37 on the one hand the so-AND gate 47 ^ to which a further switch-to the take-over memory 32 leading criteria collector device 55 is connected, with which the clock signals of the 21, on the other Data collection line 23 connected. The clock generator 35 can either be connected to the clock inputs of the flip-enable circuit 36 flop 52 connected to the control circuit 37 or to the clock inputs of the flip-flop 53 and can be connected to one of the matrix via an enable line 17.

33 connected release unit 38 connected. 4, the clock signal unit 4 also has a registration switch 39, which, via the switch generator 55 via the switch generator 55, provides a registration line 40 with a likewise from the matrix 33 to the flip-flop 53. The decoder 50, which is programmed by the registration unit 41 of the central unit 1, which can be advanced by the matrix 33, supplies via the AND gate 49 depending on the number of customers. The outputs of the registration unit 41 lead via programming a logical “1” or a logical “0” to the one priority encoder 42 and a decoder 43 for the free & o flip-flop 53, which accordingly activates the matrix 33, from the supply unit 38 the output multiplexing circuit 45 the required

Switched on by the clock generator 35, the control signals and / or to the interrogation multiplex circuit supplies takeover memory 32 to the matrix 33 signals which are supplied via the 44 interrogation signals. The Ummschaltvor feedback bus 34 to the takeover directions 54,55 by an appropriate, from the input 32 are placed. The matrix 33 is now programmed in such a way that the signal supplied by the multiplexing circuit 46 is switched over, so the flip-flop 52 is clocked in the state of readiness for takeover to the control group, which now corresponds to the idle state of the matrix 33 and the program line 19 and the query collecting line 27 of the decoder 50 other signals or criteria characterizing the readiness for takeover to the interrogation multiplexer circuits 44 or the output

7 616290

tiplex circuit 45 delivers. conditions required, such as, but also simplified again, in

In the example according to FIG. 5, the central unit 1 shows FIG. 7 for an input unit in which the AND combination with the matrix 33, which in addition to the clock generator 35, the take-over memory 32 and the enable circuit 36, also has a priority network 56 Impulse line of an enable line 17 and the query collecting line 27 verber 57 and an OR gate 58. The illustrated, to which 5 is bound, with outputs of the AND link of the central unit 1 being connected, has an input unit 4 which has a circuit 36 with the inputs of an AND link logon memory 59, at the input of which the logon switch circuit 75 is connected, at the other inputs-39, and an enable memory 60, the output of which is located at the outputs of a read-only memory 71, in which the two AND gates 61, 62 and via the AND gate 62 are stored to a control criteria which are via leads the criteria collection further AND gate 63. The second input of the AND 10 line 21 can be fed to the central unit. Gate 61 is connected to the control bus 19 and the second Other outputs of the enable circuit lead to the input of the AND gate 62 to the query line 27 of an AND logic circuit 76, at the inclusions of which. From the output of the AND gate 61, the outputs of the control pulses supplied to the matrix 33 connected to the transmitter 3 can be taken from data memory 74. The query pulses via the AND logic switch and the AND gate 62. The data stored in the data collection path of the AND gate 63 can be applied to the second device 76, the line 23 in the criteria memory 64.

stored criteria, which is taken at the output of the AND in FIG. 8 to explain the function of the control signal gate 63 and which would be output via the criteria bus 21 as a function of input units

the takeover memory 32 fed to the central unit 1, control criteria represented a detailed circuit diagram, which become one. 20 central unit 1 and two connected to it

After activation of the registration switch 39, the registration output units 77, 78 have.

The storage memory 32 consists of D flip-flops 79, one of which is supplied via line 65 by the pulse generator 57 and whose outputs are activated on the one hand at inverters 80 and on the other hand with the pulses of the registration memory 59, so there this one outputs of the inverters 80 are connected to a coding circuit constructed from an inverting AND registration signal via the registration line 40 to the priority 25 gates 81, the network 56 thereof and the OR gate 58. The priority networks are led to the rows 82 of the matrix 33. The bridges 84 leading to the work 56 depending on the priority of the registered columns 83, the bridges 84 determining the programming of the matrix 33 th input unit 4 via the associated release line 17 are only shown as far as a release pulse to the release memory 60, which according to this is required for the explanations below. Four feeds of a column 83 of the matrix 33 following the first pulse of the pulse generator 57 are led to inverter 85. The outgoing second pulse is activated via line 66. With two inverting AND gates 85, the inputs of a query pulse via the query line 27 have D inputs of two D flip-flops 79, the outputs of the two are via the AND gate 62 and the input of the other AND gates 85 at one of the inputs one unit 4, the control OR gate 86, 87 stored in the criteria memory 64, the outputs of which are at the D inputs of the criterion via the criteria bus 21, the take-over 35 and two further D flip-flops 79 . The further inputs memory 32 and the requested control signal from the matrix of the OR gates 86, 87 are connected to the outputs of one inverter 33, each via the control bus 19, to the AND gate 61, 88.89, at whose inputs the outputs be led from the exit of which it can be removed. inverting AND gate 90.91 of the units 77.78. In this case, the output of the OR gate 58 to the inverting AND gates 90, 91 form links between the release lines 17, 17 ', the control lines E, and the pulse generator 57 supplied, the F of the control bus 19 and the criteria input line blocks the pulse generator 57 until after the progression of the program X, Y. The AND gate 92 forms links between grammes from the matrix 33 via the line 68 again Release lines 17, 17 'and a control line G. Which will give. Control lines E, F, G are via inverter 92 at three columns

6, 45 of the matrix 33 is connected. The lines leading from the inverting central unit 1 to the inverters 88.89 lead to a release progressing device 69 AND gates 90.91.

on, which can be controlled by the matrix 33 and whose outputs are lines of the criteria collecting line 21.

Via the enable lines 17 to the one inputs of the AND at the outputs a, b, c, d of the D flip-flops 79 and AND gates 70 of the input units 4, which serve to enable, a logical “0”, the top line of the Matrix 33 addresses, the other inputs of which are connected to the query line 27. Accordingly, there is a logical “1” at output A and connected. The outputs of the AND gates 70 lead to fixed outputs A, B, C, D of the inverting AND gates 85 value memories 71, in which those of the input concerned have a logical “0”. If there is a logic unit 4 on the lines J, H required for the desired control program, “0” is saved from the matrix 33 via the two OR gates, control criteria which are released and queried 86, 87 at the D inputs of the Associated flip-flops next to the one input of an AND gate 72, the 55th program step is created, which can be carried out at the next clock pulse, via which, in the present release, the control criterion clock generator 35 to the memory output a = 1, b = 0 , c = 0 and d = 0 rium via the criteria bus 21 to the takeover memory, whereby the row 0001 of the matrix 33 is addressed, rather 32 is supplied. The next step appears at all outputs A, B, C, D Program, those of the matrix 33 obtained at the output of the matrix 33 accordingly become a logical “0” if an AND on the line control signals via the control bus 19 - 60 g6n J and H is still a logical «0». In this gate 73 fed to the released input unit 4, the case, the next clock step at the output of the memory results in the data supplied by the encoder 3 and in a data memory 74 a = 0, b = 0, c = 0, d = 0, which results in the initial state again stored data to the data collection line 23. is posed. In the further course of the clock steps under the

The representations of the device according to the invention. Prerequisite that a legal one on the lines J and H remains considerably "0" in the figures for easier understanding, alternately address 0000 and 0001 to the off

Easy. For the practical implementation of gears a, b, c, d laid.

In step 0000, according to the programming of the AND gate, corresponding AND logic circuits of the matrix 33 are, for example, a logical “0” to the line E,

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8th

given a logical “1” to line F and a logical “0” to line G.

If, for example, the unit 77 is released by a logical “1” on the line 17 and the unit 77 requests a clock pulse with a logical “1” on the line X, a logical “1” appears on the line J in step 0001. In the next clock step, a = 0, b = 0, c = 1 and d = 0 therefore occur at the output of the memory, as a result of which the row 0100 of the matrix 33 is activated. In this step, a clock pulse is offered via line G to unit 77. Lines E, F carry a logical “0”, which means that a logical “0” also appears on line J. At the outputs A, B, C, D the number 1010 occurs, which is offered to the memory as the next step.

At the next clock step, a = 1, b = 0, c = 1, d = 0, which activates row 0101 of matrix 33. A = 0, B = 1, C = 1, D = 0 now appears on lines A, B, C, D.

The symbols at the outputs A, B, C, D, E, F and G show the following truth table for different addresses a, b, c, d:

a b

c d

A

B

c

D

E

F

G

0

0

0

0

0

1

0

0

0

0

1

0

1

1

0

0

0

0

0

0

0

1

0

0

2nd

0

1

0

0

0

0

0

0

0

0

0

3rd

1

1

0

0

0

0

0

0

0

0

0

4th

0

0

1

0

1

0

1

0

0

0

1

5

1

0

1

0

0

1

1

0

0

0

0

6

0

1

1

0

0

0

0

0

0

0

1

7

1

1

1

0

0

0

0

0

0

0

0

8th

0

0

0

1

0

0

0

0

0

0

0

9

1

0

0

1

0

0

0

1

1

0

0

10th

0

1

0

1

0

0

0

0

0

0

0

11

1

1

0

1

0

0

0

0

0

0

0

12

0

0

1

1

1

0

1

0

0

0

1

13

1

0

1

1

0

0

0

1

1

0

0

14

0

1

1

1

0

0

0

0

0

0

0

15

1

1

1

1

0

0

0

0

0

0

0

FIG. 9 shows an example program scheme for the circuit according to FIG. 8.

It can be seen that there is a logical “1” on line J only if Y = 1, E = 1 and the enable with a logical “1” is present. When enabled and a request with X = 1, there is therefore a logical “1” on line J only if E = 1, which is only the case if the address supplied by the transfer memory 79 is the number 1000, 1001 or 1011 is.

Likewise, there is a logical “1” on line H only if Y = 1, F = 1 and the enable with a logical “1” is present. With release and a request Y1, there is therefore a logical “1” on line H only if F = 1, that is to say if the address supplied by the takeover memory 79 is the number 0000.

The query of the inverting AND gates 91 takes place when enabled if the number 0000, that is to say the first address for the matrix 33, is located at the output of the transfer memory. The number 0000 is used to query whether H = 0 or H = 1 or whether for

H = 0 there is a "yes" or "no". In the case of a “yes”, that is to say H = 0, the number 1000 is at the input of the take-over memory 79 with the signals supplied via the outputs A, B, C, D; Number 1001.

With the number 1000, A = B = C = D = 0 and E = 1. There is thus a query as to whether X = 1, which means that the release of the relevant unit 77 or 78 also becomes J = 1. The number 0010 is at the input of the transfer memory, which in the next step A = 1. B = 0, C = 1, D = 0 and G = 1. With G = 1, the AND gate 92 of the unit 77 supplies a clock pulse which can be used for any control in the unit 77. With the number 1010 at the input, the take-over memory 79 delivers a "0" at the next cycle at A, a "1" at B and C and a "0" at D, which leads to G = 1 at the next cycle, outputs A, B, C, D sets to "0" and restores the initial state. If A = 1, B = 0, C = 0 and D = 0, X = 0, so if the answer to the question of whether J = 1 is "no", the next clock step of the transfer memory returns 0000, so that the initial state is established.

If the number 0000 answers the question whether H = 0 with "no", then the number 1001 is placed at the input of the transfer memory because the line F carries a "1" and when the AND gate 91 is released the released unit and with the request Y = 1 there is a “0” at the output of the inverting AND gate and behind the inverter 89, that is to say a “1” on line H. With 1001, A = B = 0 and C = D = 1, F but «0», whereby the logical «1» of line H also becomes a logical «0». However, since D = 1, the OR gate continues to provide a logical «1». Since the output C leads with the line J to the OR gate 86, there is now a query as to whether J = 1 or J = 0. If J = 1, the number 0011 with a clock G = 1 supplies a logical «1» to outputs A, C and D, and a logical «0» to output B. Since C and D have a logical “1”, the signals on lines J and H have no influence on the activation of the transfer memory. The number 1011 not only supplies the clock G = 1 to the AND gate 92 of the released unit, but also assigns a logical “0” to A, B and C, a logical “1” to D, but also a logical one to E. "1". A query is therefore made as to whether J = 1 or not. If J = 1, 0011 returns a cycle with G = 1. Clock pulses thus occur at the output of the relevant AND gate 92 as long as J = 1. If the criterion X = 1 is removed or the release is canceled, then for the next cycle with the address 0001 A = B = C = D = 0, which establishes the initial state.

As can be seen from FIG. 9, the initial state with the address 0000 also occurs if, after the query as to whether H = 0 or not, J = 0, since at this address and J = 0 A = B = C = 0.

This considerably simplified exemplary embodiment shows that the control program delivered to the unit 77 or 78 is entirely dependent on which criteria X, Y are output, it being possible for any number of units to be connected both to the criteria lines 21 and to the control lines 19. Only that unit works that is released via the release lines 17, 17 '.

It can also be seen that in the practical implementation, instead of the gates shown in FIG. 8, corresponding logic circuits with numerous inputs and outputs can occur. The common lines connected to these logic circuits are also available to all input and / or output units in the same way.

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Claims (15)

616290 PATENT CLAIMS 1. A method for telecontrol systems for the transmission of information from one or more sensors to one or more users, in which the information at the output of a sensor is converted into digital data in an input unit and is fed via a transmission link to one or more output units in which it can be converted into the encryption required for the recipient, characterized in that the input unit (4), after being released by a central unit (1), receives control criteria from the central unit (1), which is common to all input units (4), with which the respective input unit (4) converts the information offered by the encoder (3) into a telegram word that has the same structure for all input units (4) and contains the destination address in addition to the information, the telegram word being shared by all input units when a control criterion “reading” is enabled and pending Data collection line (23) added is heard which, when a control criterion "takeover" supplied by the central unit (1) is applied to the input unit (4), takes over the telegram word for further transmission and feeds it to the output units (8,13) or parallel serial converters (5), the output units (8, 13) or the parallel-series converter (5) when released by the central unit (1) or by a separate central unit (2) on the subscriber side with a control criterion "takeover" provided by the latter for further transmission of the telegram word Take over processing. 2nd 2. The method according to claim 1, characterized in that the sensor-side, in the input unit (4) converted into parallel digital data and supplied to the parallel-serial converters (5) in serial form to these parallel-serial converters (5) assigned series-parallel converters (7) is supplied, which, when released by a central unit (2) on the subscriber side, with a control criterion “reading” supplied by it, sends the telegram word in parallel form to a subscriber-side common to all series-parallel converters (7) Place data collection line (24), from which it is taken over by the output unit (8), if necessary, via a further data collection line for further processing when released by the central unit (2) on the subscriber side and a control criterion provided by the latter. 3. The method according to claim 1 or 2, characterized in that before the control criterion "takeover" from the sensor-side central unit (1) via an all output units or parallel series converters (5) common query manifold (27) the released output unit or the released parallel-series converter (5) is queried for readiness for takeover, whereupon the readiness for takeover is communicated to the central unit (1) via a criteria collection line (21) common to all output units or parallel-series converters (5) and that Control criterion "takeover" is fed from the central unit (1) to the output unit or the parallel-series converter (5). 4. The method according to claim 2 or 3, characterized in that before the control criterion "takeover" of the output unit (8) is fed from the central unit (2) on the subscriber side, a control criterion "check" is fed in which the output of a in the output unit ( 8) the test word obtained from the pending telegram word via a test word bus (20), which is also common to all output units (8), to the test word inputs of the series-parallel converter (7), which outputs this test word with a in the series-parallel converter (7) Compare the test word obtained from the telegram word and feed the result via the criteria collecting line (22) to the central unit (2) on the recipient side, which then outputs the control criterion “transfer”. 5 5. The method according to claims 2 or 3, characterized in that before the control criterion “takeover” the parallel-serial converter (5) from the central unit (1) on the sensor side is supplied with a control criterion “check” which is the submission of a in the parallel-to-serial converter (5), the test word obtained from the pending telegram word via a common test word line (29) common to all parallel-to-serial converters (5) to the test word inputs of the input units (4), which this test word with a in the input unit ( 4) Compare the test word obtained from the telegram word and feed the result via the criteria collecting line (21) to the central unit (1) on the transmitter side, which then outputs the control criterion “transfer”. 6. The method according to claim 4 or 5, characterized in that after the delivery of the control criterion "takeover" and the takeover has taken place via an acknowledgment query line (30,31) the released output unit (8) or the released parallel-series converter (5th ) it is queried whether a data exchange has been carried out in the circuit between the parallel-series converter and the series-parallel converter or between the output unit and the slave. 7. The method according to claim 2 or 3, characterized in that before the control criterion "takeover" the series-parallel converter (12.7) or the input unit (4.16) and the output unit (8.13) or the parallel-to-series converter (5, 10) is supplied with a control criterion “test” which causes a test word obtained from the pending telegram word to be sent to the test word inputs of the central unit (1,2), which compares the test words and if they match submits the criterion “takeover”. 8. The method according to claim 2 or 3, characterized in that before the control criterion “takeover” the series-parallel converter (7) or the input unit (16) from the central unit (2) on the subscriber side, a control criterion “check”. is supplied, which causes a test word obtained in the series-parallel converter (7) or the input unit (16) from the pending telegram word to be fed, the test word inputs are fed to the output unit (8), which converts this test word with one in the output unit ( 8) compares the test word obtained from the telegram word and supplies the result to the central unit (2) on the subscriber side. 9. The method according to claim 2 or 3, characterized in that, before the control criterion “takeover” of the input unit (4) is supplied by the central unit (1) on the transmitter side, a control criterion “check” is supplied which enables the output of a control unit in the input unit ( 4) causes the test word obtained from the telegram word and feeds test word inputs to the parallel-series converter (5), which compares this test word with a test word obtained in it and feeds the result to the central unit (1) on the transmitter side. 10th 15 20th 25th 30th 35 40 45 50 55 60 65 616 290 10. Device for carrying out the method according to claim 1, characterized in that the central unit (1, 2) via a common control bus (19, 20) and a common criteria bus (21, 22) with the input units (4, 16), the output units (8,13), the parallel-to-serial converters (5,10) and to the serial-to-parallel converters (7,12), the criteria bus (21,22) being connected to the data inputs of a transfer memory ( 32) or a meter is connected, the outputs of which are connected to the data inputs of a programmable matrix (33), to the outputs of which the control bus (19, 20) is connected. 11. The device according to claim 10, characterized in that outputs of the programmable matrix (33) are connected to data inputs of the transfer memory (32) or the counter. 12. Device according to claim 10 or 11, characterized in that at the outputs of the programmable matrix (33) one to the input units (4, 16), output units (8, 13), parallel-series converters (5, 10) and series - Parallel converters (7, 12) leading query bus (27) is connected. 13. Device according to one of claims 10 to 12, characterized in that in the central unit a registration unit (41) is provided, which is connected via a priority encoder (42) and a decoder (43) to a release unit (38) , which is connected via release lines (17) to the input units (4), output units, parallel-serial converters and serial-parallel converters, both the registration unit (41) and the release unit (38) being connected to outputs of the programmable ones Matrix (33) are connected. 14. Device according to one of claims 10 to 13, characterized in that outputs of the programmable matrix (33) are connected to the take-over memory or counter via a further decoder (50). 15. Device according to one of claims 10 to 14, "characterized in that the transfer memory (32) is divided into two or more sub-memories (52, 53), a switchover device (54, 55) being provided which can be controlled via the criteria collecting line (21) with which the clock generator (35) can be optionally connected to one of the sub-memories (52, 53) and one of the same to the matrix (33).