CH546441A - Verfahren zur herstellung und sperrung von verbindungen zwischen systemeinheiten eines modular aufgebauten programmgesteuerten verarbeitungssystems. - Google Patents

Verfahren zur herstellung und sperrung von verbindungen zwischen systemeinheiten eines modular aufgebauten programmgesteuerten verarbeitungssystems.

Info

Publication number
CH546441A
CH546441A CH328872A CH546441DA CH546441A CH 546441 A CH546441 A CH 546441A CH 328872 A CH328872 A CH 328872A CH 546441D A CH546441D A CH 546441DA CH 546441 A CH546441 A CH 546441A
Authority
CH
Switzerland
Prior art keywords
establishing
controlled processing
processing system
modular program
blocking connections
Prior art date
Application number
CH328872A
Other languages
English (en)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of CH546441A publication Critical patent/CH546441A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Hardware Redundancy (AREA)
  • Selective Calling Equipment (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
CH328872A 1971-04-07 1972-03-07 Verfahren zur herstellung und sperrung von verbindungen zwischen systemeinheiten eines modular aufgebauten programmgesteuerten verarbeitungssystems. CH546441A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19712117128 DE2117128A1 (de) 1971-04-07 1971-04-07 Verfahren zum Ein- und Ausschalten von Systemeinheiten in einem modular aufgebauten Verarbeitungssystem

Publications (1)

Publication Number Publication Date
CH546441A true CH546441A (de) 1974-02-28

Family

ID=5804183

Family Applications (1)

Application Number Title Priority Date Filing Date
CH328872A CH546441A (de) 1971-04-07 1972-03-07 Verfahren zur herstellung und sperrung von verbindungen zwischen systemeinheiten eines modular aufgebauten programmgesteuerten verarbeitungssystems.

Country Status (12)

Country Link
US (1) US3906452A (de)
BE (1) BE781825A (de)
CA (1) CA961984A (de)
CH (1) CH546441A (de)
DE (1) DE2117128A1 (de)
FR (1) FR2133415A5 (de)
GB (1) GB1377165A (de)
IT (1) IT950954B (de)
LU (1) LU65110A1 (de)
NL (1) NL7204544A (de)
SE (1) SE372116B (de)
ZA (1) ZA721527B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE369345B (de) * 1973-10-30 1974-08-19 Ellemtel Utvecklings Ab
US5168555A (en) * 1989-09-06 1992-12-01 Unisys Corporation Initial program load control
EP0457308B1 (de) * 1990-05-18 1997-01-22 Fujitsu Limited Datenverarbeitungssystem mit einem Eingangs-/Ausgangswegetrennmechanismus und Verfahren zur Steuerung des Datenverarbeitungssystems
US5453737A (en) * 1993-10-08 1995-09-26 Adc Telecommunications, Inc. Control and communications apparatus
CN111382101B (zh) * 2018-12-28 2021-06-04 深圳市优必选科技有限公司 一种通信总线电路、通信总线及主从通信系统
US11341407B2 (en) * 2019-02-07 2022-05-24 International Business Machines Corporation Selecting a disconnect from different types of channel disconnects by training a machine learning module

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3200380A (en) * 1961-02-16 1965-08-10 Burroughs Corp Data processing system
US3274561A (en) * 1962-11-30 1966-09-20 Burroughs Corp Data processor input/output control system
US3411139A (en) * 1965-11-26 1968-11-12 Burroughs Corp Modular multi-computing data processing system
US3419852A (en) * 1966-02-14 1968-12-31 Burroughs Corp Input/output control system for electronic computers
US3505648A (en) * 1966-09-28 1970-04-07 Ibm Arithmetic and logic system using ac and dc signals
US3566363A (en) * 1968-07-11 1971-02-23 Ibm Processor to processor communication in a multiprocessor computer system
US3641505A (en) * 1969-06-25 1972-02-08 Bell Telephone Labor Inc Multiprocessor computer adapted for partitioning into a plurality of independently operating systems
US3680052A (en) * 1970-02-20 1972-07-25 Ibm Configuration control of data processing system units
US3651272A (en) * 1970-06-05 1972-03-21 Bell Telephone Labor Inc Program controlled key telephone system for automatically connecting unanswered calls to stations
US3689897A (en) * 1971-01-13 1972-09-05 Burroughs Corp Switching maxtrix control circuit for handling requests on a first-come first-serve priority basis
US3716843A (en) * 1971-12-08 1973-02-13 Sanders Associates Inc Modular signal processor

Also Published As

Publication number Publication date
ZA721527B (en) 1972-11-29
BE781825A (fr) 1972-10-09
IT950954B (it) 1973-06-20
FR2133415A5 (de) 1972-11-24
GB1377165A (en) 1974-12-11
DE2117128A1 (de) 1972-10-19
NL7204544A (de) 1972-10-10
SE372116B (de) 1974-12-09
CA961984A (en) 1975-01-28
LU65110A1 (de) 1972-12-07
US3906452A (en) 1975-09-16

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Legal Events

Date Code Title Description
PL Patent ceased