CH504725A - Rechenwerk - Google Patents

Rechenwerk

Info

Publication number
CH504725A
CH504725A CH804070A CH804070A CH504725A CH 504725 A CH504725 A CH 504725A CH 804070 A CH804070 A CH 804070A CH 804070 A CH804070 A CH 804070A CH 504725 A CH504725 A CH 504725A
Authority
CH
Switzerland
Prior art keywords
arithmetic unit
arithmetic
unit
Prior art date
Application number
CH804070A
Other languages
German (de)
English (en)
Inventor
Simon Mitrofanoff Nicholas
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH504725A publication Critical patent/CH504725A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Executing Machine-Instructions (AREA)
  • Error Detection And Correction (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
  • Detection And Correction Of Errors (AREA)
CH804070A 1969-06-12 1970-05-29 Rechenwerk CH504725A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US83268469A 1969-06-12 1969-06-12

Publications (1)

Publication Number Publication Date
CH504725A true CH504725A (de) 1971-03-15

Family

ID=25262350

Family Applications (1)

Application Number Title Priority Date Filing Date
CH804070A CH504725A (de) 1969-06-12 1970-05-29 Rechenwerk

Country Status (5)

Country Link
US (1) US3596074A (enExample)
JP (1) JPS5126020B1 (enExample)
CH (1) CH504725A (enExample)
FR (1) FR2052351A5 (enExample)
GB (1) GB1279355A (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3711693A (en) * 1971-06-30 1973-01-16 Honeywell Inf Systems Modular bcd and binary arithmetic and logical system
USH1970H1 (en) 1971-07-19 2001-06-05 Texas Instruments Incorporated Variable function programmed system
US4037094A (en) * 1971-08-31 1977-07-19 Texas Instruments Incorporated Multi-functional arithmetic and logical unit
US4503511A (en) * 1971-08-31 1985-03-05 Texas Instruments Incorporated Computing system with multifunctional arithmetic logic unit in single integrated circuit
US3749899A (en) * 1972-06-15 1973-07-31 Hewlett Packard Co Binary/bcd arithmetic logic unit
US3752394A (en) * 1972-07-31 1973-08-14 Ibm Modular arithmetic and logic unit
FR2253415A5 (enExample) * 1973-12-04 1975-06-27 Cii
CH592916B5 (enExample) * 1974-08-19 1977-11-15 Ebauches Sa
US3956620A (en) * 1974-11-26 1976-05-11 Texas Instruments Incorporated Adder with carry enable for bit operations in an electric digital calculator
US3958112A (en) * 1975-05-09 1976-05-18 Honeywell Information Systems, Inc. Current mode binary/bcd arithmetic array
US4125867A (en) * 1976-10-27 1978-11-14 Texas Instruments Incorporated Electronic calculator or microprocessor having a hexadecimal/binary coded decimal arithmetic unit
US4118786A (en) * 1977-01-10 1978-10-03 International Business Machines Corporation Integrated binary-BCD look-ahead adder
JPS53130021U (enExample) * 1977-03-22 1978-10-16
US5964825A (en) * 1996-02-09 1999-10-12 Texas Instruments Incorporated Manipulation of boolean values and conditional operation in a microprocessor
US6374346B1 (en) 1997-01-24 2002-04-16 Texas Instruments Incorporated Processor with conditional execution of every instruction

Also Published As

Publication number Publication date
DE2027179A1 (de) 1971-01-07
GB1279355A (en) 1972-06-28
JPS5126020B1 (enExample) 1976-08-04
US3596074A (en) 1971-07-27
FR2052351A5 (enExample) 1971-04-09
DE2027179B2 (de) 1972-08-24

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Legal Events

Date Code Title Description
PL Patent ceased