CH494591A - Verfahren zur Herstellung von Halbleiterelementen mit bestimmter Lebensdauer der Ladungsträger - Google Patents

Verfahren zur Herstellung von Halbleiterelementen mit bestimmter Lebensdauer der Ladungsträger

Info

Publication number
CH494591A
CH494591A CH543069A CH543069A CH494591A CH 494591 A CH494591 A CH 494591A CH 543069 A CH543069 A CH 543069A CH 543069 A CH543069 A CH 543069A CH 494591 A CH494591 A CH 494591A
Authority
CH
Switzerland
Prior art keywords
production
semiconductor elements
charge carriers
certain lifetime
lifetime
Prior art date
Application number
CH543069A
Other languages
English (en)
Inventor
Erich Dr Weisshaar
Original Assignee
Transistor Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transistor Ag filed Critical Transistor Ag
Priority to CH543069A priority Critical patent/CH494591A/de
Priority to DE19702013224 priority patent/DE2013224A1/de
Priority to GB05869/70A priority patent/GB1274975A/en
Publication of CH494591A publication Critical patent/CH494591A/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)
CH543069A 1969-04-09 1969-04-09 Verfahren zur Herstellung von Halbleiterelementen mit bestimmter Lebensdauer der Ladungsträger CH494591A (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CH543069A CH494591A (de) 1969-04-09 1969-04-09 Verfahren zur Herstellung von Halbleiterelementen mit bestimmter Lebensdauer der Ladungsträger
DE19702013224 DE2013224A1 (de) 1969-04-09 1970-03-19 Verfahren zur Herstellung von Halbleiterelementen mit bestimmter Lebensdauer der Ladungsträger
GB05869/70A GB1274975A (en) 1969-04-09 1970-04-03 Improvements in or relating to semiconductor elements having a definite charge carrier life time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH543069A CH494591A (de) 1969-04-09 1969-04-09 Verfahren zur Herstellung von Halbleiterelementen mit bestimmter Lebensdauer der Ladungsträger

Publications (1)

Publication Number Publication Date
CH494591A true CH494591A (de) 1970-08-15

Family

ID=4293451

Family Applications (1)

Application Number Title Priority Date Filing Date
CH543069A CH494591A (de) 1969-04-09 1969-04-09 Verfahren zur Herstellung von Halbleiterelementen mit bestimmter Lebensdauer der Ladungsträger

Country Status (3)

Country Link
CH (1) CH494591A (de)
DE (1) DE2013224A1 (de)
GB (1) GB1274975A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3929529A (en) * 1974-12-09 1975-12-30 Ibm Method for gettering contaminants in monocrystalline silicon
US4144099A (en) * 1977-10-31 1979-03-13 International Business Machines Corporation High performance silicon wafer and fabrication process
DE3844648C2 (de) * 1987-06-23 1992-02-20 Taiyo Sanso Co. Ltd., Osaka, Jp

Also Published As

Publication number Publication date
GB1274975A (en) 1972-05-17
DE2013224A1 (de) 1970-10-15

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Legal Events

Date Code Title Description
PL Patent ceased