CH482363A - Arrangement for the transmission of information - Google Patents

Arrangement for the transmission of information

Info

Publication number
CH482363A
CH482363A CH811969A CH811969A CH482363A CH 482363 A CH482363 A CH 482363A CH 811969 A CH811969 A CH 811969A CH 811969 A CH811969 A CH 811969A CH 482363 A CH482363 A CH 482363A
Authority
CH
Switzerland
Prior art keywords
arrangement
transmission
information
Prior art date
Application number
CH811969A
Other languages
German (de)
Inventor
Merz Eduard
Original Assignee
Landis & Gyr Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Landis & Gyr Ag filed Critical Landis & Gyr Ag
Priority to CH811969A priority Critical patent/CH482363A/en
Priority to DE19691937646 priority patent/DE1937646B2/en
Priority to NL6912640A priority patent/NL6912640A/xx
Publication of CH482363A publication Critical patent/CH482363A/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
CH811969A 1969-05-29 1969-05-29 Arrangement for the transmission of information CH482363A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CH811969A CH482363A (en) 1969-05-29 1969-05-29 Arrangement for the transmission of information
DE19691937646 DE1937646B2 (en) 1969-05-29 1969-07-21 CIRCUIT ARRANGEMENT FOR THE TRANSMISSION OF BINARY INFORMA TION WORDS WHERE CYCLE SIGNALS ARE SYNCHRONIZED IN A RECEIVING DEVICE WITH THE INCOMING BINARY SIGNALS
NL6912640A NL6912640A (en) 1969-05-29 1969-08-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH811969A CH482363A (en) 1969-05-29 1969-05-29 Arrangement for the transmission of information

Publications (1)

Publication Number Publication Date
CH482363A true CH482363A (en) 1969-11-30

Family

ID=4335474

Family Applications (1)

Application Number Title Priority Date Filing Date
CH811969A CH482363A (en) 1969-05-29 1969-05-29 Arrangement for the transmission of information

Country Status (3)

Country Link
CH (1) CH482363A (en)
DE (1) DE1937646B2 (en)
NL (1) NL6912640A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2902540C2 (en) * 1979-01-24 1983-12-08 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Circuit arrangement for the serial transmission of digital signal blocks

Also Published As

Publication number Publication date
DE1937646A1 (en) 1970-12-10
NL6912640A (en) 1970-12-01
DE1937646B2 (en) 1971-05-13

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Legal Events

Date Code Title Description
PL Patent ceased