CH433825A - Aus Nand-Stufen aufgebauter binärer Volladdierer - Google Patents

Aus Nand-Stufen aufgebauter binärer Volladdierer

Info

Publication number
CH433825A
CH433825A CH117666A CH117666A CH433825A CH 433825 A CH433825 A CH 433825A CH 117666 A CH117666 A CH 117666A CH 117666 A CH117666 A CH 117666A CH 433825 A CH433825 A CH 433825A
Authority
CH
Switzerland
Prior art keywords
full adder
binary full
adder constructed
nand
stages
Prior art date
Application number
CH117666A
Other languages
German (de)
English (en)
Inventor
Jacob Heijn Herman
Slob Arie
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of CH433825A publication Critical patent/CH433825A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CH117666A 1965-01-30 1966-01-28 Aus Nand-Stufen aufgebauter binärer Volladdierer CH433825A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6501243A NL6501243A (US07413550-20080819-C00001.png) 1965-01-30 1965-01-30

Publications (1)

Publication Number Publication Date
CH433825A true CH433825A (de) 1967-04-15

Family

ID=19792238

Family Applications (1)

Application Number Title Priority Date Filing Date
CH117666A CH433825A (de) 1965-01-30 1966-01-28 Aus Nand-Stufen aufgebauter binärer Volladdierer

Country Status (4)

Country Link
BE (1) BE675761A (US07413550-20080819-C00001.png)
CH (1) CH433825A (US07413550-20080819-C00001.png)
GB (1) GB1078269A (US07413550-20080819-C00001.png)
NL (1) NL6501243A (US07413550-20080819-C00001.png)

Also Published As

Publication number Publication date
GB1078269A (en) 1967-08-09
BE675761A (US07413550-20080819-C00001.png) 1966-07-28
NL6501243A (US07413550-20080819-C00001.png) 1966-08-01

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