CH420676A - Multiplikationseinrichtung - Google Patents
MultiplikationseinrichtungInfo
- Publication number
- CH420676A CH420676A CH526163A CH526163A CH420676A CH 420676 A CH420676 A CH 420676A CH 526163 A CH526163 A CH 526163A CH 526163 A CH526163 A CH 526163A CH 420676 A CH420676 A CH 420676A
- Authority
- CH
- Switzerland
- Prior art keywords
- multiplier
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US193472A US3192367A (en) | 1962-05-09 | 1962-05-09 | Fast multiply system |
Publications (1)
Publication Number | Publication Date |
---|---|
CH420676A true CH420676A (de) | 1966-09-15 |
Family
ID=22713784
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH526163A CH420676A (de) | 1962-05-09 | 1963-04-26 | Multiplikationseinrichtung |
Country Status (4)
Country | Link |
---|---|
US (1) | US3192367A (de) |
CH (1) | CH420676A (de) |
DE (1) | DE1202542B (de) |
GB (1) | GB1015175A (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1053147A (de) * | 1963-06-04 | |||
US3730425A (en) * | 1971-05-03 | 1973-05-01 | Honeywell Inf Systems | Binary two{40 s complement multiplier processing two multiplier bits per cycle |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL106122C (de) * | 1953-04-20 | |||
US3069085A (en) * | 1958-04-15 | 1962-12-18 | Ibm | Binary digital multiplier |
-
1962
- 1962-05-09 US US193472A patent/US3192367A/en not_active Expired - Lifetime
-
1963
- 1963-04-18 DE DES84753A patent/DE1202542B/de active Pending
- 1963-04-26 CH CH526163A patent/CH420676A/de unknown
- 1963-04-26 GB GB16449/63A patent/GB1015175A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE1202542B (de) | 1965-10-07 |
US3192367A (en) | 1965-06-29 |
GB1015175A (en) | 1965-12-31 |
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