CH399784A - Addierwerk - Google Patents

Addierwerk

Info

Publication number
CH399784A
CH399784A CH962262A CH962262A CH399784A CH 399784 A CH399784 A CH 399784A CH 962262 A CH962262 A CH 962262A CH 962262 A CH962262 A CH 962262A CH 399784 A CH399784 A CH 399784A
Authority
CH
Switzerland
Prior art keywords
adder
Prior art date
Application number
CH962262A
Other languages
English (en)
Inventor
Francis Schmitt William
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of CH399784A publication Critical patent/CH399784A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4912—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/491—Indexing scheme relating to groups G06F7/491 - G06F7/4917
    • G06F2207/49195—Using pure decimal representation, e.g. 10-valued voltage signal, 1-out-of-10 code

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
CH962262A 1961-08-17 1962-08-10 Addierwerk CH399784A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US132027A US3192369A (en) 1961-08-17 1961-08-17 Parallel adder with fast carry network

Publications (1)

Publication Number Publication Date
CH399784A true CH399784A (de) 1965-09-30

Family

ID=22452111

Family Applications (1)

Application Number Title Priority Date Filing Date
CH962262A CH399784A (de) 1961-08-17 1962-08-10 Addierwerk

Country Status (6)

Country Link
US (1) US3192369A (de)
BE (1) BE621314A (de)
CH (1) CH399784A (de)
DE (1) DE1177379B (de)
GB (1) GB965830A (de)
NL (1) NL282241A (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3480768A (en) * 1966-12-27 1969-11-25 Digital Equipment Corp Digital adder with expedited intrastage carry
US5181186A (en) * 1988-04-13 1993-01-19 Al Ofi Moatad S TPC computers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2879001A (en) * 1956-09-10 1959-03-24 Weinberger Arnold High-speed binary adder having simultaneous carry generation
US2936117A (en) * 1957-05-31 1960-05-10 Bell Telephone Labor Inc High speed switching circuits employing slow acting components
US2966305A (en) * 1957-08-16 1960-12-27 Ibm Simultaneous carry adder
US2981471A (en) * 1957-12-09 1961-04-25 Honeywell Regulator Co Information manipulating apparatus
US2962215A (en) * 1957-12-23 1960-11-29 Ibm Magnetic core circuits
US3055586A (en) * 1958-11-12 1962-09-25 Iuternat Business Machines Cor Digit-by-digit decimal core matrix multiplier

Also Published As

Publication number Publication date
DE1177379B (de) 1964-09-03
BE621314A (de)
GB965830A (en) 1964-08-06
US3192369A (en) 1965-06-29
NL282241A (de)

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