CH348565A - Additionneur binaire - Google Patents

Additionneur binaire

Info

Publication number
CH348565A
CH348565A CH348565DA CH348565A CH 348565 A CH348565 A CH 348565A CH 348565D A CH348565D A CH 348565DA CH 348565 A CH348565 A CH 348565A
Authority
CH
Switzerland
Prior art keywords
binary adder
adder
binary
Prior art date
Application number
Other languages
English (en)
French (fr)
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Publication of CH348565A publication Critical patent/CH348565A/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/502—Half adders; Full adders consisting of two cascaded half adders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Optimization (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
CH348565D 1956-12-03 1957-12-02 Additionneur binaire CH348565A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US625847A US3001711A (en) 1956-12-03 1956-12-03 Transistor adder circuitry

Publications (1)

Publication Number Publication Date
CH348565A true CH348565A (fr) 1960-08-31

Family

ID=24507851

Family Applications (1)

Application Number Title Priority Date Filing Date
CH348565D CH348565A (fr) 1956-12-03 1957-12-02 Additionneur binaire

Country Status (7)

Country Link
US (1) US3001711A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BE (1) BE562896A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CH (1) CH348565A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE1096087B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR1196975A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB844966A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NL (2) NL222924A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3309666A (en) * 1958-10-22 1967-03-14 Ncr Co Transistorized parity bit generating and checking circuit
US3100837A (en) * 1960-08-22 1963-08-13 Rca Corp Adder-subtracter
NL276777A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1961-04-04
US3209132A (en) * 1962-08-28 1965-09-28 Ibm Serial binary adder-subtracter
US3612847A (en) * 1964-04-03 1971-10-12 Saint Gobain Electrical apparatus and method for adding binary numbers
US3466602A (en) * 1966-05-18 1969-09-09 Allen Bradley Co Single error detector for binary information
JPS5531500B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1968-07-03 1980-08-19
US3590230A (en) * 1969-04-03 1971-06-29 Bell Telephone Labor Inc Full adder employing exclusive-nor circuitry
US3651415A (en) * 1970-12-21 1972-03-21 Teletype Corp Bidirectional counter

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2734134A (en) * 1956-02-07 beard
US2629834A (en) * 1951-09-15 1953-02-24 Bell Telephone Labor Inc Gate and trigger circuits employing transistors
US2765115A (en) * 1951-10-30 1956-10-02 Raytheon Mfg Co Arithmetic adders
US2628310A (en) * 1951-12-31 1953-02-10 Ibm Counter circuits
BE520390A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1952-09-30
DE1068486B (de) * 1952-10-09 1959-11-05 International Standard Electric Corporation, N'ew York, N. Y. (V.'St.A.) Schaltungsanordnung für ein vielfach stabiles Register
NL191906A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1953-10-29
BE534549A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1953-12-31
US2852699A (en) * 1955-03-23 1958-09-16 Raytheon Mfg Co Magnetic core gating circuits

Also Published As

Publication number Publication date
US3001711A (en) 1961-09-26
FR1196975A (fr) 1959-11-27
NL222924A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BE562896A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB844966A (en) 1960-08-17
DE1096087B (de) 1960-12-29
NL133227C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

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