CA936925A - Phase locking circuit arrangements - Google Patents

Phase locking circuit arrangements

Info

Publication number
CA936925A
CA936925A CA136385A CA136385A CA936925A CA 936925 A CA936925 A CA 936925A CA 136385 A CA136385 A CA 136385A CA 136385 A CA136385 A CA 136385A CA 936925 A CA936925 A CA 936925A
Authority
CA
Canada
Prior art keywords
circuit arrangements
locking circuit
phase locking
phase
arrangements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA136385A
Other versions
CA136385S (en
Inventor
Taylor Ian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CMC Electronics Inc
Original Assignee
Ian Taylor
Canadian Marconi Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ian Taylor, Canadian Marconi Co filed Critical Ian Taylor
Application granted granted Critical
Publication of CA936925A publication Critical patent/CA936925A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/043—Pseudo-noise [PN] codes variable during transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/241—Testing correct operation using pseudo-errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CA136385A 1971-03-26 1972-03-06 Phase locking circuit arrangements Expired CA936925A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB803371 1971-03-26

Publications (1)

Publication Number Publication Date
CA936925A true CA936925A (en) 1973-11-13

Family

ID=9844486

Family Applications (1)

Application Number Title Priority Date Filing Date
CA136385A Expired CA936925A (en) 1971-03-26 1972-03-06 Phase locking circuit arrangements

Country Status (4)

Country Link
CA (1) CA936925A (en)
DE (1) DE2214946A1 (en)
FR (1) FR2131602A5 (en)
IT (1) IT954534B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3843262C2 (en) * 1988-12-22 1994-04-28 Ant Nachrichtentech Method and circuit arrangement for regulating the phase position of a clock signal
JPH0396015A (en) * 1989-09-08 1991-04-22 Oki Electric Ind Co Ltd High speed digital pll device

Also Published As

Publication number Publication date
FR2131602A5 (en) 1972-11-10
DE2214946A1 (en) 1972-10-12
IT954534B (en) 1973-09-15

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