CA932470A - Controlled pause in data processing apparatus - Google Patents

Controlled pause in data processing apparatus

Info

Publication number
CA932470A
CA932470A CA099440A CA99440A CA932470A CA 932470 A CA932470 A CA 932470A CA 099440 A CA099440 A CA 099440A CA 99440 A CA99440 A CA 99440A CA 932470 A CA932470 A CA 932470A
Authority
CA
Canada
Prior art keywords
processing apparatus
data processing
controlled pause
pause
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA099440A
Other languages
English (en)
Inventor
R. Peters Theodore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Application granted granted Critical
Publication of CA932470A publication Critical patent/CA932470A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Bus Control (AREA)
CA099440A 1970-04-27 1970-11-30 Controlled pause in data processing apparatus Expired CA932470A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3208370A 1970-04-27 1970-04-27

Publications (1)

Publication Number Publication Date
CA932470A true CA932470A (en) 1973-08-21

Family

ID=21863013

Family Applications (1)

Application Number Title Priority Date Filing Date
CA099440A Expired CA932470A (en) 1970-04-27 1970-11-30 Controlled pause in data processing apparatus

Country Status (8)

Country Link
US (1) US3678463A (oth)
BE (1) BE766178A (oth)
CA (1) CA932470A (oth)
DE (1) DE2120289A1 (oth)
FR (1) FR2090746A5 (oth)
GB (1) GB1343072A (oth)
NL (1) NL7105621A (oth)
SE (1) SE364790B (oth)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3898621A (en) * 1973-04-06 1975-08-05 Gte Automatic Electric Lab Inc Data processor system diagnostic arrangement
US3999169A (en) * 1975-01-06 1976-12-21 The United States Of America As Represented By The Secretary Of The Navy Real time control for digital computer utilizing real time clock resident in the central processor
SE387451B (sv) * 1975-07-25 1976-09-06 Ellemtel Utvecklings Ab Tidgivningsanordning for datorer
US4144447A (en) * 1977-04-12 1979-03-13 International Business Machines Corporation Interval timer
JPS5440049A (en) * 1977-09-06 1979-03-28 Toshiba Corp Information process system
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
DE58908047D1 (de) * 1989-04-25 1994-08-18 Siemens Ag Verfahren zur Synchronisation von Datenverarbeitungsanlagen.
US6343363B1 (en) * 1994-09-22 2002-01-29 National Semiconductor Corporation Method of invoking a low power mode in a computer system using a halt instruction
US5987244A (en) * 1994-12-22 1999-11-16 Texas Instruments Incorporated Power management masked clock circuitry, systems and methods
US5771373A (en) * 1994-12-22 1998-06-23 Texas Instruments Incorporated Power management masked clock circuitry, systems and methods
US5754436A (en) * 1994-12-22 1998-05-19 Texas Instruments Incorporated Adaptive power management processes, circuits and systems
US8336762B1 (en) 2008-11-17 2012-12-25 Greenwise Bankcard LLC Payment transaction processing

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3312951A (en) * 1964-05-29 1967-04-04 North American Aviation Inc Multiple computer system with program interrupt
US3333252A (en) * 1965-01-18 1967-07-25 Burroughs Corp Time-dependent priority system
US3408629A (en) * 1966-01-10 1968-10-29 Nielsen A C Co Data handling system
US3541520A (en) * 1967-12-18 1970-11-17 Ibm Time-sharing arrangement
US3611306A (en) * 1969-02-05 1971-10-05 Burroughs Corp Mechanism to control the sequencing of partially ordered instructions in a parallel data processing system
US3611311A (en) * 1969-08-15 1971-10-05 Grason Stadler Co Inc Interface apparatus

Also Published As

Publication number Publication date
US3678463A (en) 1972-07-18
GB1343072A (en) 1974-01-10
NL7105621A (oth) 1971-10-29
BE766178A (fr) 1971-09-16
DE2120289A1 (de) 1971-11-11
FR2090746A5 (oth) 1972-01-14
SE364790B (oth) 1974-03-04

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