CA879961A - Data processing system input-output arrangement - Google Patents

Data processing system input-output arrangement

Info

Publication number
CA879961A
CA879961A CA879961A CA879961DA CA879961A CA 879961 A CA879961 A CA 879961A CA 879961 A CA879961 A CA 879961A CA 879961D A CA879961D A CA 879961DA CA 879961 A CA879961 A CA 879961A
Authority
CA
Canada
Prior art keywords
data processing
processing system
system input
output arrangement
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA879961A
Inventor
T. Butler Thomas
Kenneth P. Kretsch, Sr.
M. Neville Sylvester
George W. Smith, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Publication date
Application granted granted Critical
Publication of CA879961A publication Critical patent/CA879961A/en
Expired legal-status Critical Current

Links

CA879961A Data processing system input-output arrangement Expired CA879961A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA879961T

Publications (1)

Publication Number Publication Date
CA879961A true CA879961A (en) 1971-08-31

Family

ID=36365761

Family Applications (1)

Application Number Title Priority Date Filing Date
CA879961A Expired CA879961A (en) Data processing system input-output arrangement

Country Status (1)

Country Link
CA (1) CA879961A (en)

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