CA3101654A1 - Fixed-admittance modeling and real-time simulation method for power electronic converter - Google Patents
Fixed-admittance modeling and real-time simulation method for power electronic converter Download PDFInfo
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Abstract
A constant-admittance modeling and real-time simulation method for a power electronic converter comprises the following steps of: replacing each of resistor branches, inductor branches, capacitor branches and switch branches in the power electronic converter with a respective equivalent model formed by an equivalent admittance and a historical current source which are connected in parallel, replacing an independent voltage source branch with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, calculating a node admittance matrix of a circuit to be simulated according to the equivalent admittance of each branch, calculating a branch voltage and a branch current of each branch according magnitudes of the historical current sources and the equivalent current source at the current simulation time in combination with the node admittance matrix and the equivalent admittance of each branch, and completing the final simulation. The method prevents changes of the admittance matrix after switching operations and can rapidly attenuate the transient error after the switch operation, so that the problem of virtual power loss of conventional modeling simulation methods in real-time simulation of power electronic converters is solved, thereby greatly improving the precision of simulation.
Description
Description Fixed -Admittance Modeling and Real-Time Simulation Method for Power Electronic Converter Technical Field The invention relates to the technical field of power systems, and specifically relates to a constant-admittance modeling and real-time simulation method for a power electronic converter.
Background Art Electromagnetic transient simulation is an important part of power system simulation. The basic theory and method of power system electromagnetic transient simulation was proposed by H. W.
Dommel, Canada in the late 1960s. For applications of different types, electromagnetic transient simulation can be divided into off-line simulation and real-time simulation.
In general, off-line simulation tools take much longer time for computation than duration time of transient phenomena under research. When facing application scenarios having strict requirements on time, a real-time simulator ensures accurate synchronization of the internal clock of the simulator and the real-world clock through cooperation of software and hardware platforms, and can provide a test environment that closely simulates an actual field for various power system protection and control devices.
As more and more power electronic devices are introduced into power systems, the high-frequency discrete characteristics of power electronic switches offer great challenges for modeling and real-time simulation of power electronic devices. At present, in electromagnetic transient simulation, modeling methods generally used for power electronic switches can be divided into the following two types:
1) two-value resistor modeling, namely using a small resistor as an equivalent of a switch when the switch is turned on, and using a large resistor as an equivalent of the switch when the switch is turned off; and
Background Art Electromagnetic transient simulation is an important part of power system simulation. The basic theory and method of power system electromagnetic transient simulation was proposed by H. W.
Dommel, Canada in the late 1960s. For applications of different types, electromagnetic transient simulation can be divided into off-line simulation and real-time simulation.
In general, off-line simulation tools take much longer time for computation than duration time of transient phenomena under research. When facing application scenarios having strict requirements on time, a real-time simulator ensures accurate synchronization of the internal clock of the simulator and the real-world clock through cooperation of software and hardware platforms, and can provide a test environment that closely simulates an actual field for various power system protection and control devices.
As more and more power electronic devices are introduced into power systems, the high-frequency discrete characteristics of power electronic switches offer great challenges for modeling and real-time simulation of power electronic devices. At present, in electromagnetic transient simulation, modeling methods generally used for power electronic switches can be divided into the following two types:
1) two-value resistor modeling, namely using a small resistor as an equivalent of a switch when the switch is turned on, and using a large resistor as an equivalent of the switch when the switch is turned off; and
2) inductor/capacitor equivalent based constant-admittance modeling, namely using a small inductor as an equivalent of a switch when the switch is turned on, and using a small capacitor as an equivalent of the switch when the switch is turned off;
when binary resistor modeling is used, an abrupt change in the admittance of a switch branch is caused when the state of the switch changes, and the admittance matrix needs to be reformed every time a switching operation occurs, so that the efficiency is low, the real-time requirement cannot be met, and binary resistor modeling is often applied to off-line electromagnetic transient simulation tools, such as PSCAD/EMTDC, Simulink/SimPowerSystem, EMTP series simulation software and the like; and in inductor/capacitor equivalent based constant-admittance modeling, equivalent admittances of small inductors and small capacitors can be equalized through reasonable parameter setting to prevent changes of the admittance matrix caused by switching operations, so that the simulation efficiency is greatly improved, and inductor/capacitor equivalent based constant-admittance modeling is often applied to Small time-step model libraries of RIDS (Real-Time Digital Simulator).
However, due to limitation of physical characteristics of inductors and capacitors, constant-admittance modeling has an obvious transient error after a switching operation occurs, and the power loss of a converter In the real-time simulation is much larger than the actual situation, which greatly influences the precision of simulation, and this phenomenon is called virtual power loss problem.
At present, no description or report of technology similar to the present invention has been found, and no similar information has been collected at home or abroad.
Summary of the Invention To overcome the defects in existing power electronic converter modeling methods, an object of the invention is to provide a constant-admittance modeling and real-time simulation method specifically used for a power electronic converter, and the method prevents changes of an admittance matrix caused by switching operations, and also solves the problem of virtual power loss of conventional modeling simulation methods in real-time simulation of power electronic converters, thereby greatly improving the precision of simulation.
The present invention is realized by the following technical scheme.
A constant-admittance modeling and real-time simulation method for a power electronic converter comprises the following steps of:
Sl, numbering each branch and each node in the power electronic converter and in a circuit where the power electronic converter resides, wherein a grounding node is numbered as 0;
S2, replacing each of resistor branches, inductor branches, capacitor branches and switch branches with a respective equivalent model formed by an equivalent admittance and a history current source which are connected in parallel; replacing an independent voltage source branch with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, and calculating the equivalent admittance of the equivalent model of each branch, wherein the equivalent admittance of the equivalent model of each switch branch is constant in both an on state and an off state;
S3, calculating a node admittance matrix of a circuit to be simulated according to the equivalent
when binary resistor modeling is used, an abrupt change in the admittance of a switch branch is caused when the state of the switch changes, and the admittance matrix needs to be reformed every time a switching operation occurs, so that the efficiency is low, the real-time requirement cannot be met, and binary resistor modeling is often applied to off-line electromagnetic transient simulation tools, such as PSCAD/EMTDC, Simulink/SimPowerSystem, EMTP series simulation software and the like; and in inductor/capacitor equivalent based constant-admittance modeling, equivalent admittances of small inductors and small capacitors can be equalized through reasonable parameter setting to prevent changes of the admittance matrix caused by switching operations, so that the simulation efficiency is greatly improved, and inductor/capacitor equivalent based constant-admittance modeling is often applied to Small time-step model libraries of RIDS (Real-Time Digital Simulator).
However, due to limitation of physical characteristics of inductors and capacitors, constant-admittance modeling has an obvious transient error after a switching operation occurs, and the power loss of a converter In the real-time simulation is much larger than the actual situation, which greatly influences the precision of simulation, and this phenomenon is called virtual power loss problem.
At present, no description or report of technology similar to the present invention has been found, and no similar information has been collected at home or abroad.
Summary of the Invention To overcome the defects in existing power electronic converter modeling methods, an object of the invention is to provide a constant-admittance modeling and real-time simulation method specifically used for a power electronic converter, and the method prevents changes of an admittance matrix caused by switching operations, and also solves the problem of virtual power loss of conventional modeling simulation methods in real-time simulation of power electronic converters, thereby greatly improving the precision of simulation.
The present invention is realized by the following technical scheme.
A constant-admittance modeling and real-time simulation method for a power electronic converter comprises the following steps of:
Sl, numbering each branch and each node in the power electronic converter and in a circuit where the power electronic converter resides, wherein a grounding node is numbered as 0;
S2, replacing each of resistor branches, inductor branches, capacitor branches and switch branches with a respective equivalent model formed by an equivalent admittance and a history current source which are connected in parallel; replacing an independent voltage source branch with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, and calculating the equivalent admittance of the equivalent model of each branch, wherein the equivalent admittance of the equivalent model of each switch branch is constant in both an on state and an off state;
S3, calculating a node admittance matrix of a circuit to be simulated according to the equivalent
3 admittance of each branch;
S4, if a current simulation time t is a simulation initial time, taking magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches as zero, and separately calculating an equivalent current of the independent voltage source branch; and if the current simulation time t is not the simulation initial time, calculating magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches at the current simulation time according to branch voltages and branch currents of the resistor branches, the inductor branches, the capacitor branches and the switch branches at a previous simulation time, and separately calculating the equivalent current of the independent voltage source branch;
S5, calculating an injection current flowing into each node according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
S6, calculating a voltage of each node according to the injection current flowing into each node in combination with the node admittance matrix;
S7, calculating the branch voltage and the branch current of each branch according to the voltage of each node in combination with the equivalent admittance of each branch; and S8, if a final simulation time is not reached, returning to S4, and entering a next simulation time t + At ; otherwise, ending.
Preferably, the equivalent admittance of each branch is calculated according to the following formulae:
Y = ¨
h R
_ the equivalent admittance of each resistor branch is: ; wherein, R
is a resistance of the resistor branch;
At Yh L
the equivalent admittance of each inductor branch is: = L; wherein, L is an inductance of the inductor branch, and At is a time step of real-time simulation;
Yh_r the equivalent admittance of each capacitor branch is: = At;
wherein, C is a capacitance of the capacitor branch;
bsv the equivalent admittance of each switch branch is: ; wherein, Cdc is a Lõ
capacitance of a direct-current side of the power electronic converter, and is an inductance
S4, if a current simulation time t is a simulation initial time, taking magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches as zero, and separately calculating an equivalent current of the independent voltage source branch; and if the current simulation time t is not the simulation initial time, calculating magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches at the current simulation time according to branch voltages and branch currents of the resistor branches, the inductor branches, the capacitor branches and the switch branches at a previous simulation time, and separately calculating the equivalent current of the independent voltage source branch;
S5, calculating an injection current flowing into each node according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
S6, calculating a voltage of each node according to the injection current flowing into each node in combination with the node admittance matrix;
S7, calculating the branch voltage and the branch current of each branch according to the voltage of each node in combination with the equivalent admittance of each branch; and S8, if a final simulation time is not reached, returning to S4, and entering a next simulation time t + At ; otherwise, ending.
Preferably, the equivalent admittance of each branch is calculated according to the following formulae:
Y = ¨
h R
_ the equivalent admittance of each resistor branch is: ; wherein, R
is a resistance of the resistor branch;
At Yh L
the equivalent admittance of each inductor branch is: = L; wherein, L is an inductance of the inductor branch, and At is a time step of real-time simulation;
Yh_r the equivalent admittance of each capacitor branch is: = At;
wherein, C is a capacitance of the capacitor branch;
bsv the equivalent admittance of each switch branch is: ; wherein, Cdc is a Lõ
capacitance of a direct-current side of the power electronic converter, and is an inductance
4 of an alternating-current side of the power electronic converter; and Y = ¨
b _ R
the equivalent admittance of the independent voltage source branch is: ;
wherein is an internal resistance of the independent voltage source branch.
When the power electronic converter is a three-level converter, historical currents and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is: Ih = 0 =
the historical current of each inductor branch is: Ih (t) = L(1 ¨ At) ;
wherein, (t ¨ At) is the branch current of the inductor branch at the previous simulation time;
/b (t) = ¨Yõ cur (t ¨ At) the historical current of each capacitor branch is: -' _ ;
wherein, u (t ¨ At) is the branch voltage of the capacitor branch at the previous simulation time, and Yb-c is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is:
Ih (t) = -5.04Yh (t ¨ iõ, (1¨At) ; and in the off state, the historical current of I (0=hsi sõ,(t 0.39i,õ (1 At) ; wherein u. (t At) n (t ¨ At) i each switch branch is: b-is the branch voltage of the switch branch at the previous simulation time, s the branch current of the switch branch at the previous simulation time, and b-is the equivalent admittance of the switch branch;
(t) (t) = _________________________________________________________ the equivalent current source of the independent voltage source branch is V, wherein, (t) is an internal electric potential of the independent voltage source branch, and R, is the internal resistance of the independent voltage source branch; and when the power electronic converter is a two-level converter, historical currents and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is: /h-R = 0 ;
the historical current of each inductor branch is: Ih --L(t)= i L(1 ¨ At) ;
wherein, i L(1 ¨ is At) .
the branch current of the inductor branch at the previous simulation time;
(t)= ¨Y,, (t ¨At) ;
wherein, _( the historical current of each capacitor branch is: hi u (t ¨At) is the branch voltage of the capacitor branch at the previous simulation time, and 171)-c is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is:
h _sõ,(t) = (-1 -I- NI-27)1u(t ¨ At)¨ (t ¨ At); and in the off state, the historical current of each switch branch is:
h sõ (t) = h ¨At) + (1 (t _At) or, in the on state, the historical current of each switch branch is:
I h õss (t) = (-1¨ -Nii)Yh _,õ,Usõ,(t ¨ At) ¨ sõ (t ¨ At) ;and in the off state, the historical current of each switch branch is:
h sõ,(t)=Yu(t ¨ At)+(1¨..5)isH(t ¨ At) wherein, us,,, (t ¨ At) is the branch voltage of the switch branch at the previous simulation time, (t ¨ At) Y
is the branch current of the switch branch at the previous simulation time, and 6- s is the equivalent admittance of the switch branch; and (t) = (t) s the equivalent current source of the independent voltage source branch is , =
wherein, (t) is an internal electric potential of the independent voltage source branch, and Rs =
is the internal resistance of the independent voltage source branch.
Compared with the prior art, the method provided by the present invention has the following technical effects:
(1) According to the invention, in the power electronic converter, the equivalent admittance of the equivalent model of each switch branch is constant in both the on state and the off state, so that the operation of reforming an admittance matrix due to a change in the switch state in a simulation process is prevented, and therefore the simulation efficiency is guaranteed and real-time requirement can be met.
(2) Compared with conventional inductor/capacitor equivalent based methods, the method provided by the present invention can provide a real-time simulation waveform closer to an ideal switch waveform, and the precision of real-time simulation of the power electronic converter is greatly improved. A converter composed of ideal switches has no virtual power loss, while in conventional inductor/capacitor equivalent based methods, the virtual power loss of the power electronic converter increases along with the increase of switching frequency, as shown in Fig. 3, to an extent of up to 60% or more at 100 kHz, and is greatly not matched with the actual situation.
By using the method provided by the present invention, the virtual power loss of the power electronic converter substantially does not change along with the switching frequency and is always maintained at a level close to zero, and the power electronic converter is closer to a converter composed of ideal switches.
Brief Description of the Drawings Other features, objects and advantages of the present invention will become apparent by taking the following detailed description of non-limiting embodiments with reference to the accompanying drawings in which:
Fig. 1 shows a schematic diagram of an equivalent model of resistor branches, inductor branches, capacitor branches and switch branches according to the present invention;
Fig. 2 shows a current waveform comparison of a constant-admittance modeling and real-time simulation method for a three-level converter according to Embodiment 1 of the present invention;
Fig. 3 shows a voltage waveform comparison of the constant-admittance modeling and real-time simulation method for the three-level converter according to Embodiment 1 of the present invention;
Fig. 4 shows virtual power loss rates under different converter switching frequencies of the constant-admittance modeling and real-time simulation method for the three-level converter according to Embodiment 1 of the present invention;
Fig. 5 shows a circuit diagram of the constant-admittance modeling and real-time simulation method for the three-level converter according to Embodiment 1 of the present invention; wherein, (a) is a circuit diagram of a single-phase three-level converter, (b) is an circuit diagram of a general three-level converter equivalent circuit, and (c) is circuit diagram of a three-level converter constant-admittance equivalent model;
Fig. 6 shows a flow chart of the constant-admittance modeling and real-time simulation method for the three-level converter according to Embodiment 1 of the present invention;
Fig. 7 shows a current waveform comparison of a constant-admittance modeling and real-time simulation method for a two-level converter according to Embodiment 2 of the present invention;
Fig. 8 shows a simple circuit including a single-phase two-level bridge converter; and Fig. 9 shows a flow chart of the constant-admittance modeling and real-time simulation method for the two-level bridge converter according to Embodiment 2 of the present invention.
Detailed Description of the Invention Embodiments of the present invention are described in detail below: the embodiments are implemented based on the technical scheme of the invention, and detailed implementations and specific operation processes are provided. It should be noted that several variations and modifications may be made by those skilled in the art without departing from the spirit of the invention and shall all fall within the scope of the invention.
Embodiment 1: A constant-admittance modeling and real-time simulation method for a three-level converter comprises the following steps that:
Step (1), each branch and each node in the three-level converter and in a circuit where the three-level converter resides are numbered, wherein a grounding node is numbered as 0;
Step (2), each of resistor branches, inductor branches, capacitor branches and switch branches is replaced with a respective equivalent model formed by an equivalent admittance and a historical current source which are connected in parallel, and an independent voltage source branch is replaced with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel; wherein, the equivalent admittance of each branch is calculated according to the following formulae:
Y ¨
h _R R
the equivalent admittance of each resistor branch is wherein, R is an resistance of the resistor branch;
At _ ¨
the equivalent admittance of each inductor branch is wherein, L is an inductance of the inductor branch, and At is a time step of real-time simulation;
Yh C
the equivalent admittance of each capacitor branch is - = At wherein, C is a capacitance of the capacitor branch;
the switch branches, namely the switch branches in the three-level converter, each is replaced with an equivalent model formed by an equivalent admittance and a historical current source which are connected in parallel, and the equivalent admittance of each switch branch is constant in both an on state and an off state, namely the equivalent admittance of each switch branch is v C, II)._ sw \ILa, wherein, C dc is a capacitance of a direct-current side of the three-level converter, and La' is an inductance of an alternating-current side of the three-level converter; and , 1 r = ¨
hys r, the equivalent admittance of the independent voltage source branch is rs-, wherein, Rs. is the internal resistance of the independent voltage source branch;
Step (3), a node admittance matrix of a circuit to be simulated is calculated according to the equivalent admittance of each branch;
Step (4), if a current simulation time t is a simulation initial time, magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches are taken as zero, and an equivalent current of the independent voltage source branch is separately calculated, and if the current simulation time t is not the simulation initial time, magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches at the current simulation time are calculated according to branch voltages and branch currents of the resistor branches, the inductor branches, the capacitor branches and the switch branches at a previous simulation time, and an equivalent current of the independent voltage source branch is separately calculated;
wherein, a historical current of each branch and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is /`'-' = 0 =
' the historical current of each inductor branch is Ih ¨ L (t) = (t ¨ At) wherein, iL (t ¨ At) is the branch current of the inductor branch at the previous simulation time;
/ . the historical current of each capacitor branch is h-( (t)= ¨Yb ( ( 4/ . (t ¨ At) wherein, uc. (t ¨ At) is the branch voltage of the capacitor branch at the previous simulation Y .
time, and l'-( is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is (t) = -5.04Y, õEtc (t ¨ At) ¨ i (t ¨ At) and in the off state, the historical current of each switch branch is h ,õ,(t) Y14(t ¨ 0 .39i ,õ (t ¨At) usõ, (t ¨ At) .
wherein, is the branch voltage of the switch branch at the previous simulation time, i. (t ¨ At) Y
is the branch current of the switch branch at the previous simulation time, and h -s is the equivalent admittance of the switch branch;
(t)= (t) the equivalent current source of the independent voltage source branch is wherein, vs (t) is an internal electric potential of the independent voltage source branch, and Rs is the internal resistance of the independent voltage source branch;
Step (5), an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
Step (6), a voltage of each node is calculated according to the injection current flowing into each node in combination with the node admittance matrix;
Step (7), the branch voltage and the branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of the equivalent model of each branch; and Step (8), if a final simulation time is not reached, the process returns to Step (4) and enters a next simulation time t + At; otherwise, the process is ended.
In order to facilitate understanding, the above embodiment of the present invention will be further explained below with reference to a simple circuit of a single-phase three-level converter as shown in Fig. 5 as a specific application example, but the scope of the present invention should not be limited thereby.
In the specific realization of real-time simulation of the three-level converter, the following hardware platforms are adopted in this specific application example: a PXIe-8135 (a PXIe controller) and a PXIe-7975R (an FPGA module) of the National Instruments (NI) Corporation are separately installed in a PXIe chassis, the PXIe controller is mainly responsible for simulation of a converter control system, the FPGA module is mainly responsible for simulation of circuit parts of the three-level converter, and communication between the PXIe controller and the FPGA module is achieved through a PXIe bus. In addition, the PXIe controller can also communicate with an upper computer through Ethernet such that real-time simulation waveforms are displayed on the upper computer, and the FPGA module can be connected with an external controller and an oscilloscope through I/O ports to perform hardware-in-loop simulation.
Programs in the upper computer, the PXIe controller and the FPGA module are all programmed in a LabVIEW development environment of the National Instruments (NI) Corporation. Through Labview programming, the programs in the host computer perform functions of communicating with the PXIe controller, displaying the simulation waveforms, etc.; and the programs in the PXIe controller perform functions of communicating with the upper computer, reading data from and writing data into the FPGA module, simulating the control system of the converter, etc. The above-described programs do not fall within the scope of the present invention, and relevant program examples are available on the official website of the National Instruments (NI) Corporation, therefore the programs will not be described in detail here.
However, the FPGA
module is the specific implementation carrier of the invention and is programmed through Labview, referring to Fig. 5 which is a circuit diagram of a constant-admittance modeling and real-time simulation method for a single-phase three-level converter according to this specific application example.
The constant-admittance modeling and real-time simulation method for the single-phase three-level converter according to the specific application example comprises the following steps that:
(1) each branch and each node in the three-level converter and in a circuit where the three-level converter resides are numbered, as shown in Fig. 5b;
(2) each of resistor branches, inductor branches, capacitor branches and switch branches is replaced with a respective equivalent model (as shown in Fig. 1) formed by an equivalent admittance and a historical current source which are connected in parallel, and an independent voltage source branch is replaced with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, wherein a simulation step is taken as 1,us , and the equivalent admittance of each branch is as follows:
= ¨1=10S2-1 branch 1 (independent voltage source branch) 0.1 branch 2 (capacitor branch) Y.d, = 2e ¨3 = 2000 SY' le ¨ 6 branch 3 (capacitor branch) Y = 2e ¨3 = 2000 b de 2 le ¨ 6 branch 4 (switch branch) Y = .\/ 2e ¨3 = 0.2Q-1 50e-3 branch 5 (switch branch) Y , = 2e ¨3 = 0.2 SI
50e ¨3 branch 6 (switch branch) Y1, 3 = _______ = 0.2Q' 50e ¨3 branch 7 (inductor branch) = le -6 = 2e ¨ 4 - 50e-3 Y R = ¨1=0.10-1 h_ branch 8 (resistor branch) .. 10 and the calculated value of the equivalent admittance of each branch is also marked in Fig. 5b;
(3) a node admittance matrix Yr, of a circuit to be simulated is calculated according to the equivalent admittance of each branch 2010.2 ¨10 ¨0.2 0 ¨10 2010.2 ¨0.2 0 =
¨0.2 ¨0.2 0.6002 ¨2e-4 0 0 ¨2e-4 0.1002 (4.0) if a current simulation time t = 0 ,us is a simulation initial time, magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches are taken as zero, and an equivalent current of the independent voltage source branch is separately calculated, i.e.:
= ¨750=7500 A
branch 1 (independent voltage source branch) - 0.1 branch 2 (capacitor branch) Ih_C <lc I OA
branch 3 (capacitor branch) = 0 A
branch 4 (turned-off switch branch) ./õ_ = 0 A
branch 5 (turned-off switch branch) //,_ õ, 2 = 0 A
branch 6 (turned-on switch branch) / = 0 A
branch 7 (inductor branch) Ih = OA
=OAIh_R
branch 8 (resistor branch) (5.0) an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time (an inflow current is positive and an outflow current is negative):
injection current of node I1 =7500A
injection current of node 2 2 = ¨7500 A
injection current of node 3 /õ, = OA
injection current of node 4 /õ4 = 0 A
(6.0) a voltage of each node is calculated according to a node voltage equation YV = I. with the injection current, which has been given, flowing into each node in combination with the node admittance matrix:
V =3.7125V
voltage of node 1 ni voltage of node 2 Vn, = ¨3.7125 V
voltage of node 3 Vn, = 0 V
voltage of node 4 Vn4 = 0 V
(7.0) a branch voltage and a branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of each branch:
V = 7.4250 V I = 7.4257e3A
branch 1 (independent voltage source branch) hi' h Vs branch 2 (capacitor branch) V. = 3.7125 V, //, = 7.4250e3 A
branch 3 (capacitor branch) Võ = 3.7125 V, , = 7.4250e3 A
branch 4 (switch branch) V = 3.7125 V, / = 0.7425 A
h _ma I b branch 5 (switch branch) V, = 3.7125 V, / = 0.7425 A
branch 6 (switch branch) V = 0 V, I, -- 0 A
h _ nr3 branch 7 (inductor branch) V; = 0 V, I h = OA
branch 8 (resistor branch) Vh_ õ = 0 V, I h =OA
t (8.0) if the current simulation time = 0 ,us does not reach a final simulation time, the process returns to the step (4.0) and enters a next simulation time t = 1 ;
t =1 ,us the process enters the next simulation time i i (4.1) if the current simulation time t = 1 ds s not the simulation initial time, a magnitude of the historical current source of each branch at the current simulation time is calculated according to the branch voltage and the branch current of each branch at the previous simulation time, wherein a historical current of each branch and an equivalent current are calculated according to the following formulae:
/ = 750 =7500A
branch 1 (independent voltage source branch) 0.1 branch 2 (capacitor branch) /hi, = -7.4250e3 A
branch 3 (capacitor branch) I _cae, = -7.4250e3 A
branch 4 (turned-off switch branch) I, ,õ,,= -0.4529A
branch 5 (turned-off switch branch) I, õ, 2 = -0.4529 A
branch 6 (turned-on switch branch) /õ_,,,3 = 0 A
branch 7 (inductor branch) Iõ_,= 0 A
branch 8 (resistor branch) /h-8 =OA
(5.1) an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
injection current of node 1 /õ' = 1.4925e4 A
injection current of node 2 Iõ2 = ¨1.4925e4 A
injection current of node 3 /õ3 = OA
injection current of node 4 L, = OA
(6.1) a voltage of each node is calculated according to the injection current flowing into each node in combination with the node admittance matrix;
voltage of node 1 V =7.3881V
voltage of node 2 V,õ ¨7.3881V
voltage of node 3 Võ3 =3.6998e-16V
voltage of node 4 Vu4 = 7.3847e-19V
(7.1) the branch voltage and the branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of each branch;
V =14.7762 V / = 7.3522e3 A
branch 1 (independent voltage source branch) hi' h branch 2 (capacitor branch) Võ , = 7.3881V, = 7.3512e3 A
branch 3 (capacitor branch) Vh_cd = 7.3881V, kcae, ,, = 7.3512e3 A
branch 4 (switch branch) V, = 7.388 1V, /,, = 1.0247 A
branch 5 (switch branch) V, 0,2 = 7.3881V, /h , =1.0247 A
_ 141 branch 6 (switch branch) V = 3 .6998e-16 V, /,_ ,w3 = 7 .3995e-17 A
branch 7 (inductor branch) V = 3.6924e-16 V, = 7.3847e-20A
branch 8 (resistor branch) V, = 7.3847e-19 V, /, = 7.3847e-20 A
(8.1) if the current simulation time t = 1,us does not reach a final simulation time, the process returns to the step (4.1) and enters a next simulation time t = 21us;
the process enters the next simulation time t = 2 ,us :
(4.2) if the current simulation time t = 2 ps is not the simulation initial time, the magnitude of the historical current source of each branch and the equivalent current at the current simulation time are calculated according to the branch voltage and the branch current of each branch at the previous simulation time...; this step is as same as the aforementioned step and therefore will not be repeated here; and steps (4)-(8) are repeated as above until the final simulation time is reached, and then the simulation program is ended.
Implementation results are shown in Figs. 2, 3 and 4, wherein Fig. 2 and Fig.
3 show comparisons between results of the method provided by the above embodiment of the present invention and a conventional real-time simulation method, and Fig. 4 shows virtual power loss rates under different converter switching frequencies of the two methods. As shown in Fig.
2 and Fig. 3, the real-time simulation waveform obtained by using the method provided by the embodiment of the invention is closer to an ideal switching waveform than the conventional inductor/capacitor equivalent based method, and the precision of real-time simulation of the three-level converter is greatly improved. A converter composed of ideal switches has no virtual power loss, while in conventional inductor/capacitor equivalent based methods, the virtual power loss of the three-level converter increases along with the increase of switching frequency, as shown in Fig. 4, to an extent of up to 60% or more at 100 kHz, and is greatly not matched with the actual situation. By using the method provided by the present invention, the virtual power loss of the three-level converter substantially does not change along with the switching frequency and is always maintained at a level close to zero, and the three-level converter is closer to the converter composed of ideal switches.
Embodiment 2: A constant-admittance modeling and real-time simulation method for a two-level converter comprises the following steps that:
(1) each branch and each node in the two-level bridge converter and in a circuit where the two-level bridge converter resides are numbered, as shown in Fig. 8;
(2) each of resistor branches, inductor branches, capacitor branches and switch branches is replaced with a respective equivalent model (as shown in Fig. 1) formed by an equivalent admittance and a historical current source which are connected in parallel, and an independent voltage source branch is replaced with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, wherein a simulation step is taken as 1,us , and the equivalent admittance of each branch is as follows:
branch 1 (independent voltage source branch) - 0.1 2e-3 = 2000 SY' branch 2 (capacitor branch) - le ¨6 2e ¨3 Yh (k2 = =2000' branch 3 (capacitor branch) le ¨6 \I 2e-3 Y = _____ = 0.2 Sr' h +id branch 4 (switch branch) 50e ¨3 \I Y
w2 2e-3 h s branch 5 (switch branch) 50e ¨3 le-6 Y bL = 50e ¨3 = 2e ¨ 4 Sr' branch 6 (inductor branch) Y = 1 h-" 10 branch 7 (resistor branch) and the calculated value of the equivalent admittance of each branch is also marked in Fig. 8b;
(3) a node admittance matrix Y. of the circuit to be simulated is calculated according to the equivalent admittance of each branch 2010.2 ¨10 ¨0.2 0 ¨10 2010.2 ¨0.2 0 Y. =
¨0.2 ¨0.2 0.4002 ¨2e-4 0 0 ¨2e-4 0.1002 (4.0) if a current simulation time t = 0 ps is a simulation initial time, magnitudes of the historical current sources of all the branches are taken as zero, and an equivalent current of the independent voltage source branch is separately calculated, i.e.:
I. = 750 =7500A
branch 1 (independent voltage source branch) 0.1 branch 2 (capacitor branch) /õ. = OA
branch 3 (capacitor branch) 'h (k' = 0 A
branch 4 (switch branch) 'h = 0 A
branch 5 (switch branch) /h_ 2 = 0 A
branch 6 (inductor branch) 1.,J, = 0 A
/h =OA
branch 7 (resistor branch) (5.0) an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time (an inflow current is positive and an outflow current is negative):
injection current of node 1 in = 7500 A
= ¨7500 A
injection current of node 2 -injection current of node 3 1,3 = OA
injection current of node 4 /n4 = OA
(6.0) a voltage of each node is calculated according to a node voltage equation YõVõ = Iõ with the injection current, which has been given, flowing into each node in combination with the node admittance matrix:
voltage of node 1 Vn = 3.7125 V
voltage of node 2 Vn2 = ¨3.7125 V
voltage of node 3 0= V Vn3 0= voltage of node 4 V V n4 (7.0) a branch voltage and a branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of each branch:
branch 1 (independent voltage source branch) V = 7.4250 V / = 7.4257e3 A h V = 3 .7 125V'1 Cdcl = 7.4250e3 A
branch 2 (capacitor branch) h -c""
Vb_(Vc2 = 3.7125 V / = 7.4250e3 A
branch 3 (capacitor branch) h (Vc.1 - -V = 3.7125 V, /,, = 0.7425 A
branch 4 (switch branch) b_ _ V = 3.7125 V / = 0.7425 A
branch 5 (switch branch) h _ vw2 b sly"
-Lac branch 6 (inductor branch) Vb -1""µ = 0 V /h = 0 A
branch 7 (resistor branch) Vb -R = 0 V' Ih R = OA
(8.0) if the current simulation time t Ps does not reach a final simulation time, the process returns to the step (4) and enters a next simulation time t = 1,us ;
(4.1) if the current simulation time t = 1 Ps is not the simulation initial time, a magnitude of the historical current source of each branch at the current simulation time is calculated according to the branch voltage and the branch current of each branch at the previous simulation time, wherein historical currents of various branches are calculated according to the following formulae:
Is is = =7500 A
branch 1 (independent voltage source branch) - 0.1 branch 2 (capacitor branch) Ih _(õk I = -7.4250e3 A
branch 3 (capacitor branch) Ih _Cdc 2 = -7.4250e3 A
branch 4 (turned-on switch branch) Ih_ su = 2.5351A
branch 5 (turned-off switch branch) /fi - "92 = -0.4349 A
branch 6 (inductor branch) lb -L = 0 A
h _R = 0 A
branch 7 (resistor branch) (5.1) an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
injection current of node 1 Ini = 1.4922e4 A
injection current of node 2 /n2 = ¨1.4925e4 A
injection current of node 3 In3 = 2.9700A
injection current of node 4 In4 = 0 A
(6.1) a voltage of each node is calculated according to the injection current flowing into each node in combination with the node admittance matrix;
voltage of node 1 VnI = 7.3874 V
Vn2 =-7.3874V
voltage of node 2 voltage of node 3 V"3 =7.4213V
voltage of node 4 V" =0.0148V =
(7.1) the branch voltage and the branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of each branch;
V branch 1 (independent voltage source branch) hi' =14.7747 V/ h ¨ 73523e3 A
I"µ ¨ =
h = 7.3 874 V / = 7 .3497e3 A
branch 2 (capacitor branch) V h Cdcl V = 7.3874 V, Ib _CU:2 7.3497e3 A
branch 3 (capacitor branch) V = -0.0339 V / =2.5283A
branch 4 (switch branch) b I h µµ.
V = 14.8087 V / 2 5268 A
branch 5 (switch branch) b _ sw 2 is 2 ¨ -ac 0 .0015 A
branch 6 (inductor branch) V h _La = 7 .4065 V, 'h c V =0.0148V / =0.0015A
branch 7 (resistor branch) b -R b _R
(8.1) if the current simulation time t = 1,us does not reach a final simulation time, the process returns to the step (4) and enters a next simulation time t = 2 ,us;
(4.2) if the current simulation time t = 2 ,us is not the simulation initial time, the magnitude of the historical current source of each branch at the current simulation time is calculated according to the branch voltage and the branch current of each branch at the previous simulation time...; and steps (4)-(8) are repeated as above until the final simulation time is reached, and then the simulation program is ended.
Specific embodiments of the invention have been described above. It is to be understood that the invention is not limited to the particular implementations described above, and that various changes and modifications may be made by those skilled in the art within the scope of the appended claims without influencing the essence contents of the invention.
b _ R
the equivalent admittance of the independent voltage source branch is: ;
wherein is an internal resistance of the independent voltage source branch.
When the power electronic converter is a three-level converter, historical currents and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is: Ih = 0 =
the historical current of each inductor branch is: Ih (t) = L(1 ¨ At) ;
wherein, (t ¨ At) is the branch current of the inductor branch at the previous simulation time;
/b (t) = ¨Yõ cur (t ¨ At) the historical current of each capacitor branch is: -' _ ;
wherein, u (t ¨ At) is the branch voltage of the capacitor branch at the previous simulation time, and Yb-c is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is:
Ih (t) = -5.04Yh (t ¨ iõ, (1¨At) ; and in the off state, the historical current of I (0=hsi sõ,(t 0.39i,õ (1 At) ; wherein u. (t At) n (t ¨ At) i each switch branch is: b-is the branch voltage of the switch branch at the previous simulation time, s the branch current of the switch branch at the previous simulation time, and b-is the equivalent admittance of the switch branch;
(t) (t) = _________________________________________________________ the equivalent current source of the independent voltage source branch is V, wherein, (t) is an internal electric potential of the independent voltage source branch, and R, is the internal resistance of the independent voltage source branch; and when the power electronic converter is a two-level converter, historical currents and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is: /h-R = 0 ;
the historical current of each inductor branch is: Ih --L(t)= i L(1 ¨ At) ;
wherein, i L(1 ¨ is At) .
the branch current of the inductor branch at the previous simulation time;
(t)= ¨Y,, (t ¨At) ;
wherein, _( the historical current of each capacitor branch is: hi u (t ¨At) is the branch voltage of the capacitor branch at the previous simulation time, and 171)-c is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is:
h _sõ,(t) = (-1 -I- NI-27)1u(t ¨ At)¨ (t ¨ At); and in the off state, the historical current of each switch branch is:
h sõ (t) = h ¨At) + (1 (t _At) or, in the on state, the historical current of each switch branch is:
I h õss (t) = (-1¨ -Nii)Yh _,õ,Usõ,(t ¨ At) ¨ sõ (t ¨ At) ;and in the off state, the historical current of each switch branch is:
h sõ,(t)=Yu(t ¨ At)+(1¨..5)isH(t ¨ At) wherein, us,,, (t ¨ At) is the branch voltage of the switch branch at the previous simulation time, (t ¨ At) Y
is the branch current of the switch branch at the previous simulation time, and 6- s is the equivalent admittance of the switch branch; and (t) = (t) s the equivalent current source of the independent voltage source branch is , =
wherein, (t) is an internal electric potential of the independent voltage source branch, and Rs =
is the internal resistance of the independent voltage source branch.
Compared with the prior art, the method provided by the present invention has the following technical effects:
(1) According to the invention, in the power electronic converter, the equivalent admittance of the equivalent model of each switch branch is constant in both the on state and the off state, so that the operation of reforming an admittance matrix due to a change in the switch state in a simulation process is prevented, and therefore the simulation efficiency is guaranteed and real-time requirement can be met.
(2) Compared with conventional inductor/capacitor equivalent based methods, the method provided by the present invention can provide a real-time simulation waveform closer to an ideal switch waveform, and the precision of real-time simulation of the power electronic converter is greatly improved. A converter composed of ideal switches has no virtual power loss, while in conventional inductor/capacitor equivalent based methods, the virtual power loss of the power electronic converter increases along with the increase of switching frequency, as shown in Fig. 3, to an extent of up to 60% or more at 100 kHz, and is greatly not matched with the actual situation.
By using the method provided by the present invention, the virtual power loss of the power electronic converter substantially does not change along with the switching frequency and is always maintained at a level close to zero, and the power electronic converter is closer to a converter composed of ideal switches.
Brief Description of the Drawings Other features, objects and advantages of the present invention will become apparent by taking the following detailed description of non-limiting embodiments with reference to the accompanying drawings in which:
Fig. 1 shows a schematic diagram of an equivalent model of resistor branches, inductor branches, capacitor branches and switch branches according to the present invention;
Fig. 2 shows a current waveform comparison of a constant-admittance modeling and real-time simulation method for a three-level converter according to Embodiment 1 of the present invention;
Fig. 3 shows a voltage waveform comparison of the constant-admittance modeling and real-time simulation method for the three-level converter according to Embodiment 1 of the present invention;
Fig. 4 shows virtual power loss rates under different converter switching frequencies of the constant-admittance modeling and real-time simulation method for the three-level converter according to Embodiment 1 of the present invention;
Fig. 5 shows a circuit diagram of the constant-admittance modeling and real-time simulation method for the three-level converter according to Embodiment 1 of the present invention; wherein, (a) is a circuit diagram of a single-phase three-level converter, (b) is an circuit diagram of a general three-level converter equivalent circuit, and (c) is circuit diagram of a three-level converter constant-admittance equivalent model;
Fig. 6 shows a flow chart of the constant-admittance modeling and real-time simulation method for the three-level converter according to Embodiment 1 of the present invention;
Fig. 7 shows a current waveform comparison of a constant-admittance modeling and real-time simulation method for a two-level converter according to Embodiment 2 of the present invention;
Fig. 8 shows a simple circuit including a single-phase two-level bridge converter; and Fig. 9 shows a flow chart of the constant-admittance modeling and real-time simulation method for the two-level bridge converter according to Embodiment 2 of the present invention.
Detailed Description of the Invention Embodiments of the present invention are described in detail below: the embodiments are implemented based on the technical scheme of the invention, and detailed implementations and specific operation processes are provided. It should be noted that several variations and modifications may be made by those skilled in the art without departing from the spirit of the invention and shall all fall within the scope of the invention.
Embodiment 1: A constant-admittance modeling and real-time simulation method for a three-level converter comprises the following steps that:
Step (1), each branch and each node in the three-level converter and in a circuit where the three-level converter resides are numbered, wherein a grounding node is numbered as 0;
Step (2), each of resistor branches, inductor branches, capacitor branches and switch branches is replaced with a respective equivalent model formed by an equivalent admittance and a historical current source which are connected in parallel, and an independent voltage source branch is replaced with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel; wherein, the equivalent admittance of each branch is calculated according to the following formulae:
Y ¨
h _R R
the equivalent admittance of each resistor branch is wherein, R is an resistance of the resistor branch;
At _ ¨
the equivalent admittance of each inductor branch is wherein, L is an inductance of the inductor branch, and At is a time step of real-time simulation;
Yh C
the equivalent admittance of each capacitor branch is - = At wherein, C is a capacitance of the capacitor branch;
the switch branches, namely the switch branches in the three-level converter, each is replaced with an equivalent model formed by an equivalent admittance and a historical current source which are connected in parallel, and the equivalent admittance of each switch branch is constant in both an on state and an off state, namely the equivalent admittance of each switch branch is v C, II)._ sw \ILa, wherein, C dc is a capacitance of a direct-current side of the three-level converter, and La' is an inductance of an alternating-current side of the three-level converter; and , 1 r = ¨
hys r, the equivalent admittance of the independent voltage source branch is rs-, wherein, Rs. is the internal resistance of the independent voltage source branch;
Step (3), a node admittance matrix of a circuit to be simulated is calculated according to the equivalent admittance of each branch;
Step (4), if a current simulation time t is a simulation initial time, magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches are taken as zero, and an equivalent current of the independent voltage source branch is separately calculated, and if the current simulation time t is not the simulation initial time, magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches at the current simulation time are calculated according to branch voltages and branch currents of the resistor branches, the inductor branches, the capacitor branches and the switch branches at a previous simulation time, and an equivalent current of the independent voltage source branch is separately calculated;
wherein, a historical current of each branch and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is /`'-' = 0 =
' the historical current of each inductor branch is Ih ¨ L (t) = (t ¨ At) wherein, iL (t ¨ At) is the branch current of the inductor branch at the previous simulation time;
/ . the historical current of each capacitor branch is h-( (t)= ¨Yb ( ( 4/ . (t ¨ At) wherein, uc. (t ¨ At) is the branch voltage of the capacitor branch at the previous simulation Y .
time, and l'-( is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is (t) = -5.04Y, õEtc (t ¨ At) ¨ i (t ¨ At) and in the off state, the historical current of each switch branch is h ,õ,(t) Y14(t ¨ 0 .39i ,õ (t ¨At) usõ, (t ¨ At) .
wherein, is the branch voltage of the switch branch at the previous simulation time, i. (t ¨ At) Y
is the branch current of the switch branch at the previous simulation time, and h -s is the equivalent admittance of the switch branch;
(t)= (t) the equivalent current source of the independent voltage source branch is wherein, vs (t) is an internal electric potential of the independent voltage source branch, and Rs is the internal resistance of the independent voltage source branch;
Step (5), an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
Step (6), a voltage of each node is calculated according to the injection current flowing into each node in combination with the node admittance matrix;
Step (7), the branch voltage and the branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of the equivalent model of each branch; and Step (8), if a final simulation time is not reached, the process returns to Step (4) and enters a next simulation time t + At; otherwise, the process is ended.
In order to facilitate understanding, the above embodiment of the present invention will be further explained below with reference to a simple circuit of a single-phase three-level converter as shown in Fig. 5 as a specific application example, but the scope of the present invention should not be limited thereby.
In the specific realization of real-time simulation of the three-level converter, the following hardware platforms are adopted in this specific application example: a PXIe-8135 (a PXIe controller) and a PXIe-7975R (an FPGA module) of the National Instruments (NI) Corporation are separately installed in a PXIe chassis, the PXIe controller is mainly responsible for simulation of a converter control system, the FPGA module is mainly responsible for simulation of circuit parts of the three-level converter, and communication between the PXIe controller and the FPGA module is achieved through a PXIe bus. In addition, the PXIe controller can also communicate with an upper computer through Ethernet such that real-time simulation waveforms are displayed on the upper computer, and the FPGA module can be connected with an external controller and an oscilloscope through I/O ports to perform hardware-in-loop simulation.
Programs in the upper computer, the PXIe controller and the FPGA module are all programmed in a LabVIEW development environment of the National Instruments (NI) Corporation. Through Labview programming, the programs in the host computer perform functions of communicating with the PXIe controller, displaying the simulation waveforms, etc.; and the programs in the PXIe controller perform functions of communicating with the upper computer, reading data from and writing data into the FPGA module, simulating the control system of the converter, etc. The above-described programs do not fall within the scope of the present invention, and relevant program examples are available on the official website of the National Instruments (NI) Corporation, therefore the programs will not be described in detail here.
However, the FPGA
module is the specific implementation carrier of the invention and is programmed through Labview, referring to Fig. 5 which is a circuit diagram of a constant-admittance modeling and real-time simulation method for a single-phase three-level converter according to this specific application example.
The constant-admittance modeling and real-time simulation method for the single-phase three-level converter according to the specific application example comprises the following steps that:
(1) each branch and each node in the three-level converter and in a circuit where the three-level converter resides are numbered, as shown in Fig. 5b;
(2) each of resistor branches, inductor branches, capacitor branches and switch branches is replaced with a respective equivalent model (as shown in Fig. 1) formed by an equivalent admittance and a historical current source which are connected in parallel, and an independent voltage source branch is replaced with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, wherein a simulation step is taken as 1,us , and the equivalent admittance of each branch is as follows:
= ¨1=10S2-1 branch 1 (independent voltage source branch) 0.1 branch 2 (capacitor branch) Y.d, = 2e ¨3 = 2000 SY' le ¨ 6 branch 3 (capacitor branch) Y = 2e ¨3 = 2000 b de 2 le ¨ 6 branch 4 (switch branch) Y = .\/ 2e ¨3 = 0.2Q-1 50e-3 branch 5 (switch branch) Y , = 2e ¨3 = 0.2 SI
50e ¨3 branch 6 (switch branch) Y1, 3 = _______ = 0.2Q' 50e ¨3 branch 7 (inductor branch) = le -6 = 2e ¨ 4 - 50e-3 Y R = ¨1=0.10-1 h_ branch 8 (resistor branch) .. 10 and the calculated value of the equivalent admittance of each branch is also marked in Fig. 5b;
(3) a node admittance matrix Yr, of a circuit to be simulated is calculated according to the equivalent admittance of each branch 2010.2 ¨10 ¨0.2 0 ¨10 2010.2 ¨0.2 0 =
¨0.2 ¨0.2 0.6002 ¨2e-4 0 0 ¨2e-4 0.1002 (4.0) if a current simulation time t = 0 ,us is a simulation initial time, magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches are taken as zero, and an equivalent current of the independent voltage source branch is separately calculated, i.e.:
= ¨750=7500 A
branch 1 (independent voltage source branch) - 0.1 branch 2 (capacitor branch) Ih_C <lc I OA
branch 3 (capacitor branch) = 0 A
branch 4 (turned-off switch branch) ./õ_ = 0 A
branch 5 (turned-off switch branch) //,_ õ, 2 = 0 A
branch 6 (turned-on switch branch) / = 0 A
branch 7 (inductor branch) Ih = OA
=OAIh_R
branch 8 (resistor branch) (5.0) an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time (an inflow current is positive and an outflow current is negative):
injection current of node I1 =7500A
injection current of node 2 2 = ¨7500 A
injection current of node 3 /õ, = OA
injection current of node 4 /õ4 = 0 A
(6.0) a voltage of each node is calculated according to a node voltage equation YV = I. with the injection current, which has been given, flowing into each node in combination with the node admittance matrix:
V =3.7125V
voltage of node 1 ni voltage of node 2 Vn, = ¨3.7125 V
voltage of node 3 Vn, = 0 V
voltage of node 4 Vn4 = 0 V
(7.0) a branch voltage and a branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of each branch:
V = 7.4250 V I = 7.4257e3A
branch 1 (independent voltage source branch) hi' h Vs branch 2 (capacitor branch) V. = 3.7125 V, //, = 7.4250e3 A
branch 3 (capacitor branch) Võ = 3.7125 V, , = 7.4250e3 A
branch 4 (switch branch) V = 3.7125 V, / = 0.7425 A
h _ma I b branch 5 (switch branch) V, = 3.7125 V, / = 0.7425 A
branch 6 (switch branch) V = 0 V, I, -- 0 A
h _ nr3 branch 7 (inductor branch) V; = 0 V, I h = OA
branch 8 (resistor branch) Vh_ õ = 0 V, I h =OA
t (8.0) if the current simulation time = 0 ,us does not reach a final simulation time, the process returns to the step (4.0) and enters a next simulation time t = 1 ;
t =1 ,us the process enters the next simulation time i i (4.1) if the current simulation time t = 1 ds s not the simulation initial time, a magnitude of the historical current source of each branch at the current simulation time is calculated according to the branch voltage and the branch current of each branch at the previous simulation time, wherein a historical current of each branch and an equivalent current are calculated according to the following formulae:
/ = 750 =7500A
branch 1 (independent voltage source branch) 0.1 branch 2 (capacitor branch) /hi, = -7.4250e3 A
branch 3 (capacitor branch) I _cae, = -7.4250e3 A
branch 4 (turned-off switch branch) I, ,õ,,= -0.4529A
branch 5 (turned-off switch branch) I, õ, 2 = -0.4529 A
branch 6 (turned-on switch branch) /õ_,,,3 = 0 A
branch 7 (inductor branch) Iõ_,= 0 A
branch 8 (resistor branch) /h-8 =OA
(5.1) an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
injection current of node 1 /õ' = 1.4925e4 A
injection current of node 2 Iõ2 = ¨1.4925e4 A
injection current of node 3 /õ3 = OA
injection current of node 4 L, = OA
(6.1) a voltage of each node is calculated according to the injection current flowing into each node in combination with the node admittance matrix;
voltage of node 1 V =7.3881V
voltage of node 2 V,õ ¨7.3881V
voltage of node 3 Võ3 =3.6998e-16V
voltage of node 4 Vu4 = 7.3847e-19V
(7.1) the branch voltage and the branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of each branch;
V =14.7762 V / = 7.3522e3 A
branch 1 (independent voltage source branch) hi' h branch 2 (capacitor branch) Võ , = 7.3881V, = 7.3512e3 A
branch 3 (capacitor branch) Vh_cd = 7.3881V, kcae, ,, = 7.3512e3 A
branch 4 (switch branch) V, = 7.388 1V, /,, = 1.0247 A
branch 5 (switch branch) V, 0,2 = 7.3881V, /h , =1.0247 A
_ 141 branch 6 (switch branch) V = 3 .6998e-16 V, /,_ ,w3 = 7 .3995e-17 A
branch 7 (inductor branch) V = 3.6924e-16 V, = 7.3847e-20A
branch 8 (resistor branch) V, = 7.3847e-19 V, /, = 7.3847e-20 A
(8.1) if the current simulation time t = 1,us does not reach a final simulation time, the process returns to the step (4.1) and enters a next simulation time t = 21us;
the process enters the next simulation time t = 2 ,us :
(4.2) if the current simulation time t = 2 ps is not the simulation initial time, the magnitude of the historical current source of each branch and the equivalent current at the current simulation time are calculated according to the branch voltage and the branch current of each branch at the previous simulation time...; this step is as same as the aforementioned step and therefore will not be repeated here; and steps (4)-(8) are repeated as above until the final simulation time is reached, and then the simulation program is ended.
Implementation results are shown in Figs. 2, 3 and 4, wherein Fig. 2 and Fig.
3 show comparisons between results of the method provided by the above embodiment of the present invention and a conventional real-time simulation method, and Fig. 4 shows virtual power loss rates under different converter switching frequencies of the two methods. As shown in Fig.
2 and Fig. 3, the real-time simulation waveform obtained by using the method provided by the embodiment of the invention is closer to an ideal switching waveform than the conventional inductor/capacitor equivalent based method, and the precision of real-time simulation of the three-level converter is greatly improved. A converter composed of ideal switches has no virtual power loss, while in conventional inductor/capacitor equivalent based methods, the virtual power loss of the three-level converter increases along with the increase of switching frequency, as shown in Fig. 4, to an extent of up to 60% or more at 100 kHz, and is greatly not matched with the actual situation. By using the method provided by the present invention, the virtual power loss of the three-level converter substantially does not change along with the switching frequency and is always maintained at a level close to zero, and the three-level converter is closer to the converter composed of ideal switches.
Embodiment 2: A constant-admittance modeling and real-time simulation method for a two-level converter comprises the following steps that:
(1) each branch and each node in the two-level bridge converter and in a circuit where the two-level bridge converter resides are numbered, as shown in Fig. 8;
(2) each of resistor branches, inductor branches, capacitor branches and switch branches is replaced with a respective equivalent model (as shown in Fig. 1) formed by an equivalent admittance and a historical current source which are connected in parallel, and an independent voltage source branch is replaced with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, wherein a simulation step is taken as 1,us , and the equivalent admittance of each branch is as follows:
branch 1 (independent voltage source branch) - 0.1 2e-3 = 2000 SY' branch 2 (capacitor branch) - le ¨6 2e ¨3 Yh (k2 = =2000' branch 3 (capacitor branch) le ¨6 \I 2e-3 Y = _____ = 0.2 Sr' h +id branch 4 (switch branch) 50e ¨3 \I Y
w2 2e-3 h s branch 5 (switch branch) 50e ¨3 le-6 Y bL = 50e ¨3 = 2e ¨ 4 Sr' branch 6 (inductor branch) Y = 1 h-" 10 branch 7 (resistor branch) and the calculated value of the equivalent admittance of each branch is also marked in Fig. 8b;
(3) a node admittance matrix Y. of the circuit to be simulated is calculated according to the equivalent admittance of each branch 2010.2 ¨10 ¨0.2 0 ¨10 2010.2 ¨0.2 0 Y. =
¨0.2 ¨0.2 0.4002 ¨2e-4 0 0 ¨2e-4 0.1002 (4.0) if a current simulation time t = 0 ps is a simulation initial time, magnitudes of the historical current sources of all the branches are taken as zero, and an equivalent current of the independent voltage source branch is separately calculated, i.e.:
I. = 750 =7500A
branch 1 (independent voltage source branch) 0.1 branch 2 (capacitor branch) /õ. = OA
branch 3 (capacitor branch) 'h (k' = 0 A
branch 4 (switch branch) 'h = 0 A
branch 5 (switch branch) /h_ 2 = 0 A
branch 6 (inductor branch) 1.,J, = 0 A
/h =OA
branch 7 (resistor branch) (5.0) an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time (an inflow current is positive and an outflow current is negative):
injection current of node 1 in = 7500 A
= ¨7500 A
injection current of node 2 -injection current of node 3 1,3 = OA
injection current of node 4 /n4 = OA
(6.0) a voltage of each node is calculated according to a node voltage equation YõVõ = Iõ with the injection current, which has been given, flowing into each node in combination with the node admittance matrix:
voltage of node 1 Vn = 3.7125 V
voltage of node 2 Vn2 = ¨3.7125 V
voltage of node 3 0= V Vn3 0= voltage of node 4 V V n4 (7.0) a branch voltage and a branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of each branch:
branch 1 (independent voltage source branch) V = 7.4250 V / = 7.4257e3 A h V = 3 .7 125V'1 Cdcl = 7.4250e3 A
branch 2 (capacitor branch) h -c""
Vb_(Vc2 = 3.7125 V / = 7.4250e3 A
branch 3 (capacitor branch) h (Vc.1 - -V = 3.7125 V, /,, = 0.7425 A
branch 4 (switch branch) b_ _ V = 3.7125 V / = 0.7425 A
branch 5 (switch branch) h _ vw2 b sly"
-Lac branch 6 (inductor branch) Vb -1""µ = 0 V /h = 0 A
branch 7 (resistor branch) Vb -R = 0 V' Ih R = OA
(8.0) if the current simulation time t Ps does not reach a final simulation time, the process returns to the step (4) and enters a next simulation time t = 1,us ;
(4.1) if the current simulation time t = 1 Ps is not the simulation initial time, a magnitude of the historical current source of each branch at the current simulation time is calculated according to the branch voltage and the branch current of each branch at the previous simulation time, wherein historical currents of various branches are calculated according to the following formulae:
Is is = =7500 A
branch 1 (independent voltage source branch) - 0.1 branch 2 (capacitor branch) Ih _(õk I = -7.4250e3 A
branch 3 (capacitor branch) Ih _Cdc 2 = -7.4250e3 A
branch 4 (turned-on switch branch) Ih_ su = 2.5351A
branch 5 (turned-off switch branch) /fi - "92 = -0.4349 A
branch 6 (inductor branch) lb -L = 0 A
h _R = 0 A
branch 7 (resistor branch) (5.1) an injection current flowing into each node is calculated according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
injection current of node 1 Ini = 1.4922e4 A
injection current of node 2 /n2 = ¨1.4925e4 A
injection current of node 3 In3 = 2.9700A
injection current of node 4 In4 = 0 A
(6.1) a voltage of each node is calculated according to the injection current flowing into each node in combination with the node admittance matrix;
voltage of node 1 VnI = 7.3874 V
Vn2 =-7.3874V
voltage of node 2 voltage of node 3 V"3 =7.4213V
voltage of node 4 V" =0.0148V =
(7.1) the branch voltage and the branch current of each branch are calculated according to the voltage of each node in combination with the equivalent admittance of each branch;
V branch 1 (independent voltage source branch) hi' =14.7747 V/ h ¨ 73523e3 A
I"µ ¨ =
h = 7.3 874 V / = 7 .3497e3 A
branch 2 (capacitor branch) V h Cdcl V = 7.3874 V, Ib _CU:2 7.3497e3 A
branch 3 (capacitor branch) V = -0.0339 V / =2.5283A
branch 4 (switch branch) b I h µµ.
V = 14.8087 V / 2 5268 A
branch 5 (switch branch) b _ sw 2 is 2 ¨ -ac 0 .0015 A
branch 6 (inductor branch) V h _La = 7 .4065 V, 'h c V =0.0148V / =0.0015A
branch 7 (resistor branch) b -R b _R
(8.1) if the current simulation time t = 1,us does not reach a final simulation time, the process returns to the step (4) and enters a next simulation time t = 2 ,us;
(4.2) if the current simulation time t = 2 ,us is not the simulation initial time, the magnitude of the historical current source of each branch at the current simulation time is calculated according to the branch voltage and the branch current of each branch at the previous simulation time...; and steps (4)-(8) are repeated as above until the final simulation time is reached, and then the simulation program is ended.
Specific embodiments of the invention have been described above. It is to be understood that the invention is not limited to the particular implementations described above, and that various changes and modifications may be made by those skilled in the art within the scope of the appended claims without influencing the essence contents of the invention.
Claims (3)
1. A constant-admittance modeling and real-time simulation method for a power electronic converter, characterized by comprising the following steps of:
S1, numbering each branch and each node in the power electronic converter and in a circuit where the power electronic converter resides, wherein a grounding node is numbered as 0;
S2, replacing each of resistor branches, inductor branches, capacitor branches, and switch branches in the power electronic converter with a respective equivalent model formed by an equivalent admittance and a historical current source which are connected in parallel; replacing an independent voltage source branch with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, and calculating the equivalent admittance of the equivalent model of each branch, wherein the equivalent admittance of the equivalent model of each switch branch is constant in both an on state and an off state, S3, calculating a node admittance matrix of a circuit to be simulated according to the equivalent admittance of each branch;
S4, if a current simulation time t is a simulation initial time, taking magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches as zero, and separately calculating an equivalent current of the independent voltage source branch; and if the current simulation time t is not the simulation initial time, calculating magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches at the current simulation time according to branch voltages and branch currents of the resistor branches, the inductor branches, the capacitor branches and the switch branches at a previous simulation time, and separately calculating the equivalent current of the independent voltage source branch;
S5, calculating an injection current flowing into each node according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
S6, calculating a voltage of each node according to the injection current flowing into each node in combination with the node admittance matrix;
S7, calculating the branch voltage and the branch current of each branch according to the voltage of each node in combination with the equivalent admittance of the equivalent model of each branch; and S8, if a final simulation time is not reached, returning to S4 and entering a next simulation time t + .DELTA.t; otherwise, ending.
S1, numbering each branch and each node in the power electronic converter and in a circuit where the power electronic converter resides, wherein a grounding node is numbered as 0;
S2, replacing each of resistor branches, inductor branches, capacitor branches, and switch branches in the power electronic converter with a respective equivalent model formed by an equivalent admittance and a historical current source which are connected in parallel; replacing an independent voltage source branch with an equivalent model formed by an equivalent admittance and an equivalent current source which are connected in parallel, and calculating the equivalent admittance of the equivalent model of each branch, wherein the equivalent admittance of the equivalent model of each switch branch is constant in both an on state and an off state, S3, calculating a node admittance matrix of a circuit to be simulated according to the equivalent admittance of each branch;
S4, if a current simulation time t is a simulation initial time, taking magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches as zero, and separately calculating an equivalent current of the independent voltage source branch; and if the current simulation time t is not the simulation initial time, calculating magnitudes of the historical current sources of the resistor branches, the inductor branches, the capacitor branches and the switch branches at the current simulation time according to branch voltages and branch currents of the resistor branches, the inductor branches, the capacitor branches and the switch branches at a previous simulation time, and separately calculating the equivalent current of the independent voltage source branch;
S5, calculating an injection current flowing into each node according to the magnitudes of the historical current sources and the magnitude of the equivalent current source at the current simulation time;
S6, calculating a voltage of each node according to the injection current flowing into each node in combination with the node admittance matrix;
S7, calculating the branch voltage and the branch current of each branch according to the voltage of each node in combination with the equivalent admittance of the equivalent model of each branch; and S8, if a final simulation time is not reached, returning to S4 and entering a next simulation time t + .DELTA.t; otherwise, ending.
2. The constant-admittance modeling and real-time simulation method for the power electronic converter according to claim 1, characterized in that the equivalent admittance of the equivalent model of each branch is calculated according to the following formulae:
the equivalent admittance of each resistor branch is: wherein, R is a resistance of the resistor branch;
the equivalent admittance of each inductor branch is. wherein, L is an inductance of the inductor branch, and At is a time step of real-time simulation;
the equivalent admittance of each capacitor branch is. wherein, C is a capacitance of the capacitor branch;
the equivalent admittance of each switch branch is: wherein, C dc is a capacitance of a direct-current side of the power electronic converter, and L
ac is an inductance of an alternating-current side of the power electronic converter; and the equivalent admittance of the independent voltage source branch is:
wherein R s is an internal resistance of the independent voltage source branch.
the equivalent admittance of each resistor branch is: wherein, R is a resistance of the resistor branch;
the equivalent admittance of each inductor branch is. wherein, L is an inductance of the inductor branch, and At is a time step of real-time simulation;
the equivalent admittance of each capacitor branch is. wherein, C is a capacitance of the capacitor branch;
the equivalent admittance of each switch branch is: wherein, C dc is a capacitance of a direct-current side of the power electronic converter, and L
ac is an inductance of an alternating-current side of the power electronic converter; and the equivalent admittance of the independent voltage source branch is:
wherein R s is an internal resistance of the independent voltage source branch.
3. The constant-admittance modeling and real-time simulation method for the power electronic converter according to claim 1, characterized in that, when the power electronic converter is a three-level converter, historical currents and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is: I h_R = 0 the historical current of each inductor branch is:I h_L(t) = i l (t -.DELTA.t) , wherein, i l (t ¨ .DELTA.t) is the branch current of the inductor branch at the previous simulation time;
the historical current of each capacitor branch is. I h_C(t) = Y b_CµC
(t ¨ .DELTA.t) ; wherein, u C (t ¨ .DELTA.t) is the branch voltage of the capacitor branch at the previous simulation time, and Y b_C is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is:
I h_sw (t) = -5.04Y b_sw u sw (t ¨ .DELTA.t) ¨ i sw (t ¨ .DELTA.t) ; and in the off state, the historical current of each switch branch is: I h_sw(t) =Y b_sw u sw(t ¨ .DELTA.t) ¨0.39i sw (t ¨ .DELTA.t); wherein, u sw (t ¨ .DELTA.t) is the branch voltage of the switch branch at the previous simulation time, i sw (t ¨ .DELTA.t) is the branch current of the switch branch at the previous simulation time, and Yb_ sw is the equivalent admittance of the switch branch;
the equivalent current source of the independent voltage source branch is wherein, V s(t) is an internal electric potential of the independent voltage source branch, and R s is the internal resistance of the independent voltage source branch; and when the power electronic converter is a two-level converter, the historical currents and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is: I h_R=0;
the historical current of each inductor branch I h_L(t)=i l(t -.DELTA.t);wherein, i L(t-.DELTA.t) is the branch current of the inductor branch at the previous simulation time;
the historical current of each capacitor branch is: I h_C(t)=-Y b_C u C (t ¨
.DELTA.t) u C(t-.DELTA.t) is the branch voltage of the capacitor branch at the previous simulation time, and Y b_C is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is:
I h_sw (t) = (-1 + .sqroot.2)Y b_swu sw(t ¨ .DELTA.t) ¨i sw (t ¨ .DELTA.t) ;
and in the off state, the historical current of each switch branch is:
I h_sw(t) =Y b_sw u sw(t ¨ .DELTA.t)+(1+.sqroot.2)i sw(t - .DELTA.t);
or, in the on state, the historical current of each switch branch is:
I h_sw(t) = (-1 ¨ .sqroot.2)Y b_sw u sw (t ¨ .DELTA.t) ¨i sw (t ¨ .DELTA.t);
and in the off state, the historical current of each switch branch is:
I h_sw (t)=Y b_sw u sw (t ¨.DELTA.t)+(1¨.sqroot.2)i sw (t ¨.DELTA.t);
wherein, u sw(t ¨ .DELTA.t) is the branch voltage of the switch branch at the previous simulation time, i sw(t -.DELTA.t) is the branch current of the switch branch at the previous simulation time, and Y b_sw is the equivalent admittance of the switch branch; and the equivalent current source of the independent voltage source branch is wherein, V s (t) is an internal electric potential of the independent voltage source branch, and R s is the internal resistance of the independent voltage source branch.
the historical current of each resistor branch is: I h_R = 0 the historical current of each inductor branch is:I h_L(t) = i l (t -.DELTA.t) , wherein, i l (t ¨ .DELTA.t) is the branch current of the inductor branch at the previous simulation time;
the historical current of each capacitor branch is. I h_C(t) = Y b_CµC
(t ¨ .DELTA.t) ; wherein, u C (t ¨ .DELTA.t) is the branch voltage of the capacitor branch at the previous simulation time, and Y b_C is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is:
I h_sw (t) = -5.04Y b_sw u sw (t ¨ .DELTA.t) ¨ i sw (t ¨ .DELTA.t) ; and in the off state, the historical current of each switch branch is: I h_sw(t) =Y b_sw u sw(t ¨ .DELTA.t) ¨0.39i sw (t ¨ .DELTA.t); wherein, u sw (t ¨ .DELTA.t) is the branch voltage of the switch branch at the previous simulation time, i sw (t ¨ .DELTA.t) is the branch current of the switch branch at the previous simulation time, and Yb_ sw is the equivalent admittance of the switch branch;
the equivalent current source of the independent voltage source branch is wherein, V s(t) is an internal electric potential of the independent voltage source branch, and R s is the internal resistance of the independent voltage source branch; and when the power electronic converter is a two-level converter, the historical currents and the equivalent current are calculated according to the following formulae:
the historical current of each resistor branch is: I h_R=0;
the historical current of each inductor branch I h_L(t)=i l(t -.DELTA.t);wherein, i L(t-.DELTA.t) is the branch current of the inductor branch at the previous simulation time;
the historical current of each capacitor branch is: I h_C(t)=-Y b_C u C (t ¨
.DELTA.t) u C(t-.DELTA.t) is the branch voltage of the capacitor branch at the previous simulation time, and Y b_C is the equivalent admittance of the capacitor branch;
in the on state, the historical current of each switch branch is:
I h_sw (t) = (-1 + .sqroot.2)Y b_swu sw(t ¨ .DELTA.t) ¨i sw (t ¨ .DELTA.t) ;
and in the off state, the historical current of each switch branch is:
I h_sw(t) =Y b_sw u sw(t ¨ .DELTA.t)+(1+.sqroot.2)i sw(t - .DELTA.t);
or, in the on state, the historical current of each switch branch is:
I h_sw(t) = (-1 ¨ .sqroot.2)Y b_sw u sw (t ¨ .DELTA.t) ¨i sw (t ¨ .DELTA.t);
and in the off state, the historical current of each switch branch is:
I h_sw (t)=Y b_sw u sw (t ¨.DELTA.t)+(1¨.sqroot.2)i sw (t ¨.DELTA.t);
wherein, u sw(t ¨ .DELTA.t) is the branch voltage of the switch branch at the previous simulation time, i sw(t -.DELTA.t) is the branch current of the switch branch at the previous simulation time, and Y b_sw is the equivalent admittance of the switch branch; and the equivalent current source of the independent voltage source branch is wherein, V s (t) is an internal electric potential of the independent voltage source branch, and R s is the internal resistance of the independent voltage source branch.
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| CN201811491963.0A CN109543339B (en) | 2018-12-07 | 2018-12-07 | Fixed admittance modeling and real-time simulation method of three-level converter |
| CN201811491738.7 | 2018-12-07 | ||
| PCT/CN2019/081194 WO2020113874A1 (en) | 2018-12-07 | 2019-04-03 | Constant admittance modeling and real-time simulation method for power electronic converter |
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