CA2985254A1

CA2985254A1 - Integration and bonding of micro-devices into system substrate

Info

Publication number: CA2985254A1
Application number: CA2985254A
Authority: CA
Inventors: Reza Chaji; Bahareh Sadeghi Makki
Original assignee: Vuereal Inc
Current assignee: Vuereal Inc
Priority date: 2017-11-14
Filing date: 2017-11-14
Publication date: 2019-05-14
Also published as: US20230253350A1; US10818622B2; CN109786352A; CN109786352B; TWI706510B; CN116741733A; TW201923976A; US20210020593A1; US20190148321A1; DE102018128584A1

Abstract

This disclosure is related to integrating optoelectronics microdevices into a system substrate for enhanced bonding properties and durability. 2D nanostructures and 3D scaffolds create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

Description

- 2 -INTEGRATION AND BONDING OF MICRO-DEVICES INTO SYSTEM SUBSTRATE
FIELD OF THE INVENTION
[0001] The present disclosure relates to bonding micro-devices to other substrates using a low cost, reliable approach that will improve the yield and surface profile.
More specifically, the bonding area will be increased and interlocked using 2D and 3D nanostructures with or without using a host mediums.
BRIEF SUMMARY
[0002] A few embodiments of this description are related to the formation of conductive, flexible and thermally stable 2D and 3D nanostructures on the receiving and/or micro device substrates, for effective bonding of the micro-devices located on the donor substrate. In addition to improved morphological parameters such as surface topography, increased surface profile, and crystallinity, physical properties such as electrical conductivity, thermal stability, and reliability are enhanced between two substrates. Decreased pixel pitch of the micro-devices make use of nanostructures critical for effective and reliable bonding.

[0003] The micro device array may comprise micro light emitting diodes (LEDs), Organic LEDs (OLEDs), sensors, solid state devices, integrated circuits, (micro-electro-mechanical systems) MEMS, and/or other electronic components. Candidates for the receiving substrate include, but are not limited to, a printed circuit board (PCB), thin film transistor backplane, integrated circuit substrate. In the case of optical micro devices such as LEDs, the receiving substrate can be a component of a display, such as a driving circuitry backplane.
BRIEF DESCRIPTION OF THE DRAWINGS

[0004] A few embodiments of this description are related to controlling the temperature and pressure during the bonding process, to provide a strong bond.

[0005] The foregoing and other advantages of the disclosure will become apparent upon reading the following detailed description and upon reference to the drawings.

[0006] FIG. IA shows randomly formed nanotextures combining nanoparticle hard masks (such as silica or polystyrene nanosphere masks) and etching (dry, milling, wet) and their bonding onto micro device and receiving substrates.

[0007] FIG. 1B shows SEM image showing realization of silver nanotextures using nanosphere masks and milling.

[0008] FIG. 2A shows formation of arrays of nonporous/nanopores nanostructures on substrate using BCP or AAO template with engineered size-pitch and consecutive deposition of bonding material (e.g. metal) onto the template using PECVD, PVD, CVD, sputtering, printing, spin coating deposition methods.

[0009] FIG. 2B shows formation of arrays of nonporous/nanopores nanostructures on substrate using hard mask B 1) BCP or AAO, B2) patterned etch mask, and B3) silica or polymer nanosphere templates followed by Metal electro-less plating in open areas or electrochemical metal deposition.

[0010] FIG. 2C shows the bonding of nonporous/nanopores nanostructures between micro-device arrays and receiving substrate.

[0011] FIG. 3 shows formation of 3D conductive (metal, NP/CNT/rGO) nanoporous using self-assembly of nanoparticle hard mask template (such as silica or polymer nanosphere template).

[0012] FIG. 3A shows 3D metal nanoporous structure using self-assembly of nanoparticle hard mask template (such as silica or polymer nanosphere template).
100131 FIG. 3B shows 3D mixture of metal NPs, CNT/rGO NWs and silica nanospheres using self-assembly of nanoparticle hard mask template (such as silica or polymer nanosphere template).
[0014] FIG. 3C shows core/shell silica or polystyrene nanospheres with metallic shells using self-assembly of nanoparticle hard mask template (such as silica or polymer nanosphere template).
[0015] FIG. 3D shows the alignment and bonding of the structures presented in FiG. 3A-3C.

100161 FIG. 4A1 shows formation of ordered arrays of nanopillars/nanowires/needles/
nanocones nanostructure using nanosize hard masks and etching (dry, milling, wet).
[0017] FIG. 4A2 shows formation of ordered arrays of nanopillars/nanowires/needles/
nanocones nanostructure using nanosize hard masks and etching (dry, milling, wet) using silica or polystyrene nanospheres as hard mask.
[0018] FIG. 4B1 shows random formation of nanostructures through self-masking and etching (dry, wet, milling).
[0019] FIG. 4B2 shows random formation of nanostructures through seed formation and hydrothermal growth followed by subsequent metal deposition.
[0020] FIG. 5A shows bonding of vertically aligned CNTs or rGO NWs between pads of micro device arrays and receiving substrate.
[0021] FIG. 5B shows bonding of randomly formed CNTs or rGO NWs between pads of micro device arrays and receiving substrate.
[0022] FIG. 6A shows formation of random 3D stacks of rGO sheets decorated with nanopillarsNWs.
[0023] FIG. 6B shows formation of vertically aligned 3D stacks of rGO sheets decorated with nanopi I larsN Ws.
[0024] FIG. 6C shows bonding of random 3D stacks of rGO sheets decorated with nanopillarsNWs between pads of micro device arrays and receiving substrate.
[0025] FIG. 6D shows bonding of vertically aligned 3D stacks of rGO
sheets/foam/film decorated with nanopillars/NWs between pads of micro device arrays and receiving substrate.
[0026] FIG. 7A shows formation of metal nanoparticles/nanowires decorated reduced graphene oxide (rGO): a mutually-supporting porous structures.
[0027] FIG. 7B shows bonding of 3D stack of metal nanoparticles (NPs) decorated on reduced graphene oxide (rGO) sheets/foam/films between pads of micro device arrays and receiving substrate.
[0028] FIG. 7C shows bonding of 3D stack of silver nanoparticles/nanowires decorated reduced graphene oxide (rGO) sheets/foam/films between pads of micro device arrays and receiving substrate.

[0029] FIG. 8A shows 3D scaffold of aligned crossed metallic/TCO nanowires and nanofibers (metallic, polymer, CNTs, carbon, etc).
[0030] FIG. 8B1 shows 3D scaffold of randomly crossed metallic nanowires and nanofibers (metallic, polymer, CNTs, and carbon, etc.).
[0031] FIG. 8B2 shows 3D scaffold of randomly crossed metallic nanowires and nanofibers (metallic, polymer, CNT, and carbon, etc.) decorated with metal nanoparticles.
[0032] FIG. 8C shows interlocked bonding of 3D scaffold of randomly crossed nanowires/nanofibers decorated with metal NPs between micro-device arrays and receiving substrates.
[0033] FIG. 9A shows hierarchical branch-type nanowires with improved interlocking properties with a backbone (such as Sn02) and branches (such as Zn0), combining carbothermal reduction with hydrothermal or catalyst-assisted VLS growth.
[0034] FIG. 9B shows comb-like branched-type nanowires with improved interlocking properties with a backbone (such as Sn02) and branches (such as Zn0).
[0035] FIG. 9C1 shows 3D scaffold of aligned hierarchical nanostructures.
[0036] FIG. 9C2 shows 3D scaffold of randomly formed hierarchical nanostructures.
[0037] FIG. 9C3 shows 3D scaffold of randomly-formed comb-like nanostructures.
[0038] FIG. 9D1 shows bonding of 3D scaffold of aligned hierarchical nanostructures between micro-device arrays and receiving substrates.
[0039] FIG. 9D2 shows bonding of 3D scaffold of randomly-formed hierarchical nanostructures between micro-device arrays and receiving substrates.
[0040] FIG. 9D3 shows bonding of 3D scaffold of randomly-formed comb-like nanostructures between micro-device arrays and receiving substrates.
[0041] FIG. 10 shows branch-type nanowires with improved interlocking properties with A) nanowire and B) nanocone backbone (metal, TCO) and branches (metal, TCO) formed through consecutive self-assembly of etch masks (nano hard masks, silica, polymer beads, etc) and etching (dry, wet, milling).

[0042] FIG. 11 shows formation of metallic nanomesh using nanosphere lithography with engineered size pitch through etching followed by bonding material (e.g metal layer) deposition, forming 2D nanohole arrays.
[0043] FIG. 12 shows 3D assembly of silica or polystyrene nanobeads and nanostructures with one directional current path (e.g. metal/TCO NWs, graphene nanowires or CNTs, etc) for selective bonding.
[0044] FIG. 12A shows 3D assembly of mixture of silica or polystyrene nanobeads and metal/TCO NWs, graphene nanowires or CNTs, etc) for selective bonding.
[0045] FIG. 12B shows 3D assembly of mixture of silica or polystyrene nanobeads and metal/TCO NWs, graphene nanowires or CNTs, etc) with additional metal NPs for selective bonding.
[0046] FIG. 13A shows core metal nanoparticles (Ag, Ni, etc).
[0047] FIG. 13B shows core/shell nanoparticles (silica coated silver, Ag/silica, etc).
[0048] FIG. 13C shows alloyed nanoparticles (Ag-Cu, etc).
[0049] FIG. 14A shows bonding of core metal nanoparticles (Ag, Ni, etc) incorporated into curable host medium (polyimide, SU8, silicone, UV adhesives, and bonding epoxies).
[0050] FIG. 14B shows bonding of core/shell nanoparticles (e.g.silica coated metal, metal coated Silica, etc) incorporated into curable host medium (polyimide, SU8, silicone, UV
adhesives, and bonding epoxies).
[0051] FIG. 14C shows bonding of alloyed nanoparticles (Ag-Cu, etc) incorporated into curable host medium (polyimide, SU8, silicone, UV adhesives, and bonding epoxies).
[0052] FIG. 15A shows application of curing agent in bonding of the nanostructures formed on pads of micro-device arrays and receiving substrate after alignment.
[0053] FIG. 15B shows application of curing agent in bonding of the nanostructures formed on pads of micro-device arrays and receiving substrate before alignment.

DETAILED DESCRIPTION
[0054] The process of transferring micro devices into a receiver substrate involve bonding of a pre-selected array of micro devices to the receiver substrate, followed by removing the donor substrate. Several bonding processes have already been developed for micro devices.
[0055] In this disclosure, pads in a receiver substrate refers to a designated area in the receiver substrate to where a micro device is transferred. The pad could have some form of bonding materials to hold the micro device permanently. The pad can be stacked in multiple layers to offer a more mechanically stable structure with improved bonding and conductivity capability.
[0056] One embodiment is a bonding structure where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, and at least one of the said surfaces is textured after depositing some layers on the surfaces.
[0057] In this embodiment or other related embodiments in this disclosure nanoparticle can be dispersed between the two said surfaces to enhance the bonding property.
[0058] In this embodiment or other related embodiments in this disclosure soldering layers or bonding agent can be deposited on at least one of the said surfaces.
[0059] Another embodiment is a bonding process where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, at least one of the said surface is covered by nanowires, and the area between nanowires is filed by bonding agent.
[0060] The bonding agent in this embodiment or other related embodiments can be solvent filled with conductive nanoparticles.
[0061] Another embodiment is a bonding process where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, at least one of the said surface is covered by nanowires where a template is used to control the orientation of the nanowires.
[0062] The template can be made of 3d structures (spherical) deposited on the said surface.
[0063] Another embodiment is a bonding process where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, and at least one of the said surface is covered by non-conductive nanowires.
[0064] At least one of the nanowire is covered by a conductive layer.
[0065] some of the nanowires can be used as a support structure (network) for other conductive structures such as nanowire, conductive sheets, and nano particles.
[0066] In this bonding process, a bonding agent can be used to fill the space between the nanowires.
[0067] In this bonding process, some of nanowires act as bonding agent holding the two surfaces together. these nanowires can adhere to the surfaces by means of thermal, chemical, or optical activation. In one example, the nanowires are acrylic based.
[0068] Another embodiment is a bonding process where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, at least one of the said surface is covered by scaffold structure [0069] The scaffold structure can be formed by depositing at least one layer on a template.
[0070] The scaffold structure can be a preformed scaffold that is transferred to the said surface after a adhesion layer added to the surface.
[0071] The scaffold structure can be a preformed scaffold that is transferred to the said surface and adhesion layer is deposited after the said transfer.
[0072] to create electrical connection between optoelectronic devices and a pads on a receiver substrate, the optoelectronic devices gets bonded to the receiver pads. In some cases, bonding layers are deposited on the optoelectronic device and on the receiver substrate pads.
After physical connection between the bonding layers, bonding conditions are applied to solidify the bonding. these conditions could be applications of light, temperature, and/or pressure. the reliability of this bondings are direct function of surface area of the bond pads and the optoelectronic devices, amount of bonding material used for each pads, and adhesion of bonding layers to the original pads and/or optoelectronic devices.
[0073] As the bonding pads becomes smaller for the high density devices made of array of optoelectronic devices bonded to a receiver substrate, the bonding, yield, performance, and reliability becomes more challenging. In one embodiment to improve the bonding reliability and yield, the surface of bond pads on either receiver substrate or optoelectronic devices (micro devices) gest textured. Here, a layer of conductive (or nonconductive) material is deposited. This layer should be at least covering the pad areas. After deposition, other processing may be done on the said layer (or layers) such as surface treatment, patterning, and or functionalization. Then, the layer (or layers) is textured due to different means such as ion milling, RIE, other means of dry etching, or wet etching. The texture increases the surface area of the pads and also creates an interlocking case that can tolerate high mismatch between different pads. In another embodiment, bonding layers, and/or bonding agent is deposited on the surface of the pads. In one case, a thin layer of soldering materials (such as In, Tin, ...) is deposited.
In another case, nano particles (either solid conductive or hybrid shell-core conductive-nonconductive) are dispersed in the surface of the pads. These nanoparticles can be suspended inside a solution that can also act as a bonding agent (and fillers of the empty space) or it can evaporate and leave the nanoparticles on the surface. In one case, the texturing can go through all layers till it reaches the pads. This case will consist of stand alone 3d structure that are connected only through pad surface area.
[0074] In another case, 3d structures are grown on the surface (at least on the pad surface).
Here, the 3d structure such as nanowire can be conductive. In one case, it can be also the bonding agent. In another case, other layers can be deposited on top of the wire to create the bonding agent. In another case, nanoparticles such as other nanowire, 2d sheets, or spheres can be dispersed between the 3d structures. In another case, solutions can be used to fill the area between the 3d structures (in case of using dispersed nanoparticles, this solution can be the same as the solvent of the dispersed nanoparticles). In some cases, the conductive 3d structure (i.e metallic nanowire) does not offer significant structural rigidity required for bonding. In this case, a non-metallic nanowire core is deposited and the surface is covered by conductive layers (and/or bonding layers). These layers also connect the surface of the 3d structures to the pad surface or microdevice. In another case, the non-metallic nanowire is used as structural support for conductive materials such as metallic nanowire, 2d sheets (reduced graphite layers), spheres and more. other methods used for bonding of 3d structures can be used with these structures as well.
[0075] In one case, the 3d structures (either formed by the texturing or growth) can be branched through extra growth process. The extra branches can offer higher surface and better interlocking.
[0076] If 3d structure is outside the pad surface area (either by surface texturing or growth), it will not be connected to any active element on the receiver substrate or microdevice substrate.
These structures can be removed by etching or can remain on the surface and offer some extra functionality. In one case, they can offer structural support. Moreover, these structures can be designed to offer certain optical performance such as filtering of certain wavelength to offer better color purity and/or light directionality. In another case, they can be used as other sensors such as capacitive touch. As the aspect ration of this structures is very tall, the electric field at the top can be very high. Therefore, a small disturbance caused by outside source can create significant change in the electric field which can be detected as a touch input.
[0077] In another embodiment, scaffold structure is used to enhance the bonding property between optoelectronic device and receiver substrate. In one case, the scaffold layer is grown or formed on at least the pad surface. One method is to develop a template on the surface. These template can be made of particles such (spheres, nanowires, sheets, ...).
Then, at least one conductive layer is deposited on the template. After that, the template can be removed or stay inside the structure. Here, other bonding layers or agents (nanoparticles, polymers, ...) can be used. In another case, the scaffold is transferred or deposited on the surface. Here, in one case, at least one adhesion layer is used between the scaffold structure and the pad (or micro device) to hold the scaffold in place. In another case, a adhesion layer is deposited (different methods) after the scaffold is transferred or deposited on the surface. The adhesion layer can be different materials such as soldering materials, polymers, functional solution with nanoparticles, and etc.

[0078] In one embodiment, the contact area (bonding area) on the receiver and/or micro device substrate is increased using nanotextured, nanoporous, and nano-pores structures with large active surface areas. The nanotextured and nanoporous structures can be formed randomly or in a defined ordered. For example, the nanopores can be formed as arrays of aligned pores or random porous structures.
[0079] In another embodiment, conic and needle-like nanostructures, pillars, and nanowires (N Ws) made from transparent conductive oxides (TCO), metals, and/or conductive graphene-based materials such as reduced graphene oxide (rGO) and carbon nanotubes (CNTs) are used. These upright (or slightly tilted) structures provide a vertical current path with low resistivity, and show advantages of mechanical flexibility, and thermal stability. The nanostructures can be randomly formed in high density arrangements, or fabricated in ordered array structures with desired size and pitch. The number of nanostructures will be optimized for maximum vertical conduction.
[0080] In this embodiment, the said structures are formed through etching a planar layer. A
thin film layer is deposited through different methods (e.g. plasma enhanced chemical vapor deposition (PECVD), sputtering, printing, spin coating, ...) to use as a hard mask and then a pattern is formed on top of the layer. The said layer is etched using different methods (ion milling, dry etching, wet etching and etc) to form a 3D nanostructure. The structure can be formed either by etching the entire layer or only partially etching of said layer.
[0081] In another method, the said structure is self assembled on the surface.
The surface of pads area either on the micro device or receiver substrate is treated either through deposition or different curing process (e.g. surface functionalization, etc) to enable selective assembly of the said structure on the pad areas or the entire surface area.
[0082] In another embodiment, the structure is covered by another layer to enhance the bonding process. In one case, the structures are covered by materials that can be either cured through light, thermal, mechanical force, or chemical reaction. In this case, after aligning and connecting the receiver substrate and micro-devices together, the required curing agent is applied to enhance the bonding.

[0083] In another embodiment, between the structures can be filled with other materials to enhance the bonding process. These materials can be curable under different conditions and curing agents (lights, pressure, thermal, and etc).
[0084] In another embodiment the entire surface of either receiver or micro device substrate is covered with the structures including the pad areas and the space between the pad areas.
However, the structures are sparse so that there is no connection between the structures. In one case, the structures can be separated by some dielectric structures such as thin film layer, nanoparticles, and etc. Here, the micro-devices and the receiver substrates are aligned and bonded together through the structures formed on the surface. The bonding can be enhanced using different curing process. In one case, current can be applied through the structures to passing through the micro devices for micro welding. In another cuse, higher temperature, pressure, and/or light can be used to enhance the bonding process.
[0085] In one embodiment, interlocked nanostructures with extremely large surface areas are formed using randomly crossed metallic nanowires, branch-type nanowires, 3D metallic, and carbon nanofibers, and metallic mesh/clothes, forming a 3D scaffold. The crossing of NWs spatially extend the bonding area, leading to effective bonding.
[0086] For the above embodiments, the size (diameter), length, and concentration of nanostructures in the pad area are engineered to maximize the bonding profile.
Thus, maximum performance is achieved.
[0087] One embodiment utilizes anchored nanoparticles onto the NWs/rGO and CNTs using a layer by layer (LBL) assembly process. In these structures, the metallic/rGO
NWs and CNTs will be decorated with metallic, silica-coated metal, and metal coated silica nanoparticle (NP) nanofillers, such as silver, silver/silica, and nickel NPs. Such structures enhance surface area, producing high performance conductive adhesives. As a result, a maximum bonding area and an optimal conduction path between two pads will be achieved.
[0088] Other embodiments are related to the combination of silica or polystyrene nanobeads and metal NPs, graphene nanowires, or CNTs, in a 3D assembly. Conductive nanoparticles, graphene NWs, and CNTs are diffused into the 3D silica or polystyrene crystal to create a

- 13 -vertical current path for selective bonding. During the bonding process, the silica itself acts as a mechanically robust material under pressure and temperature.
[0089] A few embodiments of this description are related to the embedment of as-formed nanostructures (porous structures, metal and rGO NWs, CNTs, metal, and silica coated NPs) into transparent and a mechanically flexible and thermally stable host medium.
[0090] A few embodiments of this description are related to controlling the temperature and pressure during the bonding process, to provide a strong bond.
[0091] The aim of this invention is to describe the applications of metal nanostructures for efficient and durable bonding between two substrates. Metal nanostructures currently play an important role in technology. Their unique chemical-physical properties has been leaded to research and development on metal-containing nanostructured materials resulting in wide utilization of metal nanostructures in industrial practices. Nanostructured metals with high cohesive energy have a high melting point, leading to extended component stability during bonding (correlating to improved reliability). The high surface activation energy of the metallic particles is crucial for robust bonding between two surfaces. The inventors should note that systems containing metal nanoparticles are particularly interesting because metal NP synthesis and surface chemical modification is simple. Here, all of process presented regarding metal nanostructure fabrication are high throughput processes conducted at low temperatures, and compatible with conventional semiconductor processes.
[0092] 2D and 3D metal nanostructures have superior properties, including unique morphological structures, large surface area and high electrical conductivity.
As shown in FIG.
IA 2D metallic textured structures are formed by combining nanomasking and etching.
Nanoparticles such as aluminum oxide (A1203), silica and polystyrene nanospheres or othe masks can be used as etch-masks. Reactive ion etching (RIE) using anisotropic plasma chemistry with high etching selectivity to metal, physical etching through a milling process, and a simple yet controlled wet etching process can be used to form metallic nanotextures.
The geometry and size of the textures can be adjusted by the size of the etch masks and etching conditions. This structure can be formed either on the receiver substrate or the micro device pads. During bonding, the surface texture can accommodate some height difference between different pads

- 14 -and/or micro devices. Moreover, it the surface texture create more surface area for more reliable bonding. FIG. 1B shows silver nanotextures realized using nanosphere masks and milling. The metal nanotextured structures can also be formed by polymer self-masking in a dry or wet etching processes.
[0093] In another embodiment, the surface texture is developed using template and deposition. In this method, a template is formed on the space between the templates is covered by conductive materials. The template can be removed or left on the surface.
As shown in FIG.
2, 3D spongy nanoporous and nanopores (random and ordered) are formed by nanotemplating followed by (single crystal) bonding material (e.g metal) deposition/growth using, PECVD, PVD, CVD, sputtering, printing, spin coating, etc (FIG. 2A), as well as electrochemical deposition and electroless plating (FIG. 2B) of a structural layer (e.g.
metals such as silver (Ag), nickel (Ni), Co, or metal alloys). In one case, Block-Copolymers (BCPs), Aluminum Anodic Oxide (AAO) are used as template. In the latter structures the nanotemplates are formed using (BCP), Aluminum Anodic Oxide AAO, and silica or polymer nanosphere (colloidal crystal). The template can be subsequently removed either chemically (for example, in dimethylforamide DMF), or through lift-off (in the case of silica templates). The shape, pitch and size of the nanoporous/nanopores can be adjusted by the size of the nanotemplate. FIG. 2C
shows the bonding of nonporous/nanopores structures between micro-device arrays and receiving substrate.
Here, the surfaces can be covered by other bonding or filler layers.
[0094] One method of accommodating surface roughness is to form porous bonding layer on top of the pads or micro-devices. While the porous layer has mechanical strength to hold the micro-device in place, the elasticity can compensate for the surface non-uniformity. Moreover, the elasticity can provide more tolerance for mechanical stress due to possible folding, rolling or pressure. Here, after forming the porous surface, other layers can be deposited to facilitate bonding between micro-device and the receiver pads. However, the purpose surface itself can be made of bonding materials such as Indium, Tin, Silver, etc In another embodiment, the templates are fully covered by the conductive layers (some opening can formed. The templates are removed by etching or other means leaving a 3D porous layer. The conductive layer can be deposited on the template after forming the template on the surface or the template can be

- 15 -covered by conductive layer prior forming into the surface. As shown in FIG.
3A in one approach for the formation of metal nanoporous using silica or polymer nanosphere template, the metal can be deposited by PVD and CVD methods following 3D template formation.
FIG. 3B
shows another approach which entails the use of a mixture of metal NPs, CNT, rGO nanowires (N Ws) and silica nanospheres to form a template. A 3D metal nanoporous structure will be released upon silica removal. In the third approach shown in FIG. 3C, core/shell silica nanaospheres with metallic shells form a 3D colloidal crystal template. An array of hollow metallic spheres will form following silica removal.
[0095] FIG. 4 shows upright arrays of nanostructures, including conic, needle-like nanostructures, pillars and nanowires, are formed on transparent conductive oxides (TCO) (ZnO, ITO, G1ZO, etc) and metals (Ag, Ni, etc). The structures can be fabricated as ordered array structures with desired size and pitch (FIG. 4A1, 4A2), or randomly formed in a high density arrangement (FIG. 4B). The number of nanostructures will be optimized for maximum vertical conduction. The structures can be formed using both mask or mask-less approaches using similar, but more controlled approaches, as explained here. In the former method, the shape, size, and the pitch (determined by the density of the nanostructures in the bonding area) are controlled by the size of the etch masks (patterned hard masks with photolithography, silica nanospheres, polystyrene nanobeads, etc.) and etching selectivity to the bonding material (TCO, or metal) using either an RIE or a milling process. The latter approach is achievable during an RIE process with self-masking (FIG. 4B1) or in a hydrothermal growth (FIG. 4B2). In such processes, the geometrical parameters of the nanostructures are controlled by the precursor/gas chemistry and hydrothermal/plasma condition. As-formed nanostructures can be overcoated with layers with good bonding properties to enhance the bonding quality.
[0096] In addition to top down etching, TCO NWs can be grown using the hydrothermal method at a low temperature compatible with most receiver substrate (e.g ¨150 C). The grown structures can be used as active bonding areas, or as supporting templates for desired metallic films such as Ag, Ni, Co, etc (FIG. 4B2). In this case, the array of nanowire is formed with materials that are compatible with low temperature process and have better mechanical strength (e.g zno). The surface of the nanowire is then can be covered by conductive and bonding layers.

- 16 -[0097] The various metal nanostructures mentioned in this disclosure such as nanocones, nanopillars, and nanowires can be produced using a wet chemical etch process such as selective metal nanoscale etch method (SMNEM). The wet chemical process provides high throughput and low temperature (<75 C) etching, which is compatible with conventional semiconductor processes. Dielectrophoresis-assisted growth can also be used to form metallic nanowires from an aqueous salt solution, such as silver and palladium.
[0098] Highly conductive graphene-based materials such as reduced graphene oxide (rGO) NWs and carbon nanotubes (CNTs) can be implemented as one-dimensional and vertical current paths for bonding (FIG. 5). rGO NWs can be fabricated through chemical reduction and CNTs are produced using CVD, laser ablation, and arc discharge methods. Vertically aligned (FIG. 5A) or randomly formed nanostructures (FIG. 5B) can be formed onto the substrate.
[0099] FIG. 6 shows the 3D stack of rGO sheets/foam/films decorated with in-situ grown ZnO nanopillars/nanowires can be realized by a direct freeze-drying and hydrothermal process.
The stacks can be formed randomly (FIG. 6A) or in a vertically aligned structure (FIG. 6B). The unique structure creates an interlocking, flexible, high performance bonding medium, which effectively reduces agglomeration of rGO while increasing the density and surface profile of the composite (FIG. 6C, 6D).
[00100] Metal nanoparticles/nanowires decorated rGO sheets/films/foams are mutually-supporting porous structures that can be prepared in situ by annealing self-assembled graphene oxide (GO) NWs coated with metallic precursors in an inert atmosphere (FIG 7A). 3D
stack of metal nanoparticles (FIG 7B) or nanowires (FIG 7C) decorated rGO also create a bonding material with enhanced interlocking and surface profile.
[00101] 3D scaffolds of stand-alone nanowires and nanofibers or decorated with metal NPs are another examples of 3D nanostructures with improved interlocking properties and extremely large surface areas. They can be formed using aligned (FIG 8A) or randomly (FIG
8B1) crossed metallic nanowires, 3D metallic and polymer, CNTs, and carbon nanofibers.
Carbon nanofibers can be electro-spun (electrospinning) onto the substrate, followed by chemical (or physical) deposition of metals, or chemical deposition of metal nanoparticles and decoration of nanofibers with conductive NPs (FIG 8B2). This process leads to rapidly improved conduction. Gold and silver nanostructures are synthesized by simply immersing the (carbon, polymer, DNA, etc) nanofibers (with some surface functional groups for reaction with metal precursors) into an aqueous solution of metal ion precursors. While the metal ions are locally reduced on the surface of the nanofibers, large metal nanoparticles form, and smooth carbon (or polymer)¨metal hybrid nanostructures forms. FIG 8C shows the interlocked bonding of 3D
scaffold of randomly crossed nanowires/nanofibers decorated with metal nanoparticles between micro-device arrays and receiving substrates.
[00102]
Branch-type nanowires with improved interlocking properties, including hierarchical and comb-like nanostructures with a backbone (such as Sn02) and branches (such as Zn0), can be fabricated in a process that combines carbothermal reduction with hydrothermal growth (FIG 9A, B). The hybrid Sn02¨ZnO nanowires can also be produced via a two-step carbothermal reduction method at low pressure (around 1Pa). It can also be produced using a single step carbothermal reduction based on the catalyst-assisted vapour-liquid-solid (VLS) mechanism. In this synthetic process, activated carbon powder acts as a reducing agent, while metal nanoparticles or nanoclusters serve as nucleation seeds. The metal nanoparticle seeds determine the growth direction, interfacial energy and diameter of the resultant one-dimensional metal oxide nanowires. In this facile synthesis method, the morphology and properties of nanowires are mainly controlled by growth parameters such as temperature, thickness of the catalyst layer, rate of carrier gas flow, and distance between the source and the substrate. The diameter of the backbone nanowire will be in the range of few tens of nanometers (-50-100nm) while the branched nanowires have slightly smaller diameters (-10-30nm).
Metals such as silver can be evaporated onto the as-formed branched NW structure, covering it with a metallic layer.
3D scaffold of such structures with high interlocking bonding properties can be produced by stacking the aligned or randomly-formed hierarchical and comb-like nanostructures (FIG
9C1-C3). The resulting 3D structure can be decorated with metallic nanoparticles to further improve the surface bonding area. The bonding structures utilizing these architectures are presented in FIG. 9D1-D3.

[00103] These nanowires claimed in [00101] can be either directly formed onto the pads of the micro devices and/or receiving substrate, or they can be transferred to the pads and attached to the surface by deposition of thin layers and selection of adhesive materials.
[00104] Branch-type nanowires with improved interlocking properties with a nanowire/nanocone backbone (metal, TCO) and branches (metal, TCO) can also be formed through consecutive self-assembly of etch masks (nano hard masks, silica, polymer beads, etc) and etching (dry, wet, milling) (FIG 10).
[00105] A precisely controlled nanomesh from bonding materials (e.g.
metal films) can be fabricated using nanosphere lithography to pattern bonding materials (e.g. silver thin films), forming 2D hexagonal nanohole arrays with excellent uniformity, high conductivity and good transparency (FIG 11). Silica or polymer nanospheres with appropriate surface functional groups can be assembled in monolayers via simple and scalable drop-casting, spin-coating, vertical dip coating, or Langmuir Blodgett Troughs methods. Next, the size of silica or polymer beads are reduced via etching. Etching is performed under fluorine, mixture of fluorine-oxygen (CF4/02), or oxygen gas (for the case of polymer beads), using moderate plasma condition for few minutes (5-10 minutes). The metal is then deposited onto the structure.
Metallic nanomesh will form after lift-off of nanobeads, achieved with simple ultrasonication or chemical etching.
The size and pitch of the metal nanomesh can be engineered by the initial size of the selected nanobeads and the post-etching step.
[00106] 3D Nanoporous metal nanostructures can be formed with silica nano-templating and subsequent electroplating (FIG 2B3). First, the metal layer is deposited on the substrate. Then, silica or polymer nanobeads with the desired size will be assembled onto the surface, forming a monolayer template. The size of the nanobeads are optimized by plasma dry etching, creating openings. Next, the metal layer electroplated onto the openings. The beads are removed in a chemical etch process that results in a 3D nanoporous metal nanostructures with improved surface area.
[00107] Metallic nanoparticles (NPs) can be anchored onto all of the above mentioned nanostructures, including the NWs, CNTs, rGO, 3D scaffolds presented here, using a layer by layer (LBL) assembly process, dip coating or drop-casting. These structures will be decorated with metallic or silica coated-metal nanofillers such as silver, silver/silica, nickel, Ag-Cu nanoparticles. The nanofillers can be grown onto the nanostructures in a CVD
process, hydrothermal or carbothermal growth methods, or simple drop-casting from monodispersed metal colloidal solutions onto the as-formed nanostructures. The NP anchored nanostructures enhance surface area, producing high performance conductive adhesives. As a result, the optimum conduction between two pads and maximum bonding area will be achieved.
[00108] The combination of silica nanospheres or polystyrene nanobeads and nanostructures with one directional current path (e.g. metal/TCO NWs, graphene nanowires or CNTs, etc) can form a 3D assembly that is advantageous for selective bonding (where Cartridges with arrays of micro-LED devices are used) (FIG 12A). The silica component makes this structure mechanically resilient to bonding pressure and temperature.
Metallic nanoparticles can also be added to the structure to increase the bonding surface area (FIG
12B). Conductive metallic nanowires/nanoparticles, graphene NWs and CNTs can be diffused into a 3D silica or polystyrene crystal by simple drop-casting. This structure can create vertical current paths for selective bonding.
[00109] In the simplest approach presented in this proposal, core metal nanoparticles such as Ag, Ni, etc (FIG 13A), core/shell nanoparticles (silica coated silver, Ag/silica, etc) (FIG
13B), and alloyed nanoparticles (Ag-Cu, etc) will be incorporated into thermally and mechanically stable transparent host mediums such as polyimide, SU8, silicone, UV adhesives, and bonding epoxies (FIG 14). This host medium is curable under light, thermal, or mechanical forces. In this approach, selection of nanoparticles with appropriate surface functional groups is critical for producing a highly conductive anisotropic layer. Ag nanoparticles with self-assembled monolayers (SAMs) of carboxyl and thiol groups enhance interface properties of the NPs and improve conduction. The NP concentration in the medium is another key parameter that must be optimized for the minimum-close to zero lateral conduction.
Despite its simplicity, this approach is highly scalable.
[00110] Due to the physical geometry and high density of all of the above structures, they can produce an anisotropic bonding medium without being embedded in a surrounding host.

They create self-standing metal nanostructures with active surfaces (catalytic properties), high conduction properties in the vertical direction, and high surface area, while showing sufficient resistance to the high pressure and temperature applied during bonding.
[00111] The structures presented in here can be covered by an overcoat layer to enhance the bonding properties (FIG 15).
1001121 To provide extra mechanical resistance during bonding, specifically for the cases where the density of the said porous/textures nanostructures, NWs, CNTs and 3D scaffolds are low , the nanostructures will be embedded into a mechanically transparent, flexible and thermally stable host medium to act as a curing agent. The use of stable host mediums such as polyimide, SU8, silicone, UV adhesives, and bonding epoxies is also beneficial in cases where nanoparticles are only used as fillers (core: Ag, Ni, etc and core/shell structures: Ag/silica), or alloys Ag-Cu. The curing agent can be applied after (FIG 15A) or before (FIG
15B) alignment and connection of the receiver substrate and micro device.
1001131 The light intensity, temperature, pressure, and mechanical forces during bonding will be controlled and adjusted for different structures. These parameters will be adjusted depending on the porosity and density of the structures, ensuring the creation of anisotropic, conductive, and strong bonds.

Claims

WHAT IS CLAIMED IS:

1. A bonding structure where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, and at least one of the said surfaces is textured after depositing some layers on the surfaces.

2. A bonding process based on claim 1 where nanoparticle is dispersed between the two said surface.

3. A bonding process based on claim 1 where soldering layers or bonding agent is deposited on at least one of the said surfaces.

4. A bonding process where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, at least one of the said surface is covered by nanowires, and the area between nanowires is filed by bonding agent.

5. The bonding agent in claim 4 that can be solvent filled with conductive nanoparticles.

6. A bonding process where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, and at least one of the said surface is covered by non-conductive nanowires.

7. The said nanowires in claim 6 where at least one of them is covered by a conductive layer.

8. The said nanowires in claim 6 where they are used as support structure for other conductive structures such as nanowire, conductive sheets, and nano particles.

9. The bonding process in claim 6 where a bonding agent can be used to fill the space between the nanowires.

10. The bonding process of claim 6 where some of nanowires act as bonding agent holding the two surfaces together.

11. A bonding process where the surface of at least one pad on the receiver substrate is electrically bonded to a surface of an optoelectronic microdevice, at least one of the said surface is covered by scaffold structure

12. The scaffold structure of claim 11 where it is formed by depositing at least one layer on a template.

13. The scaffold structure of claim 11 where a preformed scaffold is transferred to the said surface after a adhesion layer added to the surface.

14. The scaffold structure of claim 11 where a preformed scaffold is transferred to the said surface and adhesion layer is deposited after the said transfer.