CA2943174C - Communication method and communication device - Google Patents

Abstract

In a communication method according to one embodiment of the present invention a code word, which is generated on the basis of quasi-cyclic parity check codes including repeat-accumulate quasi-cyclic low-density parity check codes, is subjected to a cyclic block permutation wherein the order of cyclic blocks in this code word is rearranged, and each bit of the code word that has undergone the cyclic block permutation is mapped to a constellation point of a non-uniform constellation, thereby improving reception performance.

Description

DESCRIPTION
COMMUNICATION METHOD AND COMMUNICATION DEVICE
TECHNICAL FIELD

[0002]
The present disclosure relates to a digital communication field. More specifically, the present disclosure relates to bit interleavers and bit de-interleavers in a bit-interleaved coding and modulation (BICM) system using quasi-cyclic low-density parity-check codes (QC LDPC codes) and quadrature amplitude modulation (QAM).
BACKGROUND ART

[0003]
In these years, a lot of transmitters are proposed, and in the transmitters, bit interleavers are disposed between encoders that encode information bits and output codeword bits, and constellation mappers that map the codeword bits to constellations and that output modulation symbols (for example, refer to PTL1).
Citation List Patent Literature

[0004]
PTL 1: European Patent Publication No. 2552043 Non- Patent Literature

[0005]
NPL 1: DVB-S2 standard: ETSI EN 302 307, V1.2.1 (August, 2009) SUMMARY OF THE INVENTION

[0006]
A communication method according to one aspect of the present disclosure is a data communication method for performing data communication in a digital communication system using a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code. The communication method includes an interleaving step of executing a cyclic block permutation for a codeword generated based on the quasi-cyclic parity-check code, where the codeword includes a sequence of N cyclic blocks, each of the N cyclic blocks includes Q
bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword, and a constellation mapping step of mapping each of the bits of the codeword for which the cyclic block permutation is executed to a constellation point of a non-uniform constellation. In the communication method, the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword.
According to a further aspect of the disclosure, there is provided a communication method which comprises: executing a cyclic block permutation for a codeword generated based on a quasi-cyclic low density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the codeword includes N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword; mapping each of the bits of the codeword for which the cyclic block permutation is executed to any one of constellation points of a non-uniform constellation, the mapping including section interleaving, generating each constellation word from bits in B cyclic blocks of the codeword for which the cyclic block permutation is executed, where B is a bit number of the QAM symbol, the B cyclic blocks thereby forming the respective section, the section interleaving being performed by writing all bits of one section of the codeword for which the cyclic block permutation is executed row-by-row in a matrix and reading these bits column-by-column from the matrix; and transmitting the mapped codeword, wherein the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword, wherein the code rate of the quasi-cyclic low-density parity-check code is equal to 7/15, and the cyclic block permutation is defined according to the following table:

j-th j)-th j-th (j)-th j-th x (j)-th .i-th jr 0-th block of block of block of block of block of block of block of block of Group-wise Grotp-wise Group-wise Group-wise Group-vise Group-wise Group-wise Group-wise Interleaver Interleaver Interleaver Interleaver Interleaver Interleaver Interleaver Interleaver output input output irput output input output input 6 Ill 51 164 96 142 ¨ 141 - 12

7 62 52 168 97 108 142 56 a 42 53 163 98 69 143 152 _ 15 120 60 30 _ 105 11 , 150 32 _ _ wherein the j-th block of Group-wise Interleaver output indicates the index of the cyclic blocks within a codeword after the cyclic blocks are permutated, and wherein the Tr(j)-th block of Group-wise Interleaver input indicates the index of the cyclic blocks within the codeword before the cyclic blocks are permutated, wherein N is equal to 180, and Q is equal to 360.
According to a further aspect of the disclosure, there is provided a communication device which comprises: interleaving circuitry for executing a cyclic block permutation for a codeword generated based on a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the codeword includes N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword; constellation mapping circuitry formapping each of the bits of the codeword for which the cyclic block permutation is executed to any one of constellation points of a non-uniform 4096 QAM
constellation, the mapping including section interleaving, generating each constellation word from bits in B cyclic blocks of the codeword for which the cyclic block permutation is executed, where B is a bit number of the QAM symbol, the B cyclic blocks thereby forming the respective section, the section interleaving being performed by writing all bits of one section of the codeword for which the cyclic block permutation is executed row-by-row in a matrix and reading these bits column-by-column from the matrix; and transmitting circuitry for transmitting the mapped codeword, wherein the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword, wherein the code rate of the quasi-cyclic low density parity-check code is equal to 7/15, and the cyclic block permutation is defined according to the following table:

j-th Jr (j)-th j-th (j)-th j-th (j) -tb j-tb (j)-th block of block of block of block of block of block of block of block of Grap-wi se Grow-wise Group-use Group-wise Group-wise Grap-1 i se Group-rise Group-vise inter leaver Inter I eaver Inter I eaver Inter I eager I nte rleaver Inter leaver Interleaver I nterleaver output input output irput output input output input

8 42 53 163 98 69 143 152

9 102 54 170 99 7 144 20 INEUI111111111111ffilli 91 IREINIIIHNI 167 126 wherein the j-th block of Group-wise Interleaver output indicates the index of the cyclic blocks within the codeword after the cyclic blocks are permutated, and wherein the Tr(j)-th block of Group-wise Interleaver input indicates the index of the cyclic blocks within the codeword before the cyclic blocks are permutated, wherein N is equal to 180, and Q is equal to 360.
BRIEF DESCRIPTION OF DRAWINGS
[0007]
FIG. 1 is a block diagram illustrating one configuration example of a transmitter including general bit-interleaved coding and modulation (BICM).
FIG. 2 is a block diagram illustrating one configuration example of a BICM
encoder of FIG. 1.
FIG. 3 is a diagram illustrating one example of a parity-check matrix of a quasi-cyclic low-density parity-check code with M = 6, N = 18, Q = 8.
FIG. 4 is a diagram illustrating one example of a table that defines repeat-accumulate quasi-cyclic low-density parity-check codes.
FIG. 5 is a diagram illustrating an information part of the parity-check matrix for a first bit in each cyclic block of the information part for the repeat-accumulate quasi-cyclic low-density parity-check codes of FIG. 4.
FIG. 6 is a diagram illustrating a full parity-check matrix including entries for all information bits and a staircase parity part for the parity-check matrix of FIG. 5.
FIG. 7 is a diagram illustrating a matrix representing quasi-cyclic structure of the parity-check matrix of FIG. 6.
FIG. 8A is a diagram illustrating a 4-QAM constellation.
FIG. 8B is a diagram illustrating a 16-QAM constellation.
FIG. 8C is a diagram illustrating a 64-QAM constellation.
FIG. 9A is a block diagram illustrating configuration of a 4-QAM mapper.
FIG. 9B is a block diagram illustrating configuration of a 16-QAM mapper.
FIG. 9C is a block diagram illustrating configuration of a 64-QAM mapper.
FIG. 10 is a schematic view for illustrating different robustness levels in an 8-PAM symbol using Gray encoding.

FIG. 11 is a diagram illustrating one example of a 4096-QAM constellation based on 1D-64 NU-PAM designed for a specific SNR.
FIG. 12A is a diagram for illustrating one example of the BICM encoder of FIG.

based on DVB-NGH.
FIG. 12B is a diagram for illustrating one example of the BICM encoder of FIG.

based on DVB-NGH.
FIG. 12C is a diagram for illustrating one example of the BICM encoder of FIG.

based on DVB-NGH.
FIG. 13A is a diagram for illustrating one example of the BICM encoder of FIG.

based on ATSC 3Ø
FIG. 13B is a diagram for illustrating one example of the BICM encoder of FIG.

based on ATSC 3Ø
FIG. 13C is a diagram for illustrating one example of the BICM encoder of FIG.

based on ATSC 3_0 FIG. 14 is a block diagram illustrating one configuration example of a bit interleaver according to an exemplary embodiment of the present disclosure.
DESCRIPTION OF EMBODIMENT
[0008]
<<Items confirmed until the inventors have achieved the present disclosure>>
FIG. 1 is a block diagram illustrating one configuration example of a transmitter including general bit-interleaved coding and modulation (BICM).
[0009]
Transmitter 100 illustrated in FIG. 1 includes input processing unit 110, BICM
encoder 120, orthogonal frequency-division multiplexing (OFDM) modulator 130, up-converter 140, radio frequency (RF) amplifier 150, and antenna 160.

[0010]
Input processing unit 110 formats input-bit-streams into blocks of a determined length called baseband frames. BICM encoder 120 converts the baseband frames into data-streams including a plurality of complex values. OFDM modulator 130 uses, for example, OFDM modulation, and typically performs time interleaving and frequency interleaving for improving diversity. Up-converter 140 converts digital baseband signals into analog RF signals. RF amplifier 150 performs power amplification of the analog RF signals, and outputs the analog RF signals to antenna 160.

[0011]

FIG. 2 is a block diagram illustrating one configuration example of BICM
encoder 120 of FIG. 1.

[0012]
BICM encoder 120 illustrated in FIG. 2 includes low-density parity-check (LDPC) encoder 121, bit interleaver 122, and quadrature amplitude modulation (QAM) mapper 124.

[0013]
LDPC encoder 121 encodes input blocks, that is, the baseband frames, and outputs LDPC codewords to bit interleaver 122. Bit interleaver 122 permutates bits of each LDPC codeword, and then QAM mapper 124 maps the bits of each LDPC
codeword to complex cells. QAM mapper 124 maps the permutated bits of each LDPC
codeword to the complex cells by using QAM.

[0014]
Each component of BICM encoder 120 in FIG. 2 will be described in more detail below.

[0015]
First, LDPC encoder 121 will be described.

[0016]
LDPC encoder 121 encodes the baseband frames by using a specific LDPC
code. The present disclosure is particularly designed for LDPC block codes having staircase parity structure which is employed in the DVB-S2, DVB-T2, DVB-C2 standards, and for variations of Raptor-like LDPC codes. More details will be described below.

[0017]
The LDPC block code is a linear error-correcting code that is fully defined by its parity-check matrix (PCM). This PCM is a binary sparse matrix representing connection of the codeword bits (also referred to as bit nodes or variable nodes) to parity checks (also referred to as check nodes). Columns and rows of the PCM
correspond to the variable nodes and check nodes, respectively. Connection of the variable nodes to the check nodes are represented by "1" entries in the PCM
matrix.

[0018]
Quasi-cyclic low-density parity-check (QC LDPC) codes have structure especially suitable for hardware implementation. In fact, most if not all standards today use the QC LDPC codes. The PCM of such a QC LDPC code has special structure having cyclic matrices (or also referred to as cyclic). The cyclic matrix is a square matrix in which each row is a cyclic shift of a previous row by one matrix element, and may have one or more folded diagonals.

[0019]
A size of each cyclic matrix is Q x Q (Q rows and Q columns), and Q is referred to as a cyclic factor of the QC LDPC code. This quasi-cyclic structure makes it possible to process Q check nodes in parallel. Therefore, the quasi-cyclic structure is clearly advantageous for efficient hardware implementation.

[0020]
The PCM of a QC LDPC code is a matrix having Q x M rows and Q x N
columns, and the codewords each include N blocks including Q bits. In addition, M is a number of blocks in a parity part. Note that a Q-bit block is referred to as a quasi-cyclic block or simply a cyclic block throughout this document, and is abbreviated as QB.

[0021]
FIG. 3 is a diagram illustrating one example of the PCM of the QC LDPC code with M = 6, N = 18, Q = 8. The PCM includes cyclic matrices having one or two folded diagonals. This QC LDPC code encodes a block of 8 x 12 = 96 bits to a codeword of 8 x 18 =144 bits, and thus a code rate is 2/3. Note that in FIG. 3, FIG. 5 to FIG. 7, a black square is a matrix element of a value "1," and a white square is a matrix element of a value "0."

[0022]
The QC LDPC code with the PCM illustrated in FIG. 3 belongs to a special family of QC LDPC codes referred to as repeat-accumulate quasi-cyclic low-density parity-check (RA QC LDPC) codes. The RA QC LDPC codes are known for ease of encoding, and are employed in a very large number of standards such as the second generation DVB standards (DVB-S2, DVB-T2, DVB-C2).

[0023]
Next, the following describes definition of the RA QC LDPC codes used in the standard family of DVB-S2, DVB-T2, DVB-C2, as described in Section 5.3.2 and Appendixes B and C of NPL1 of the DVB-S2 standard (DVB-S2 standard: ETSI EN

307: V1.2.1 (August, 2009)). In this standard family, cyclic factor Q is equal to 360.

[0024]
Each LDPC code is fully defined by a table containing, for a first bit of each cyclic block in an information part, indices of each check node to which the first bit is connected. Note that the indices of each check node start with zero. These indices are referred to as "addresses of the parity bit accumulators" in the DVB-S2 standard.
FIG. 4 illustrates the table for the LDPC code one example of which is illustrated in FIG.
3.

[0025]
FIG. 5 is a diagram illustrating the information part of the PCM for a first bit in each cyclic block of the information part for the RA QC LDPC code of FIG. 4.

[0026]
The full PCM includes entries for all information bits and the staircase parity part, and is illustrated in FIG. 6.

[0027]
For each bit other than the first bit of each cyclic block in the information part, the indices of each check node to which the bit is connected are calculated by Equation 1 described below.

[0028]
[Equation 1]
== (io -F x )%(Q x M )

[0029]
where q is a bit index (0, Q - 1) within one cyclic block, iq is a check node index for bit q, and io is one of the check nodes to which the first bit of the cyclic block in the table of FIG. 4 is connected. M is a number of cyclic blocks in the parity part, and is 6 in the example of FIG. 6, and Q is a number of bits of one cyclic block and is 8 in the example of FIG. 6. Q x M is a number of parity bits, and is 8 x 6 = 48 in the example of FIG. 6. % is a modulo operator. Note that for example, for the cyclic block QB of "1," calculation by Equation 1 described above is performed on each of io= 13, 24, 27, 31,47 in the case of FIG. 4.

[0030]
In order to represent the quasi-cyclic structure of the PCM in FIG. 6, a permutation expressed by Equation 2 described below is applied to the rows of the PCM in FIG. 6, and this application of the permutation results in the matrix illustrated in FIG. 7.
[00311 [Equation 2]

j =(i%M)xQ + floor (1 I M) [0032]
where i and j are indices starting with zero. i is an index of the check nodes before permutation, and j is an index of the check nodes after permutation. M
is a number of cyclic blocks in the parity part, and is 6 in the example of FIG. 6, and Q is a number of bits of one cyclic block, and is 8 in the example of FIG. 6. % is a modulo operator, and floor(x) is a function that outputs a maximum integer equal to or less than x.
[0033]
Since this permutation by Equation 2 is not applied to the bits, code definition is not changed. However, the parity part of the PCM resulting from this permutation by Equation 2 is not quasi-cyclic. In order to make the parity part quasi-cyclic, a special permutation expressed by Equation 3 described below needs to be applied only to the parity bits.
[0034]
[Equation 3]
j = (i%Mx M + floor (i I Q) [0035]
where i and j are indices starting with zero, i is an index of the parity bits before permutation, and j is an index of the parity bits after permutation. M is a number of cyclic blocks in the parity part, and is 6 in the example of FIG. 7, and Q is a number of bits of one cyclic block, and is 8 in the example of FIG. 7. % is a modulo operator, and floor(x) is a function that outputs a maximum integer equal to or less than x.
[0036]
This permutation by Equation 3 applied only to the parity bits changes the code definition.
[0037]
Note that the permutation by Equation 3 applied only to the parity bits is referred to as a parity permutation or parity interleaving throughout this document.
However, the parity permutation or the parity interleaving will be regarded as part of the LDPC
encoding process hereinafter.

[0038]
The next-generation ATSC 3.0 standard for terrestrial reception of digital video service is currently under development, and will define 1/15, 2/15, ..., 13/15 as code rates, and 16200 code bits and 64800 code bits as code lengths.
[0039]
Next, QAM mapper 124 will be described.
[0040]
QAM mapper 124 maps the bit of the codeword to one point of a plurality of points in a QAM constellation by independently modulating real components and imaginary components by using pulse-amplitude modulation (PAM). Each point in the QAM constellation corresponds to one combination of the bits. FIG. 8A to FIG.
8C are diagrams illustrating three types of QAM constellations relevant to the present disclosure, a 4-QAM constellation, a 16-QAM constellation, and a 64-QAM
constellation.
[0041]
Here, the real components and the imaginary components use the same type of PAM. The real components and the imaginary components use 2-PAM, 4-PAM, 8-PAM
in the 4-QAM constellation, the 16-QAM constellation, and the 64-QAM
constellation, respectively.
[0042]
The present disclosure also assumes that the PAM mapping uses Gray encoding, as illustrated from FIG. 8A to FIG. 8C.
[0043]
FIG. 9A, FIG. 98, FIG. 9C are blocks illustrating configurations of the QAM
mappers corresponding to the constellations of FIG 8A, FIG. 8B, FIG. 8C, respectively.
4-QAM mapper 124A of FIG. 9A includes two independent 2-PAM mappers 124A-1, 124A-2 each of which encodes one bit. 16-QAM mapper 124B of FIG. 9B includes two independent 4-PAM mappers 1248-1, 124B-2 each of which encodes two bits.
64-QAM mapper 124C of FIG. 9C includes two independent 8-PAM mappers 1240-1, 124C-2 each of which encodes three bits.
[0044]
The bits encoded in a PAM symbol have different robustness levels, in other words, different reliability when the PAM symbol received in a receiver is demapped.
This is a well known fact, and FIG. 10 illustrates a schematic view for illustrating the different robustness levels in an 8-PAM symbol using Gray encoding.
[0045]
The different robustness levels result from a fact that a distance between a portion with a bit value of zero and a portion with a bit value of one is different for each of three bits b1, b2, b3. The reliability of a bit is proportional to an average distance between the portion with a bit value of zero and the portion with a bit value of one. In the example illustrated in FIG. 10, bit b1 has lowest reliability, bit b2 has second lowest reliability, and bit b3 has highest reliability.
[0046]
In order to increase a transmission rate of bits, that is, BICM capacity, non-uniform constellations have been introduced in the DVB-NGH standard, which is the first time. This increase is achieved by changing an interval between PAM
constellation points, and so-called 1D-NU-PAMs are obtained. Next, a square non-uniform constellation is obtained from the 1D-NU-PAMs.
[0047]
In ATSC 3.0, this idea is further improved by introducing two-dimensional non-uniform constellations, so-called 2D-NUCs. The 2D-NUCs involve increased demapping complexity at the receiver because An in-phase (I)-component and a quadrature (Q)-component of the received complex cells are dependent on each other.
Higher demapping complexity is considered acceptable in ATSC 3.0 up to a constellation order of 1024. Moreover, only PAM based constellations for 4096-QAM
constellations are determined to be allowed. FIG. 11 illustrates one example of a 4096-QAM constellation based on 1D-64 NU-PAM.
[0048]
A number of bits in the QAM symbol is represented by B. Since the QAM
constellations are square, B is an even number. Further, since a square QAM
symbol includes two PAM symbols of the same type, the bits encoded in the QAM symbol can be grouped into pairs having the same robustness levels. The bits encoded in the QAM symbol are referred to as a constellation word.
[0049]
Next, bit interleaver 122 will be described.
[0050]
Typically, the bits of an LDPC codeword have different importance levels, and the bits of a constellation have different robustness levels. Direct, that is, non-interleaved mapping of the LDPC codeword bits to the QAM constellation bits does not achieve optimal performance. In order to prevent such performance reduction, the codeword bits need to be interleaved before the codeword bits are mapped to constellations.
[0051]
For this purpose, bit interleaver 122 is provided between LDPC encoder 121 and QAM mapper 124, as illustrated in FIG. 2. Careful designing of bit interleaver 122 can achieve an optimal relationship between the bits of the LDPC codeword and the bits encoded by the constellation, and leads improved performance. Typically, evaluation criterion of the performance is a bit error rate (BER) or a frame error rate (FER) as a function of a signal-to-noise ratio (SNR).
[0052]
The different importance levels of the bits of an LDPC codeword result firstly from a fact that a number of parity checks (check nodes) is different in some of the bits.
The larger the number of the parity checks (check nodes) connected to a codeword bit (variable node) is, the more important the bit is in iterative LDPC decoding processing.
[0053]
Further, the different importance levels of the bits of the LDPC codeword results secondly from a fact that the variable nodes have different connectivity to the cycles in the Tanner graph representation of the LDPC code. Thus, the importance levels of the bits may be different even when the number of the parity checks (check nodes) connected to the codeword bits of the LDPC codeword is the same number in each of the bits.
[0054]
These ideas are well known in the art. As a general rule, the larger the number of the check nodes connected to a variable node is, the larger the importance level of the variable node is.
[0055]
Particularly, in the case of QC LDPC codes, all bits included in a cyclic block of Q bits have the same importance level because the number of the parity checks (check nodes) connected to each of the bits is the same number, and connectivity to the cycles in the Tanner graph representation is the same.
[0056]
Next, a method for mapping the bits of a QC LDPC codeword to constellation words will be described. This mapping is performed by bit interleaver 122 in FIG. 2.
Note that this method for mapping is disclosed in PTL1 (EP11006087.8). While (EP11006087.8) relates to a case where a number of transmission antennas is any number T, the following describes a case relevant to the present disclosure, that is, a case where number of transmission antennas T is one.
[0057]
According to PTL1 (EP11006087.8), the bits of a QC LDPC codeword are mapped to constellation words such that (i) each constellation word is made of bits in B/2 cyclic blocks of the QC
LDPC
codeword, and (ii) each pair of constellation word bits that are encoded in the same QAM
symbol and that have the same robustness level is made of bits in the same cyclic block.
[0058]
Particularly, the Q x B/2 bits of the B/2 cyclic blocks are mapped to 0/2 spatial-multiplexing blocks. In this case, the B/2 cyclic blocks are referred to as a section.
[0059]
FIG. 12A to FIG. 12C are diagrams for illustrating one example of BICM encoder 120 of FIG. 2.
[0060]
FIG. 12A illustrates arrangement of 24 cyclic blocks with four sections. In the example of FIG. 12A, a number of cyclic blocks per section is B/2 = 12/2 = 6.
[0061]
FIG. 12B is a diagram illustrating one example of structure of a pathway from bit interleaver 122 to QAM mapper 124 (including one pair of PAM mappers 124-1, 124-2) in BICM encoder 120 in FIG. 2 based on DVB-NGH.
[0062]
The LDPC codeword generated by LDPC encoder 121 in FIG. 2 is fed to bit interleaver 122 in FIG. 12B. Bit interleaver 122 is six cyclic blocks per section. Note that processing is performed by bit interleaver 122 and QAM mapper 124 in FIG.
12B (a pair of PAM mappers 124-1, 124-2 are included) for each section in FIG. 12A.
Bit interleaver 122 permutates the fed bits, and then arranges the permutated bits to the Date Recue/Date Received 2021-07-09 real part and the imaginary part of the corresponding constellation words. The pair of PAM mappers 124-1, 124-2 map bits (b1, Re, b2, Re, ¨, b6, Re) to a real component (Re) of complex symbol s1, and map bits (b1,im, b2,im,....b6 m) to an imaginary component (Im) of complex symbol Si by using the 64-PAM constellation.
[0063]
FIG. 120 is a diagram for illustrating bit permutation executed by bit interleaver 122 in FIG. 12B. As illustrated in FIG. 12C, bit interleaver 122 executes processing equivalent to writing all bits of one section of the codeword row-by-row in a matrix, and to reading the written bits column-by-column from the matrix. Note that this matrix is of B/2 rows and Q columns.
[0064]
FIG. 13A to FIG. 13C are diagrams for illustrating other examples of BICM
encoder 120 of FIG. 2. FIG. 13A to FIG. 13C are similar to FIG. 12A to FIG.
12C, respectively, except that FIG 13A to FIG 13C illustrate the arrangement based on ATSC
3Ø
[0065]
FIG. 13A illustrates arrangement of 24 cyclic blocks with two sections. Unlike the case of FIG. 12A, in the example of FIG. 13A, a number of cyclic blocks per section is bit number B of the QAM symbol, and is 12 in the example of FIG. 13A.
[0066]
FIG. 13B is a diagram illustrating one example of structure of a pathway from bit interleaver 122 to QAM mapper 124 of BICM encoder 120 in FIG 2 based on ATSC
3Ø
[0067]
The LDPC codeword generated by LDPC encoder 121 in FIG. 2 is fed to bit interleaver 122 in FIG. 13B. Bit interleaver 122 is 12 cyclic blocks per section. Note that processing is performed by bit interleaver 122 and QAM mapper 124 in FIG.
13B for each section of FIG. 13A. Bit interleaver 122 permutates the fed bits. QAM
mapper 124 maps bits (bo, 131, b11) to complex symbol s1 by using the 4096-QAM
constellation.
[0068]
FIG. 13C is a diagram for illustrating bit permutation executed by bit interleaver 122 in FIG. 13B. As illustrated in FIG. 130, bit interleaver 122 executes processing equivalent to writing all bits of one section of the codeword row-by-row in a matrix, and to reading the written bits column-by-column from the matrix. Note that this matrix is of B rows and Q columns.
[0069]
EXEMPLARY EMBODIMENT
As described above, the different cyclic block of a determined LDPC code may have a different importance level because the importance level of a bit is dependent on the number of check nodes connected to the bit. Thus, improvement in transmission performance may be achieved by matching the importance level of the cyclic block with robustness of the bit of the constellation word to which this cyclic block is mapped.
Particularly, the bit of the cyclic block with the highest importance level is mapped to the bit of the constellation word with the strongest robustness. Conversely, the bit of the cyclic block with the lowest importance level is mapped to the bit of the constellation word with the weakest robustness.
[0070]
FIG. 14 is a block diagram illustrating one configuration example of the bit interleaver according to an exemplary embodiment of the present disclosure. In the example of FIG. 14, the LDPC codeword includes N = 12 cyclic blocks QB1, 0B2, ..., 0B12 which each include Q = 8 bits.
[0071]
In the bit interleaver, in order to permutate the cyclic blocks within the codeword without affecting a sequence of the bits within each cyclic block in a first stage, a cyclic block permutation (QB permutation) is executed for the codeword. This processing in the first stage is performed by cyclic block permutation unit 210.
[0072]
In a second stage, in order to permutate the bits within the cyclic blocks, an intra-cyclic block permutation (intra-QB permutation) is executed for the cyclic blocks.
This processing in the second stage is executed by intra-QB permutation units 220-1 to 220-12. Note that the second stage may not exist.
[0073]
In a third stage, after the first stage and the second stage are executed, the bits of each cyclic block of the codeword are mapped to the constellation word.
This third stage can be implemented by dividing the codeword into a plurality of sections and performing mapping to the constellation word for each section (section permutation).
For example, the third stage is realized by disposing an interleaver (section interleaver) that has a function equivalent to bit interleaver 122 described with reference to FIG. 13A

to FIG. 13C, in a subsequent stage of the intra-QB permutation unit.
[0074]
The inventors have found that improvement in communication performance for a determined LDPC code is achieved by optimizing the cyclic block permutation, that is, by selecting the cyclic block permutation that matches the constellation bits of different reliability with the cyclic blocks of different importance levels.
[0075]
However, the mapping of the cyclic blocks to the constellation word bits is not straightforward. Since no analytical solution has been known so far, finding an optimized cyclic block permutation is very time-consuming work. A method used for finding the optimal cyclic block permutation disclosed in the present disclosure includes the following steps, and is applied to each of different constellations and different code rates.
[0076]
In a preliminary step, a very huge number (1e4, 1e5) of cyclic block permutations are generated randomly under no constraint. Monte-Carlo simulations are executed for these cyclic block permutations by using blind demapping and iterative demapping in order to determine a threshold signal-to-noise ratio (SNR) at a determined target value of a block error rate (BLER). The cyclic block permutation with the lowest threshold SNR, that is, with the best performance is kept.
[0077]
The inventors have found that optimization of the cyclic block permutation for the blind demapping does not result in optimal performance in the iterative demapping, and vice versa. It remains as a challenging task to find a cyclic block permutation that achieves good performance for both the blind demapping and the iterative demapping.
[0078]
Thus, cyclic block permutations that achieve good performance for both the blind demapping and the iterative demapping are presented.
[0079]
An SNR range for various cyclic block permutations is determined from the preliminary step. Then, the threshold SNR is set in order to select only cyclic block permutations that achieve good performance for the blind demapping. The good performance means a low SNR. The threshold SNR should not be set too low. This is because the too low threshold SNR leads to exclusion of many cyclic block permutations that achieve very good performance for the iterative demapping.
On the other hand, when the cyclic block permutation that is strictly optimized for the blind demapping is used for the iterative demapping, performance becomes poor. It is a question of experience to select the initial threshold SNR appropriately.
[0080]
In a first selection step, a large number of cyclic block permutations are generated randomly under no constraint. A BLER
curve regarding the blind demapping is determined for each cyclic block permutation by using Monte-Carlo simulations, for example. Only the cyclic block permutations with the SNR at the BELR
target value being lower than a determined threshold SNR is kept. The BLER
curve regarding the iterative demapping is determined for the kept cyclic block permutations, and the best cyclic block permutation is kept.
[0081]
In a second selection step, a medium number of cyclic block permutations determined from the cyclic block permutation selected in the first selection step is generated randomly under a constraint. Then, a selection criterion in the first selection step is applied. The constrained cyclic block permutations are determined by application of a random permutation to the cyclic block of one section randomly selected.
The application of such a constraint ensures that changes in performance are small and concentrated around the good-performance cyclic block permutation that has already selected in the first selection step. The good-performance cyclic block permutation can be found by this method more effectively than by using blind unconstrained search.
[0082]
In a third selection step, the medium number of cyclic block permutations determined from the cyclic block permutation selected in the second selection step is generated randomly under a constraint. Then, the selection criterion in the first selection step is applied. The constrained cyclic block permutations are determined by application of random permutations to the bits having the same robustness level. Thus, changes in performance are very small and affect the iterative demapping more than the blind demapping. Accordingly, the performance regarding the iterative demapping is optimized without scarification of the performance regarding the blind demapping.
[0083]
The inventors have carried out optimization of the cyclic block permutations for each of the code rates 6/15, 7/15, 8/15. In addition, simultaneously with the optimization of the cyclic block permutations, the inventors have determined the optimal non-uniform constellation to be used together with the code rates 6/15, 7/15, 8/15. The following describes QB permutations and non-uniform constellations optimized for each of the code rates 6/15, 7/15, 8/15.
[0084]
Table 1 and Table 2 are tables illustrating the cyclic block permutations and non-uniform 64-PAM constellations that constitute non-uniform 4096-QAM
constellations according to the present disclosure when the code rate is equal to 6/15, respectively.
[0085]
However, in Table 1, and in Table 3 and Table 5 described below, the indices of the cyclic blocks start with zero and end with 179. "j-th block of Group-wise Interleaver Output" indicates the index of the cyclic block within the codeword after the cyclic blocks are permutated. In addition, "n(j)-th block of Group-wise Interleaver Input"
indicates the index of the cyclic block within the codeword before the cyclic blocks are permutated.
In addition, in Table 2, and in Table 3 and Table 5 described below, address label x starts with zero and ends with 63. Regarding "Address Label x (integer, MSB
first)," an address label of the most significant bit (MSB) of the bits is "0," and an address label of the next bit of the most significant bit is "1." "PAM spots p(x)" indicates the real value of the PAM symbol corresponding to the address label.

[0086]
[Table 1]
j-th 7 (j)-th j-th 7 (j)-th j-th If (D-th j-th 7 (j)-th block of block of block of block of block .. of .. block of .. block of .. block of Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise Interleaver Irterleaver Interleaver Interleaver Interleaver Interleaver Interleaver Interleaver output input output input output input output input

31 169 76 18 121 63 166 9

32 156 77 78 122 77 167 172

33 123 78 151 123 136 168 25

34 53 79 16 124 51 169 26 [0087]
[Table 2]
Address PAM Address PAM Address PAM Address PAM
Label x spots p(x) Label x spots p(x) Label x spots p(x) Label x spots p(x) (integer, (integer, (integer, (integer, MSB first) MSB first) MSB first) MSB first) 0 1,7263 16 0,1107 32 -1,7263 , 48 -0,1107 1 1,4611 17 0111 33 -1,4611 49 -0,111 2 1,1929 18 0,1099 34 -1,1929 50 -0,1099 3 1,2504 19 0,11 35 -1,2504 51 -0,11 4 0,9179 20 0,1161 36 -0, 9179 52 -0, 1161 0,9107 21 0,1166 37 -0,910] 53 -0,1166 6 0,9856 22 0,1157 38 -0, 9856 54 -0, 1157 7 0,972 23 0,1158 39 -0,972 55 -0,1158 8 0, 5891 24 0, 3626 40 -0, 5891 56 -0, 3626 9 0, 5902 25 0, 3619 41 -0, 5902 57 -0, 3619 0, 5809 26 0, 366 42 -0, 5809 58 -0, 366 11 0, 5821 27 0, 3659 43 -0, 5821 59 -0, 3659 12 0, 6911 28 0, 3341 44 -0, 6911 60 -0, 3341 13 0, 6944 29 0, 3333 45 -0, 6944 61 -0, 3333 14 0, 6678 30 0, 3374 46 -0, 6678 62 -0, 3374 0, 6709 31 0, 3368 47 -0, 6709 63 -0, 3368 [0088]
5 Table 3 and Table 4 are tables illustrating the cyclic block permutations and the non-uniform 64-PAM constellations that constitute the non-uniform 4096-QAM
constellations according to the present disclosure when the code rate is equal to 7/15, respectively.

[0089]
[Table 3]
j-th it (j)-th j-th it (j)-th j-th it (j)-th j-th it ( j)-th block of block of block of block of block of block of block of block of Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise Inter I eaver Inter I eaver Inter I gayer Inter I eaver I nte r I eaver Inter I eaver Inter I eaver Inter leaver output i nput output i nput output i gout output input 19 ' 172 64 148 109 165 154 124 , [0090]
[Table 4]
Address PAM Address PAM Address PAM Address PAM
Label x spots p(x) Label x spots p(x) Label x spots p(x) Label x spots p(x) (integer, (integer, (integer, (integer, MSB first) MSB first) MSB first) MS E first) 0 1,6851 - 16 0,081 32 -1,6851 48 .. -0,081 1 1,4381 17 0,0808 33 -1,4381 49 -0,0808 2 1,1766 18 0,081 34 -1,1766 50 -0,081 3 1, 2355 19 0, 0807 35 -1, 2355 51 -0, 0807 4 0,9162 20 0, 1456 36 -0, 9162 52 -0, 1456 0,9089 21 0, 1456 37 -0, 9089 53 -0, 1456 6 1,0012 22 0,1456 38 -1,0012 54 -0, 7 0,9771 23 0, 1457 39 , -0, 9771 55 -0, 1457 8 0, 5684 24 0, 4036 40 -0, 5684 56 -0, 4036 9 0, 5681 25 0, 4036 41 -0, 5681 57 -0, 4036 0, 5704 26 0, 4043 42 -0, 5704 58 -04043 11 0,57 27 0, 4042 43 -0,57 59 -0, 4042 12 0, 7385 28 0, 3059 44 -0, 7385 60 -0, 3059 13 0, 7425 29 0, 306 45 -0, 7425 61 -0, 14 0, 7155 30 0, 3056 46 -0, 7155 62 -0, 3056 0, 7186 31 0, 3057 47 -0, 7186 63 -0, 3057 [0091]
5 Table 5 and Table 6 are tables illustrating the cyclic block permutations and the non-uniform 64-PAM constellations that constitute the non-uniform 4096-QAM
constellations according to the present disclosure when the code rate is equal to 8/15, respectively [0092]
[Table 5]
j-th ' 7 (])-th j-th 7 C]) -th j-th 7 (j)-th j-th ' 7 (j)-th .
block of block of block of block of block of block of block of block of Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise Group-wise = filter I eaver Inter I eaver Inter I eaver I nter I eaver Inter leaver Inter leaver Inter leaver Inter I eaver output input output Input output input output input 4 96 49 52 94 , 14 , 139 -- 159 _ 16 79 61 100 ' 106 108 151 7 18 133 63 173 , 108 , 10 153 34 , _ ' 32 , 142 77 48 122 26 167 116 _ _ 111 85 _ 33 130 61 175 149 42 95 87 2 132 148 177 72 _ _ ¨

[0093]
[Table 6]
Address PAM Address PAM Address PAM Address PAN
Label x spots p(x) Label x spots p(x) Label x spots p(x) Label x spots p(x) (integer, (integer, (integer, (integer, MSB first) MSB first) MSB first) MSB first) 0 1,6651 16 0,0695 32 -1,6651 48 -0,0695 1 1,4272 17 0,0694 33 -1,4272 49 -0, 0694 2 1,1713 18 0,0696 34 -1,1713 50 -0,0696 3 1, 2329 19 0, 0697 35 -1, 2329 51 -0, 0697 4 0,9125 20 0,1629 36 -0, 9125 52 -0,1629 0, 9069 21 0, 1629 37 -0, 9069 53 -0, 1629 6 1,0081 22 0,1629 38 -1,0081 54 -0,1629 7 0, 9831 23 0, 163 39 -0, 9831 55 -0, 163 8 0,5697 24 0,4194 40 -0,5697 56 -0, 4194 9 0, 5694 25 0, 4196 41 -0, 5694 57 -0, 4196 0,5739 26 0, 4196 42 -0, 5739 58 -0,4196 11 0,5733 27 0,4195 43 -0,5733 59 -0,4195 12 0,7459 28 0, 3034 44 -0,7459 60 -0, 3034 13 0, 7496 29 0, 3035 45 -0, 7496 61 -0, 3035 14 0, 7192 30 0,3032 46 -0, 7192 62 -0, 3032 0,7216 31 0,3032 47 -0, 7216 63 -0, 3032 [0094]
5 Note that cyclic block permutation unit 210 in FIG. 14 permutates the cyclic blocks within the codeword according to the code rate of the code used by LDPC

encoder 121, based on the cyclic block permutations of Table 1, Table 3, and Table 5 according to the code rates 6/15, 7/15, and 8/15, respectively.
[0095]
10 Next, operations of the QAM mapper of the present exemplary embodiment will be described.
[0096]
Mapping to complex cells s (Re, Im) by QAM mapper 124 is performed by calculation of Equation 4 described below. However, non-uniform PAM
coordinates 15 p(x) are obtained from Table 2 in the case of the code rate 6/15, from Table 4 in the case of the code rate 7/15, and from Table 6 in the case of the code rate 8/15.
[0097]
[Equation 4]

= p(x')-F j x p(x") [0098]
where address labels x' for real part p (x') are calculated by Equation 5 by using even numbered bits ba), b2, ba, b6, 105, 1310 which are output from the interleaver (section interleaver) (a number of cyclic blocks per section is B) that is disposed in a subsequent stage of FIG. 14 and that has a function equivalent to bit interleaver 122 described with reference to FIG. 13A to FIG. 13C.
[0099]
[Equation 5]
r X ¨ 25-ib2i [0100]
In addition, address label x" of imaginary part p (x") is calculated by Equation 6 by using odd numbered bits b1, b3, b5, b7, 1)9, bill that are output from the above-described section interleaver.
[0101]
[Equation 6]
x--15 If 25-ib2i+1 X ¨
[0102]
The above-described cyclic block permutations (for example, Table 1, Table 3, Table 5) and the non-uniform QAM constellations (for example, Table 2, Table 4, Table 6) are relevant to both the transmitter side and the receiver side in a digital communication system. Each of the above-described cyclic block permutations uniquely defines its inverse cyclic block permutation. One of the above-described cyclic block permutations is used for bit interleaving on the transmitter side, and its inverse cyclic block permutation is used for bit de-interleaving on the receiver side.
Further, based on the above-described definition of the above-described non-uniform QAM constellation (two-dimensional non-uniform constellation), mapping of constellation words, that is, bits of the codeword to complex cells used for transmission is performed in the transmitter, and demapping of the received complex cells is performed in the receiver on the other side of a communication channel.
[0103]
The above-described cyclic block permutations and the above-described non-uniform 4096-QAM constellations are optimized for special LDPC codes with the code rates of 6/15, 7/15, 8/15.
[0104]
Table 7-1, Table 7-2 illustrate definition of this LDPC code with the code rate of 6/15 and a code length of 64800 code bits. Note that actually, the definition of the LDPC code is completed by a last row of Table 7-1 followed by a first row of Table 7-2.

[0105]
[Table 7-1]

35 46 978 9912 9978 12567 17843 24194 34887 35206 306 344 679 5224 6674 10305 18753 25583 30.585 36943 [0106]
[Table 7-2]

, 89 552 847 6656 9889 23949 26226 27080 31236 35823 94 954 998 2003 3369 6870 7321 29856 31373 34888 , , 79 350 933 4853 6252 11932 12058 21631 24552 24876

36 149 220 6936 18408 19192 19288 23063 28411 35312 125 241 819 2245 3199 8415 21133 26786 27226 38838 , ,9802 16164 17499_22378 22403 22704 26742 29908 , [0107]
Table 8-1 and Table 8-2 illustrate definition of this LDPC code with the code rate of 7/15 and the code length of 64800 code bits. Note that actually, the definition of the LDPC code is completed by the last row of Table 8-1 followed by the first row of Table 8-2.

[0108]
[Table 8-1]

316 384 944 4872 8491 18913 21085 23198 24798_ [01091 [Table 8-2]

664 786 1043 913] 9294 10163 23389 31436 34297 , 203 507 1060 6971 12216 13321 17861 22671 29825 .107 481 555 7322 13234 19344 23498 26581 31378 , 126 247 515 6031 9549 10643 22067 29490 34450 .222 542 1021 3291 3652 13130 16349 33009 34348 _25 902 912 1137 2975 9642 11598 25919 28278 [0110]
Table 9-1 and Table 9-2 illustrate definition of this LDPC code with the code rate of 8/15 and the code length of 64800 code bits. Note that actually, the definition of the LDPC code is completed by the last row of Table 9-1 followed by the first row of Table 9-2.

a7 869 2450 4386 5316 6160 7107 10362 11132 11211 13149. 16397 16532 17113 19894 6925 :176 12392 14529 15253 15437 19226 19950 20321 23021 23651 24393 24653 co 2547 3404 3538 4666 5126 5468 7695 8799 14732 15072 15881 17410 1.71 19609 19711 22150 24941 2/908 29018 12572 28045 28990 6]

25171 26726. 28848 20224 29412 16131 26047 25649 CD
CD
NJ
oa CD

ci "

r,) 21029 22677 27150 28980 11159 15111 21608 =

3259 17301 21.02 cs) [0113]
Calculation processing of the parity bits performed by LDPC encoder 121 will be described below.
[0114]
The LDPC code with the code rates of 6/15, 7/15 is defined based on the following algorithm.
[0115]
The LDPC code is used for encoding information blocks = (so, sl, sk_i), and for accordingly generating codeword A with code length N = K + M1 + M2, A =
(Xo, 41_ i) = (ko, Xi, ===, 4-1, Po, Pi, ===, Pmi +M2- 1)=
[0116]
where, in the case of the code rate 6/15, M1 = 1080, M2 = 37800, Qi = 3, Q2 =
105. In addition, in the case of the code rate 7/15, M1 = 1080, M2 = 33480, Qi = 3, Q2 = 93.
[0117]
LDPC encoder 121 calculates the parity bit as follows.
[0118]
(1) Initialization by Equation 7 is performed.
[0119]
[Equation 7]
2, =s = 0,1, . , K ¨1 p = 0 j = 0,1, . , + M 2 - 1 [0120]
(2) For A.,õ (where, m = 0, 1, ..., 359), km is accumulated at parity bit addresses by Equation 8.
[0121]
[Equation 8]
(X x Q1) mod M1 i:f x <
M1+{(x ¨ All+nixQ2) mod M2.} if x_Afi [0122]

where x indicates the address of the parity bit accumulator corresponding to first bit Xo. Note that mod represents a modulo operator (the same applies to the followings).
[0123]
(3) For 360-th information bit XL, the addresses of the parity bit accumulators are provided in the second row of the definition based on each of Table 7-1 and Table 7-2 in the case of the code rate 6/15, and the addresses of the parity bit accumulators are provided in the second row of the definition based on each of Table 8-1 and Table 8-2 in the case of the code rate 7/15. Similarly, the addresses of the parity bit accumulators for next 2,,,õ (where m = L + 1, L + 2, ..., L + 359) are obtained by Equation 9.
[0124]
[Equation 9]
(x + inx 2) mod A 4 if x < M
M + ¨ + m X Q2 ) mod M2 if x [0125]
where x indicates the address of XL. In the case of the code rate 6/15, x is a value in the second row of the definition based on each of Table 7-1 and Table 7-2, and in the case of the code rate 7/15, x is a value in the second row of the definition based on each of Table 8-1 and Table 8-2.
[0126]
(4) Similarly, a new row of the definition based on each of Table 7-1 and Table 7-2 in the case of the code rate 6/15, and a new row of the definition based on each of Table 8-1 and Table 8-2 in the case of the code rate of 7/15 are used for each group of new 360 information bits in order to find the addresses of the parity bit accumulators.
[0127]
(5) After the codeword bits from ko to ki< _ 1 are processed, an operation expressed by Equation 10 is performed sequentially with start of i = 1.
[0128]
[Equation 10]
= p, 0 for i = 1,2, /4/1 ¨1 [0129]
(6) The parity bits from ki< to K + MI - 1 are obtained by using an interleaving operation of L = 360 expressed by Equation 11.
[0130]
[Equation 11]
AK+ Ixt4-s poixs , for 0 s< L, 0 t < ()/
[0131]
(7) The addresses of the parity bit accumulators are calculated by Equation 12 for each group of the new codeword bits of L = 360 from 4 to + MI -1, by using a new row of the definition based on each of Table 7-1 and Table 7-2 in the case of the code rate 6/15, and by using a new row of the definition based on each of Table 8-1 and Table 8-2 in the case of the code rate 7/15.
[0132]
[Equation 12]
(x+mxa) mod ./141 If x < /14, + {(x: - m, + x Q2) mod 1 ,} x.?_ Mi [0133]
where x indicates the address corresponding to a head code bit of each group of the codeword bits. In the case of the code rate 6/15, x is a value of the row corresponding to each group of the definition based on each of Table 7-1 and Table 7-2.
In the case of the code rate 7/15, x is a value of the row corresponding to each group of the definition based on each of Table 8-1 and Table 8-2.
[0134]
(8) After the codeword bits from 4 to 4 + M1 - 1 are processed, the parity bits from 4 ml to XI< Ml + M2 - I are obtained by using an interleaving operation of L = 360 .. expressed by Equation 13.
[0135]
[Equation 13]
A = for 0 S <L, 0 <Q2 [0136]

(9) Subsequently, codeword bits ki (i = 0, 1, N - 1) are sent to cyclic block permutation unit 210 of the bit interleaver.
[0137]
The LDPC code with the code rate of 8/15 is defined by the following algorithm.
[0138]
(1) The bits of the LDPC codeword are denoted as co, cN _1, and the first K bits are equal to information bits and are represented by Equation 14.
[0139]
[Equation 14]
CklA fbr 0 <K
[0140]
Then, parity bit pk = ck+ K is calculated as follows by LDPC encoder 121.
[0141]
(2) Initialization by Equation 15 is performed.
[0142]
[Equation 15]
Pk =0 .for0_.k<N¨K
[0143]
where N = 64800, and K = N x code rate.
[0144]
(3) For k which is equal to or greater than 0 and is less than K, i is a maximum integer that is not larger than a value obtained by division of k by 360, and I = k mod 360. For all j, ik is accumulated in pq0,1, k), as expressed by Equation 16.
[0145]
[Equation 16]

Pg(i,01) = PC1(1,0,1) Pq(1,1,1) = Pq(1,1))+ 1k Pq(i,2,1) Pq(1,2,1)+
tk P q(i.w(1)-1,1) P q(i.w(7)-1,1)+ k [0146]
where w(i) is a number of elements in the i-th row in the index list of the definition based on each of Table 9-1 and Table 9-2.
[0147]
(4) Processing by Equation 17 is performed on all k of 0 < k < N ¨ K.
[0148]
[Equation 17]
P k P k -1)111C" 2 [0149]
(5) All codeword bits co, cl, cN _ I
are obtained in the above-described steps.
A panty interleaver expressed by Equation 18 is applied to the last N ¨ K
codeword bits.
[0150]
[Equation 18]
u, = c, 0 <k it 4_36(w4, K.4-Rxs.+r for 0 s <360, 0 t < R
[0151]
A role of the parity interleaver is to convert the staircase structure of the parity part of the LDPC parity-check matrix into a quasi-cyclic structure similar to the information part of the matrix. Parity interleaved codeword bits co, cl , cN _1 are sent to cyclic block permutation unit 210 of the bit interleaver.
[0152]
Parameters q (i, j, 0) indicate j-th entry of the i-th row in the index list of the

37 definition based on each of Table 9-1 and Table 9-2, and satisfy a relationship of Equation 19.
[0153]
[Equation 19]
q(i ,1)= j ,0)+ R x 1( mod(AT¨ k)) for 0 < 1 < 360 [0154]
Every accumulation is realized by addition regarding the Galois field CF (2).
R
is 84 in the case of the code rate 8/15.
[0155]
Supplemental (1) >>
The present disclosure is not limited to the description provided in the above-described exemplary embodiment, and can be carried out in any form for achieving the object of the present disclosure and an object related or relevant to the object of the present disclosure. For example, the present disclosure may be as follows.
[0156]
(1) The present disclosure is described with reference to the special exemplary embodiment illustrated in the accompanying drawings, particularly, by presenting one example as values of key parameters N, M, Q. However, the present disclosure is not limited to the specific combination of these parameters. In fact, the present disclosure is applicable to any combination practically relevant to values (positive integers) for these parameters, such as those described in the DVB-T2 standard or those defined by a similar standard.
[0157]
(2) The present disclosure is not limited to a specific form for implementing the disclosed methods or devices in both software and hardware.
[0158]
Particularly, the present disclosure may be implemented in a form of a computer-readable medium that embodies computer-executable instructions adapted such that a computer, a microprocessor, a microcontroller, and the like can execute all the steps of the method according to the exemplary embodiment of the present disclosure.

38 [0159]
In addition, the present disclosure may be implemented in a form of an application-specific integrated circuit (ASIC) or in a form of a field programmable gate array (FPGA).
[0160]
(3) The present disclosure relates to a digital communication system based on the QC LDPC codes and high-order constellations. The present disclosure provides special permutations that permutate the LDPC code bits and special non-uniform constellations that transmit interleaved codewords. The permutations and the non-uniform constellations are jointly optimized at the code rate of 6/15, 7/15, or 8/15.
[0161]
<< Supplemental (2) >>
The communication method and the like according to the present disclosure will be summarized as follows.
.. [0162]
(1) A first communication method is a data communication method for performing data communication in a digital communication system using a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code. The communication method includes an interleaving step of executing a cyclic block permutation for a codeword generated based on the quasi-cyclic parity-check code, where the codeword includes a sequence of N
cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword, and a constellation mapping step of mapping each of the bits of the codeword for which the cyclic block permutation is executed to a constellation point of a non-uniform constellation. In the communication method, the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword.
[0163]
(2) According to a second communication method, in the first communication method, the code rate of the quasi-cyclic low-density parity-check code is 6/15, and the non-uniform constellation is a non-uniform 4096-QAM constellation having real coordinates and complex coordinates each of which is a non-uniform 64-PAM
constellation given according to Table 2 described above.

39 [0164]
(3) According to a third communication method, in the first or second communication method, the code rate of the quasi-cyclic low-density parity-check code is 6/15, and the cyclic block permutation is defined according to Table 1 described above.
[0165]
(4) According to a fourth communication method, in the first communication method, the code rate of the quasi-cyclic low-density parity-check code is 7/15, and the non-uniform constellation is a non-uniform 4096-QAM constellation having real coordinates and complex coordinates each of which is a non-uniform 64-PAM
constellation given according to Table 4 described above.
[0166]
(5) According to a fifth communication method, in the first or fourth communication method, the code rate of the quasi-cyclic low-density parity-check code is 7/15, and the cyclic block permutation is defined according to Table 3 described above.
[0167]
(6) According to a sixth communication method, in the first communication method, the code rate of the quasi-cyclic low-density parity-check code is 8/15, and the non-uniform constellation is a non-uniform 4096-QAM constellation having real coordinates and complex coordinates each of which is a non-uniform 64-PAM
constellation given according to Table 6 described above.
[0168]
(7) According to a seventh communication method, in the first or sixth communication method, the code rate of the quasi-cyclic low-density parity-check code is 8/15, and the cyclic block permutation is defined according to Table 5 described above.
[0169]
(8) According to an eighth communication method, in any one of the first to seventh communication methods, N is equal to 180 and Q is equal to 360.
[0170]
(9) According to a ninth communication method, in any one of the first to eighth communication methods, the quasi-cyclic parity-check code used for generation of the codeword is selected from a plurality of the determined quasi-cyclic parity-check codes having code rates different from each other.
[0171]
(10) A first communication device is a communication device in a digital communication system that performs communication by any one of the first to ninth communication methods.
[0172]
(11) A tenth communication method is a data communication method for performing data communication in a digital communication system using quasi-cyclic low-density parity-check including a repeat-accumulate quasi-cyclic low-density parity-check code. The communication method includes executing a cyclic block permutation for a codeword generated based on the quasi-cyclic low-density parity-check code, performing demapping based on a non-uniform constellation on each of complex cells obtained by performing constellation mapping of the non-uniform constellation on a bit of the codeword for which the cyclic block permutation is executed, and performing processing inverse to the cyclic block permutation on a result of the demapping.
[0173]
(12) A second communication device is a communication device in a digital communication system that performs communication by the tenth communication method.
INDUSTRIAL APPLICABILITY
[0174]
The present disclosure can be used for a BICM system that uses a QC LDPC
code and QAM.
REFERENCE MARKS IN THE DRAWINGS
[0175]
100 transmitter 110 input processing unit 120 BICM encoder 130 OFDM modulator 140 up-converter 150 RE amplifier 121 LDPC encoder 122 bit interleaver 124 QAM mapper 210 cyclic block permutation unit 220-1 to 220-12 intra-QB permutation unit

Claims (13)

1. A communication method comprising:
executing a cyclic block permutation for a codeword generated based on a quasi-cyclic low density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the codeword includes N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword;
mapping each of the bits of the codeword for which the cyclic block permutation is executed to any one of constellation points of a non-uniform 4096 QAM
constellation, said mapping including section interleaving, generating each constellation word from bits in B cyclic blocks of the codeword for which the cyclic block permutation is executed, where B is a bit number of the QAM symbol, the B cyclic blocks thereby forming the respective section, the section interleaving being performed by writing all bits of one section of the codeword for which the cyclic block permutation is executed row-by-row in a matrix and reading these bits column-by-column from the matrix; and transmitting the mapped codeword, wherein the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword, wherein the code rate of the quasi-cyclic low-density parity-check code is equal to 7/15, and the cyclic block permutation is defined according to Table A:

Date Recue/Date Received 2022-02-03 [Table A]
j-th x (j)-th j-th (1)-th j-th (D-th j-th r 01-th block of block of block of block of block of block of block of block of 6rowniee Groumnse toureise Group-eise Group-eise Grco-eise Grow-wise 6roup-in se inter leaver Inter leaver Inter leaver inter leaver liter leaver Inter leaver inter leaver lnterleaver output imut output input output mput output input 1 , 122 , 46 , 4 91 51 , 136 117 _ 12 60 57 44 102 99 147 77 i 5 120 , 60 30 105 11 150 32 24 0 = 69 49 114 179 159 137 27 61 72 29 117 , 105 , 162 19 29 70 ' 74 175 119 116 164 61--31 78 76 , 109 121 174 166 17 33 35 , 78 74 , 123 75 168 23 36 48 81 177 126 _ 81 171 21 43 160 _ 88 , 123 , 133 , 16 , 178 141 , 44 133 _ 89 33 134 _ 113 179 178 wherein the j-th block of Group-wise Interleaver output indicates an index of the cyclic blocks within the codeword after the cyclic blocks are permutated, and wherein the Tr(j)-th block of Group-wise Interleaver input indicates an index of the cyclic blocks within the codeword before the cyclic blocks are permutated, Date Recue/Date Received 2022-02-03 wherein N is equal to 180, and Q is equal to 360.

2. The communication method according to claim 1, wherein the quasi-cyclic low-density parity-check code used for generation of the codeword is selected from a plurality of determined quasi-cyclic low-density parity-check codes having code rates different from each other.

3. A communication device comprising:
interleaving circuitry for executing a cyclic block permutation for a codeword generated based on a quasi-cyclic low-density parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the codeword includes N cyclic blocks, each of the N cyclic blocks includes Q bits, each of N and Q is a positive integer, and the cyclic block permutation is permutation of the cyclic blocks within the codeword;
constellation mapping circuitry for mapping each of the bits of the codeword for which the cyclic block permutation is executed to any one of constellation points of a non-uniform 4096 QAM constellation, said mapping including section interleaving, generating each constellation word from bits in B cyclic blocks of the codeword for which the cyclic block permutation is executed, where B is a bit number of the QAM
symbol, the B cyclic blocks thereby forming the respective section, the section interleaving being performed by writing all bits of one section of the codeword for which the cyclic block permutation is executed row-by-row in a matrix and reading these bits column-by-column from the matrix; and transmitting circuitry for transmitting the mapped codeword, wherein the cyclic block permutation and the non-uniform constellation are selected based on a code rate of the quasi-cyclic low-density parity-check code used for generation of the codeword, wherein the code rate of the quasi-cyclic low density parity-check code is equal to 7/15, and the cyclic block permutation is defined according to Table B:
Date Recue/Date Received 2022-02-03 [Table B]
J-th (j)-th j-th (j)-th j-th (J)-th rth X (j)-th block of block of block of block of block of block of block of block of eras-vise Grotoinse firroise Groip-mse Groumse &Oka* araiXt-lise Groucrinse Interleaver interloper inter leaver interloper Interleser Interloper Interloper Interlewer output ioput , output iut output i rat output irput 7 , 62 , 52 168 97 108 142 56 , 119 55 57 100 103 145 85 11 72 , 56 83 101 115 , 146 84 , , 14 , 34 59 110 104 36 149 107 126 60 , 30 105 11 50 32 17 31 , 62 82 107 169 152 147 18 129 63 10 108 8 õ. 153 , 132 22 65 , 67 , 22 112 , 140 157 58 23 9 , 68 , 96 113 , 95 158 118 , 26 , 13 71 100 116 125 161 97 40 75 38 120 150 165 25 , 31 , 78 76 109 121 , 174 , 166 , 17 , 33 35 78 , 74 123 75 168 , 23 36 , 48 81 177 126 81 171 21 38 92 83 47 128 130 173 , 131 ao 6 85 63 130 156 175 , 14 42 66 , 87 45 132 171 177 128 43 160 88 123 133 , 16 , 178 141 44 133 _ 89 33 134 113 179 _ 178 wherein the j-th block of Group-wise Interleaver output indicates an index of the cyclic blocks within the codeword after the cyclic blocks are permutated, and wherein the Tr(j)-th block of Group-wise Interleaver input indicates an index of the cyclic blocks within the codeword before the cyclic blocks are permutated, Date Recue/Date Received 2022-02-03 wherein N is equal to 180, and Q is equal to 360.

4. A
transmission method performed by a transmitter, the transmission method comprising:
generating, by coding circuit of the transmitter, a codeword according to quasi-cyclic low-density parity-check coding such that the codeword consists of N cyclic blocks, the N cyclic blocks each consist of Q bits, each of N and Q is a positive integer, and a code rate of the codeword is 7/15, the quasi-cyclic low-density parity-check coding including repeat-accumulate quasi-cyclic low-density parity-check coding;
reordering, by an interleaving circuit of the transmitter, the N cyclic blocks;
mapping, by a mapping circuit of the transmitter, bits in the codeword onto constellation points of a non-uniform 4096 QAM scheme to generate mapped bits after the N cyclic blocks are reordered; and generating, by a signaling circuit of the transmitter, a transmission signal based on the mapped bits, wherein the N cyclic blocks are reordered according to Table C which is associated with the code rate, Date Recue/Date Received 2022-02-03 [Table C]
j-th x Vi-th ,-a1i X (j)-th j-:1: A : j-tt i-tl-bllocit of block of :.-.o. ;:- 1E1 1 i !:11_0:k J
bted Li- L
DrOLPIits4 GregrillIgi :3,.).U-61L4 ei '.!'4:-II I r.IJ 'dr !',.!_= 3.1.-k, , Gfary, "2 IY1_44"P I
!., HIr2!::!3s...! ]-1..,.!. :Ayi:r i:r 1 um hau I
il.d.,c PrDr ',He fl t' ,i-.5.J [hic .30411r Wi.... ='LLi: ..c.ia:: ill: :...1-,.;:C_ litti Ltit-Li.
i[iJr_ 3 03 48 81 03 :E;,j 1.38. 157 117 50 79 "J5 80 1.40 143 c 42 53 163 08 89 143 152 0 102 54 170 09 7 144 n 120 60 30 105 11 , 150 32 18 120 63 10 .1 03 8 153 132 2.1 94 66 41 111 , 173 156 121 26 13 71 100 116 , .12,5 161 97 2.7 61 72 2:',1 117 , 105 162 10 213 3 73 3Q 1111 , 1 163 155 32 127 77 91 122 , 15 167 126 34 145 79 159 124. 84 160 43 :13 q? L.',..J 47 123 130 173 131 39 7:3 .E:4 140 129 151 174 25 41 1 '.i4 a; Eta 131 53 116 18 4.2 55 81 45 13.2. 171 1 77 128 44 13'2. 39 .--A , 134 , 113 179 178 wherein in the Table C, the j-th block of Group-wise lnterleaver Output indicates the index of the cyclic block after the N cyclic blocks are reordered, and the n(j)-th block of Group-wise lnterleaver input indicates the index of the cyclic block before the N cyclic blocks are reordered.

Date Recue/Date Received 2022-02-03

5. The transmission method according to claim 4, wherein the constellation points are defined by Table D which is associated with the code rate, [Table D]
Address PAM Address PAM Address PAM Address PAM
Label x spots p (x) Label x spots p(x) Label x spots p (x) Label x spots p (x) (integv, (i nteger, (integer, (i nteger, MSB f i rst) MSB f rst) MSB f i rst) MSB f i rst) 0 1, 6851 16 0, 081 32 -1, 6851 48 -0, 081 1 1, 4381 17 0, 0808 33 -1, 4381 49 -0, 0808 2 1, 1766 18 0, 081 34 -1, 1766 50 -0, 081 3 1, 2355 19 0, 0807 35 -1, 2355 51 -0, 0807 4 0, 9162 20 0, 1456 36 -0, 9162 52 -0, 1456 0, 9089 21 0, 1456 37 -0, 9089 53 -0, 1456 6 1, 0012 22 0, 1456 38 -1, 0012 54 -0, 1456 7 0, 9771 23 0, 1457 39 -0, 9771 55 -0, 1457 8 0, 5684 24 0, 4036 40 -0, 5684 56 -0, 4036 9 0, 5681 25 0, 4036 41 -0, 5681 57 -0, 4036 0, 5704 26 0, 4043 42 -0, 5704 58 -0, 4043 11 0, 57 27 0, 4042 43 -0, 57 59 -0, 4042 12 0, 7385 28 0, 3059 44 -0, 7385 60 -0, 3059 13 0, 7425 29 0, 306 45 -0, 7425 61 -0, 306 14 0, 7155 30 0, 3056 46 -0, 7155 62 -0, 3056 0, 7186 31 0, 3057 47 -0, 7186 63 -0, 3057 wherein in the Table D, the Address Label x indicates the index of the bit of the codeword and the PAM spots p(x) indicate a real value and an imaginary value of a constellation point, the PAM spots p(x) indicate an effective value of a PAM
symbol corresponding to the Address Label x.

6. The transmission method according to claim 4, further comprising:
reordering the bits in the codeword with an M by Q matrix after the N cyclic blocks are reordered and before the bits in the codeword are mapped, M is a positive integer, wherein in the reordering of the bits, the bits are written into the M by Q matrix row-by-row and the written bits are read from the M by Q matrix column by column.

7. A reception method performed by a receiver, the reception method comprising:
receiving, by an antenna of the receiver, the transmission signal generated by Date Recue/Date Received 2022-02-03 the transmission method according to claim 4;
demapping, by a demapping circuit of the receiver, the mapped bits according to the non-uniform 4096 QAM scheme; and reversely reordering, by a deinterleaving circuit of the receiver, the N
cyclic blocks according to the Table C.

8. A transmission device comprising:
a coding circuit configured to generate a codeword according to quasi-cyclic low-density parity-check coding such that the codeword consists of N cyclic blocks, the N cyclic blocks each consist of Q bits, each of N and Q is a positive integer, and a code rate of the codeword is 7/15, the quasi-cyclic low-density parity-check coding including repeat-accumulate quasi-cyclic low-density parity-check coding;
an interleaving circuit connected to the coding circuit to reorder the N
cyclic blocks;
a mapping circuit connected to the interleaving circuit to map bits in the codeword onto constellation points of a non-uniform 4096 QAM scheme to generate mapped bits; and a signaling circuit connected to the mapping circuit to generate a transmission signal based on the mapped bits, wherein the interleaving circuit reorders the N cyclic blocks according to Table E
which is associated with the code rate, Date Recue/Date Received 2022-02-03 [Table E]
ft' it (P-til ,fr'r-' r ' --11 i-t, 1 Hi i-ti x qr¨U1 t-ii:,4. tY; tl I el* Tit 11, l'S, +. i 61L4A .4 tIr. Li HO rit 12 0 IA b1crk -7`t 4.-11i,e ':ii- td',.:-A Le I]r 7-111.:,: 4 T.,,A.¨ft e 1.,'L,..Liiir,0 arta-v.2 Hilidem 1,r_i'M ]'I_Er HIM l'.=r1L' l'7='' c. Ir IL mar Inter L,i *ft ,.,,,-. mi,i L-',;:y,.: 14:LI Lttitit irt f_ 1 122 46 4 'I ..,,I I 36 117 2 161 47 5 92 =1.:1; 13:7 154 3 0j 4c87 93 ':';'3 1 j0 157 4 j7 40 106 94 167 139 154 112 50 79 95 80 140 14j 6 =111 51 104 D5 149 141 12 , 'd 42 ,-.3 163 98 50 143 152 ii 102 54 170 :L! I 144 20 12 60 57 44 109 09 147 :77 16 46 ,' 1 50 106 166 151 152;
17 31 6L 02 10 7 1(i9 152 147 15 129 63 10 108 a 153 132 23 0 ,":13 96 112 05 15;= 118 24 0 tI9 49 114 170 159 137 70 00 I 15 ,-) 160 114 22 61 72 29 117 105 16:2 19 20 3 73 3 I., 1 10 1 1,51.:, 155 2,u 7C) 74 1 75 110 116 164 6 7 33 35 , =-r50 74 123 75 16;.: 23 34 145 -1= 159 124 64 169 43 23 )10 139 125 176 170 27 37 162 =LI2 71 127 55 1 72 136 3.0 73 'A 146 12E1 151 174 26 6 i_I5 63 130 156 1 75 14 41 134 06 56 1j1 53 176 18 42 66 8 7 45 132 1:71 177 128 , wherein in the Table E, the j-th block of Group-wise lnterleaver Output indicates the index of the cyclic block after the N cyclic blocks are reordered, and the n(j)-th block of Group-wise lnterleaver input indicates the index of the cyclic block before the N cyclic blocks are reordered.

Date Recue/Date Received 2022-02-03

9. The transmission device according to claim 8, wherein the mapping circuit defines the constellation points by Table F which is associated with the code rate, [Table F]
Address PAM Address PAM Address PAM Address PAM
Label x spots p(x) Label x spots p(x) Label x spots p(x) Label x spots p (x) (integer, (i nteger, (integer, (i nteger, MSU f i rst) EU f rst) MS13 f i rst) MSU f i rst) 0 1, 6851 16 0, 081 32 -1, 6851 48 -0, 081 1 1, 4381 17 0, 0808 33 -1, 4381 49 -0, 0808 2 1, 1766 18 0, 081 34 -1, 1766 50 -0, 081 3 1, 2355 19 0, 0807 35 -1, 2355 51 -0, 0807 4 0, 9162 20 0, 1456 36 -0, 9162 52 -0, 1456 0, 9089 21 0, 1456 37 -0, 9089 53 -0, 1456 6 1, 0012 22 0, 1456 38 -1, 0012 54 -0, 1456 7 0, 9771 23 0, 1457 39 -0, 9771 55 -0, 1457 8 0, 5684 24 0, 4036 40 -0, 5684 56 -0, 4036 9 0, 5681 25 0, 4036 41 -0, 5681 57 -0, 4036 0, 5704 26 0, 4043 42 -0, 5704 58 -0, 4043 11 0, 57 27 0, 4042 43 -0, 57 59 -0, 4042 12 0, 7385 28 0, 3059 44 -0, 7385 60 -0, 3059 13 0, 7425 29 0, 306 45 -0, 7425 61 -0, 306 14 0, 7155 30 0, 3056 46 -0, 7155 62 -0, 3056 0, 7186 31 0, 3057 47 -0, 7186 63 -0, 3057 and wherein in the Table F, the Address Label x indicates the index of the bit of the codeword and the PAM spots p(x) indicate a real value and an imaginary value of a constellation point, and the PAM spots p(x) indicate an effective value of a PAM symbol corresponding to the Address Label x.

10. The transmission device according to claim 8, wherein the interleaving circuit comprises: a bit interleaving circuit configured to reorder the bits in the codeword with an M by Q matrix, M is a positive integer, wherein the bit interleaving circuit writes the bits into the M by Q matrix row-by-row and read the written bits from the M by Q matrix column by column.

11. A reception device comprising:
an antenna through which the transmission signal is to be received, the transmission signal being generated by the transmission device according to claim 8;

Date Recue/Date Received 2022-02-03 a demapping circuit connected to the antenna to demap the mapped bits according to the non-uniform 4096 QAM scheme; and a deinterleaving circuit connected to the demapping circuit to reversely reorder the N cyclic blocks according to the Table E.

12. A transmission device, comprising:
a processor; and a transmitter connected to the processor, wherein the processor is configured to perform:
generating a codeword according to quasi-cyclic low-density parity-check coding such that the codeword consists of N cyclic blocks, the N cyclic blocks each consist of Q bits, each of N and Q is a positive integer, and a code rate of the codeword is 7/15, the quasi-cyclic low-density parity-check coding including repeat-accumulate quasi-cyclic low-density parity-check coding;
reordering the N cyclic blocks;
mapping bits in the codeword onto constellation points of a non-uniform 4096 QAM scheme to generate mapped bits; and generating a transmission signal based on the mapped bits, the transmitter is configured to transmit the transmission signal, the processor reorders the N cyclic blocks according to Table G which is associated with the code rate, and in the Table G, the j-th block of Group-wise lnterleaver Output indicates the index of the cyclic block after the N cyclic blocks are reordered, and the n(j)-th block of Group-wise lnterleaver input indicates the index of the cyclic block before the N cyclic blocks are reordered, Date Recue/Date Received 2022-02-03 [Table G]
j-th x 41-th j-tb x ( -th x(j)-th x(j-th block of block of block d block of block of block of block of blod of (towels) areirsiss Grow-fist &wile. &wills birrise Groynise Orervise Inter lower InWleiver Inby lower liter law Mel sow Marketer biter lower Interlasim olaut irtMIA altPut i IVA old* ilgod 2 161 47 5 92 t19 137 154 4 37 49 106 94 = 167 139 164 11 72 56 i 83 101 115 146 84 12 60 57 = 44 102 99 147 77 16 46 61 = 50 106 16 151 153 18 129 63 = 10 108 8 153 132 24 0 69 , 49 , 114 179 159 137 40 6 85 - 63 130 156 , 175 14 Date Recue/Date Received 2022-02-03

13. A reception device, comprising:
a receiver configured to receive the transmission signal generated by the transmission device according to claim 12; and a processor connected to the receiver, the processor being configured to perform:
demapping the mapped bits according to the non-uniform 4096 QAM
scheme; and reversely reordering the N cyclic blocks according to the Table G.
Date Recue/Date Received 2022-02-03