CA2629796C - Process control system and method with multiplexed input-output device - Google Patents
Process control system and method with multiplexed input-output device Download PDFInfo
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Abstract
A process control system and method is provided.
The system comprises a process control device for issuing a requirement command with an added address and/or group ID and a plurality of multiplexed output devices which receive the requirement command and execute a process on the basis thereof. The addresses have a same part or the group ID that are set the same for the devices. Each device compares the same part (or the group ID) with a part of a further address (or group ID) added to the received requirement command. If the same part is equal to the part of the further address, the requirement command is identified. The address is then compared with the further address based on a result of the identification. If the address is equal to the further address added to the requirement command, the process based on the requirement command is executed.
The system comprises a process control device for issuing a requirement command with an added address and/or group ID and a plurality of multiplexed output devices which receive the requirement command and execute a process on the basis thereof. The addresses have a same part or the group ID that are set the same for the devices. Each device compares the same part (or the group ID) with a part of a further address (or group ID) added to the received requirement command. If the same part is equal to the part of the further address, the requirement command is identified. The address is then compared with the further address based on a result of the identification. If the address is equal to the further address added to the requirement command, the process based on the requirement command is executed.
Description
PROCESS CONTROL SYSTEM AND METHOD WITH
MULTIPLEXED INPUT-OUTPUT DEVICE
BACKGROUND OF THE INVENTION
This invention relates to access to input-output devices connected to a process control device, and more particularly to a process control system and a process control method, for controlling the switchover of input-output devices in multiplex configuration.
In the control of the access of the related art to the input-output devices in multiplex configuration in a process control system, the physical addresses assigned to the input-output devices are used. For example, Japanese Patent document, JP-A-59-27333, discloses an input/output control system wherein the identifiers such as, for example, the physical device numbers unique to the input-output devices are stored in the registers whose contents can be renewed;
the input-output devices are selected by the central processing device in accordance with their current identifiers stored in the registers; the input-output devices, upon receiving the data and the commands to change the current identifiers from the central processing device, generate new identifiers on the basis of the data; and the physical device numbers can be renewed by renewing the contents of the registers that are the current identifiers assigned uniquely to the input-output devices, with the newly generated identifiers.
Also, in the multiplex configuration of the related art, the input-output devices to be multiplexed can be mounted only in the adjacent mounting slots in a single I/O(input-output) device mounting unit.
Further, in case of output devices in multiplex configuration, a separate piece of hardware (AND/OR
devices or selector switch) must be provided inside or outside each of the output devices in order to control the switchover between the output devices. According to the configuration shown in Fig. 6 of Japanese Patent document, JP-A-7-152679, the paired output modules 221 and 222 and the paired input modules 223 and 224 are in the duplex configuration in the I/O module 22. The pairing of such output or input modules is conducted by adding, to the configuration information numbers assigned to the input or output modules mounted in the respective module mounting slots, the data meaning that the input or output modules mounted in the two adjacent slots are in the duplex configuration when the ID
information for each slot is renewed.
As disclosed in the Japanese Patent document, JP-A-7-152679, in the related art, the configuration of multiplexed input-output devices involved a physical restriction that the input-output devices to be multiplexed must be mounted only in the adjacent mounting slots in a single I/O device mounting unit.
This restriction is imposed due to the restriction on the transmission of interlock signals that necessitates the input-output devices to be multiplexed being mounted in the adjacent mounting slots in a single I/O
device mounting unit. Further, this multiplex configuration of the related art has a problem.
Namely, since the.input-output devices to be multiplexed are mounted in the adjacent slots in the single I/O device mounting unit, the multiplexed input-output devices become inoperable all together when a failure occurs affecting the whole I/O device mounting unit on which the multiplexed input-output devices are mounted.
SUMMARY OF THE INVENTION
An object of this invention is to provide a process control system and a process control method, wherein such a physical restriction can be eliminated by realizing a multiplex configuration of input-output devices through the provision of logic addresses for the input-output devices.
This invention, which has been made to solve such problems as are suffered by similar systems and methods of the related art, employs such following configuration as follows. Namely, according to a first feature of this invention, there is provided a process control system comprising a process control device for issuing a requirement command; a multiplexed input-output device for receiving the requirement command;
MULTIPLEXED INPUT-OUTPUT DEVICE
BACKGROUND OF THE INVENTION
This invention relates to access to input-output devices connected to a process control device, and more particularly to a process control system and a process control method, for controlling the switchover of input-output devices in multiplex configuration.
In the control of the access of the related art to the input-output devices in multiplex configuration in a process control system, the physical addresses assigned to the input-output devices are used. For example, Japanese Patent document, JP-A-59-27333, discloses an input/output control system wherein the identifiers such as, for example, the physical device numbers unique to the input-output devices are stored in the registers whose contents can be renewed;
the input-output devices are selected by the central processing device in accordance with their current identifiers stored in the registers; the input-output devices, upon receiving the data and the commands to change the current identifiers from the central processing device, generate new identifiers on the basis of the data; and the physical device numbers can be renewed by renewing the contents of the registers that are the current identifiers assigned uniquely to the input-output devices, with the newly generated identifiers.
Also, in the multiplex configuration of the related art, the input-output devices to be multiplexed can be mounted only in the adjacent mounting slots in a single I/O(input-output) device mounting unit.
Further, in case of output devices in multiplex configuration, a separate piece of hardware (AND/OR
devices or selector switch) must be provided inside or outside each of the output devices in order to control the switchover between the output devices. According to the configuration shown in Fig. 6 of Japanese Patent document, JP-A-7-152679, the paired output modules 221 and 222 and the paired input modules 223 and 224 are in the duplex configuration in the I/O module 22. The pairing of such output or input modules is conducted by adding, to the configuration information numbers assigned to the input or output modules mounted in the respective module mounting slots, the data meaning that the input or output modules mounted in the two adjacent slots are in the duplex configuration when the ID
information for each slot is renewed.
As disclosed in the Japanese Patent document, JP-A-7-152679, in the related art, the configuration of multiplexed input-output devices involved a physical restriction that the input-output devices to be multiplexed must be mounted only in the adjacent mounting slots in a single I/O device mounting unit.
This restriction is imposed due to the restriction on the transmission of interlock signals that necessitates the input-output devices to be multiplexed being mounted in the adjacent mounting slots in a single I/O
device mounting unit. Further, this multiplex configuration of the related art has a problem.
Namely, since the.input-output devices to be multiplexed are mounted in the adjacent slots in the single I/O device mounting unit, the multiplexed input-output devices become inoperable all together when a failure occurs affecting the whole I/O device mounting unit on which the multiplexed input-output devices are mounted.
SUMMARY OF THE INVENTION
An object of this invention is to provide a process control system and a process control method, wherein such a physical restriction can be eliminated by realizing a multiplex configuration of input-output devices through the provision of logic addresses for the input-output devices.
This invention, which has been made to solve such problems as are suffered by similar systems and methods of the related art, employs such following configuration as follows. Namely, according to a first feature of this invention, there is provided a process control system comprising a process control device for issuing a requirement command; a multiplexed input-output device for receiving the requirement command;
and a switchover function for switching between master and standby states of the input-output device, wherein the input-output device includes at least one input device or output device per unit each of which is mounted in an arbitrary slot; the input device or the output device is provided with an arbitrary logic address corresponding to a unique number,or code; and the process control device executes an address control for the input-output device by using the provided logic address to mount the input device or the output device in multiplex configuration in a slot of a different unit.
According to a second feature of this invention, there is provided a process control system wherein consecutive logic addresses are assigned to the multiplexed input-output device.
According to a third feature of this invention, there is provided a process control system wherein the switchover function is executed by an interlock device which turns on/off an output of the multiplexed input-output device by an interlock signal.
According to a fourth feature of this invention, there is provided a process control system wherein the switchover function is executed by software which switches between the master and standby states of the multiplexed input-output device based on the logic address.
According to a fifth feature of this invention, there is provided a process control system comprising a process control device for issuing a requirement command; multiplexed input-output devices for receiving the requirement command; and a switchover function for switching between master and standby states of the input-output device, wherein the input-output device has at least one input device or output per unit each of which is mounted in an arbitrary slot;
the input device or the output device in multiplex configuration is provided with a group ID which identifies a group of multiplexed input-output devices and with a logic address corresponding to a unique number or code or a physical address representing combination of the slot and the unit; and the process control device executes an address control for the input-output device by using the group ID to identify the input device or the output device in multiplex configuration; and the switchover function between the master and standby states of the multiplexed input-output devices is executed based on the logic address or the physical address.
According to a sixth feature of this invention, there is provided a process control method, comprising the steps of: mounting each of at least one of input device or output device per unit included in an input-output device in an arbitrary slot; providing the input device or the output device with an arbitrary logic address corresponding to a unique number or code;
According to a second feature of this invention, there is provided a process control system wherein consecutive logic addresses are assigned to the multiplexed input-output device.
According to a third feature of this invention, there is provided a process control system wherein the switchover function is executed by an interlock device which turns on/off an output of the multiplexed input-output device by an interlock signal.
According to a fourth feature of this invention, there is provided a process control system wherein the switchover function is executed by software which switches between the master and standby states of the multiplexed input-output device based on the logic address.
According to a fifth feature of this invention, there is provided a process control system comprising a process control device for issuing a requirement command; multiplexed input-output devices for receiving the requirement command; and a switchover function for switching between master and standby states of the input-output device, wherein the input-output device has at least one input device or output per unit each of which is mounted in an arbitrary slot;
the input device or the output device in multiplex configuration is provided with a group ID which identifies a group of multiplexed input-output devices and with a logic address corresponding to a unique number or code or a physical address representing combination of the slot and the unit; and the process control device executes an address control for the input-output device by using the group ID to identify the input device or the output device in multiplex configuration; and the switchover function between the master and standby states of the multiplexed input-output devices is executed based on the logic address or the physical address.
According to a sixth feature of this invention, there is provided a process control method, comprising the steps of: mounting each of at least one of input device or output device per unit included in an input-output device in an arbitrary slot; providing the input device or the output device with an arbitrary logic address corresponding to a unique number or code;
and executing, by a process control device, an address control for the input-output device by using the provided logic address to mount the input device or the output device in multiplex configuration in a slot of a different unit.
According to a seventh feature of this invention, there is provided a process control method, comprising the steps of: mounting each of at least one input device or output device per unit included in an input-output device in an arbitrary slot; providing an input device or output device in multiplex configuration with a group ID which identifies a group of multiplexed input-output devices and with a logic address corresponding to a unique number or code or a physical address representing combination of the slot and the unit; and executing, by the process control device, an address control of the input-output device by using the group ID to identify the input device or the output device in multiplex configuration; and executing a switching function between the master and standby states of the multiplexed input-output device based on the logic address or the physical address.
According to this invention, access to the multiplexed input and output devices is made through the use of logic addresses instead of physical addresses, and therefore physical restrictions are eliminated, whereby the degree of freedom in mounting input and output devices as well as the resistance to failure is increased.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram of the process control system according to a first embodiment of this invention;
Fig. 2 is a block diagram showing the output devices in duplex configuration included in the process control system according to the first embodiment;
Fig. 3 schematically shows the format of a requirement command issued from the process control device included in the process control system according to the first embodiment;
Fig. 4 is a flow chart for the operation of the process control device issuing the requirement command, according to the first embodiment;
Fig. 5 is a flowchart for the operation of switching over among the output devices in multiplex configuration according to the first embodiment;
Fig. 6 shows graphs illustrating by state transitions the moment of switchover from one output device to the other in duplex configuration according to the first embodiment (similar to a second embodiment);
According to a seventh feature of this invention, there is provided a process control method, comprising the steps of: mounting each of at least one input device or output device per unit included in an input-output device in an arbitrary slot; providing an input device or output device in multiplex configuration with a group ID which identifies a group of multiplexed input-output devices and with a logic address corresponding to a unique number or code or a physical address representing combination of the slot and the unit; and executing, by the process control device, an address control of the input-output device by using the group ID to identify the input device or the output device in multiplex configuration; and executing a switching function between the master and standby states of the multiplexed input-output device based on the logic address or the physical address.
According to this invention, access to the multiplexed input and output devices is made through the use of logic addresses instead of physical addresses, and therefore physical restrictions are eliminated, whereby the degree of freedom in mounting input and output devices as well as the resistance to failure is increased.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram of the process control system according to a first embodiment of this invention;
Fig. 2 is a block diagram showing the output devices in duplex configuration included in the process control system according to the first embodiment;
Fig. 3 schematically shows the format of a requirement command issued from the process control device included in the process control system according to the first embodiment;
Fig. 4 is a flow chart for the operation of the process control device issuing the requirement command, according to the first embodiment;
Fig. 5 is a flowchart for the operation of switching over among the output devices in multiplex configuration according to the first embodiment;
Fig. 6 shows graphs illustrating by state transitions the moment of switchover from one output device to the other in duplex configuration according to the first embodiment (similar to a second embodiment);
Fig. 7 is a block diagram of the process control system according to a second embodiment of this invention;
Fig. 8 is a block diagram showing the output devices in duplex configuration included in the process control system according to the second embodiment;
Fig. 9 is a flow chart for the switchover operation taking place between output devices in multiplex configuration, according to the second embodiment;
Fig. 10 is a block diagram of the process control system according to a third embodiment of this invention;
Fig. 11 is a block diagram showing the output devices in multiplex configuration included in the process control system according to the third embodiment;
Fig. 12 schematically shows the format of a requirement command issued from the process control device included in the process control system according to the third embodiment;
Fig. 13 is a flow chart for the switchover operation taking place between output devices according to the third embodiment;
Fig. 14 is a flowchart for the operation of switching over among the output devices in multiplex configuration according to the third embodiment;
Fig. 15 shows graphs illustrating by the state transition the moment of switchover from one output device to another in the multiplex configuration according to the third embodiment;
Fig. 16 is a block diagram of the process control system according to a fourth embodiment;
Fig. 17 shows in block diagram the multiplex configuration of the output devices as the fourth embodiment;
Fig. 18 schematically shows the format of a requirement command issued from the process control device;
Fig. 19 is a flowchart for the operation of switching over among the output devices in multiplex configuration according to the fourth embodiment; and Fig. 20 graphically shows the operations of the multiplexed output devices generating output demands when the process control device issues a requirement command, according to the fourth embodiment.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The first through fourth embodiments of the process control system according to this invention will now be described in detail with reference to Figs. l.
through 20 of the attached drawings.
[Embodiment 11 Figs. 1 through 6 are related to the first embodiment of the process control system according to this invention. Fig. 1 shows a block diagram of the process control system according to the first embodiment of this invention. Fig. 2 is a block diagram showing the output devices in duplex configuration included in the process control system according to the first embodiment. Fig. 3 schematically shows the format of a requirement command issued from the process control device included in the process control system according to the first embodiment. Fi.g. 4 is a flow chart for the operation of the process control device issuing the requirement command, according to the first embodiment. Fig. 5 is a flowchart for the operation of switching over among the output devices in multiplex configuration according to the first embodiment. Fig. 6 shows graphs illustrating by state transition the moment of switchover from one output device to the other in multiplex configuration according to the first embodiment of this invention.
As shown in Fig. 1, the process control system of this invention comprises a process control.
device 101; input and output device mounting units 102a, 102b, each with input and output devices mounted thereon; input devices 103a-1, 103a-2, 103b-1, 103b-2 for inputting data; output devices 103a-3, 103b-3 for outputting data; transmission/reception paths 104a, 104b for transmitting/receiving a switchover requirement command; logic addresses 105a-1 - 105a-3, 105b-1 - 105b-3 assigned respectively to the input devices 103a-1, 103a-2, 103b-1, 103b-2 and the output devices output devices 103a-3, 103b-3; interlock signal buses 106-1, 106-2 for the interlock signals to go through between the output devices 103a-3, 103b-3; an output data transmission channel 107; input and output device mounting slot numbers 108a-1 - 108a-3, 108b-1 -108b-3; and input and output device mounting unit numbers 109a, 109b for uniquely identifying the input and output device mounting units 102a, 102b.
The process control device 101 performs arithmetic operations for controlling the inputs from the input and output devices, delivers outputs to the output devices, and issues a switchover requirement command for the input-output devices in duplex configuration. The combinations of the input and output device mounting unit numbers 109a, 109b for uniquely identifying the input and output device mounting units 102a, 102b and the input and output device mounting slot numbers 108a-1 - 108a-3, 108b-1. -108b-3, give the physical addresses, that is, addresses used in the related arts. In the embodiments of this invention, the logic addresses are used instead of the physical addresses to access the input-output devices.
Here, the logic addresses refer to the ID numbers or codes assigned uniquely to individual input-output devices. The numbers "2", "411, "6", "8", "1011, and 11711 indicated at 105a-1 - 105a-3, 105b-1 - 105b-3 in Fig.1 are the logic addresses, and also referred to as the self logic addresses of the input and output devices.
Here, in input devices 103a-1, 103a-2, 103b-1, 103b-2, and output devices 103a-3, 103b-3, if the logic address, expressed in hexadecimal notation, of a device is different from the logic address, expressed in hexadecimal notation, of another like device only by their least significant bits, they are deemed to be in duplex configu2:-ation. In the example shown in Fig. 1, the output devices 103a-3 and 103b-3 are in duplex configuration since the logic address "6" of the output device 103a-3 is expressed as "Ox0110" in hexadecimal notation whereas the logic address "711 of the output device 103b-3 is expressed as "Ox011l" in hexadecimal notation, so that they differ from each other only by their least significant bits.
Fig. 2 is a block diagram showing the output devices 103a-3 and 103b-3 in duplex configuration, according to the first embodiment of this invention.
As shown in Fig. 2, the output devices 103a-3, 103b-3 respectively include command reception units 201a, 201b for receiving various commands issued from the process control device 101; command judgment units 202a, 202b for judging the commands received by the command reception units 201a, 201b; I/O output units 203a, 203b for delivering the "output" data when the results of judgment made in the command judgment units 202a, 202b indicate the output of the I/O output data; interlock devices 205a, 205b for accepting the "output ON"
requirements when the results of judgment made in the command judgment units 202a, 202b indicate the "output ON"; output switching units 204a, 204b for controlling the ON/OFF of the "output" data delivered from the I/O
output units 203a, 203b in response to the interlocking signals outputted from the interlock devices 205a, 205b; and the logic address holding units 206b for storing the self logic addresses of the output devices 103a-3, 103b-3 themselves. The output switching units 204a, 204b operate in gang with each other in such a manner that one, for example 204a, is in the ON state while the other, for example 204b, is in the OFF state, and vice versa. The switch over between the ON and OFF
states of the output switching units 204a, 204b is controlled by the interlock devices 205a, 205b.
Fig. 3 shows the format of the requirement command 301 issued from the process control device 101.
The format consists of a destination logic address 302 and requirement command data 303.
Fig. 4 is a flow chart for the operation of issuing a switchover requirement command when such a switchover requirement is raised through the manipulation on, for example, a human machine interface (HMI) screen in. the system containing the output devices 103a-3, 103b-3 in duplex configuration, or when the master side output device in the duplex configuration fails. In Step 401, judgment is passed whether or not there is need for switching over between the master and standby for output devices 103a-3, 103b-3. If there is such a need, the requirement command 301 is issued, in Step 402, to the logic address of the output device 103a-3 or 103b-3 which is to serve as the master output device.
Fig. 5 is a flow chart for the operation of switching over between the output devices 103a-3, 103b-3 according to the first embodiment of this invention.
The following description is dedicated to the procedure shown in Fig. 5 for the time being, but concrete examples of the procedure will be described later.
In Step 501, the command reception units 201a, 201b receive the requirement command 301 issued from the process control device 101. In Step 502, comparison is made between the destination logic address 302, whose least significant bit has been masked, of the requirement command 301 received in Step 501 and the self logic address, whose least significant bit has been also masked, stored in the logic address holding unit 206a or 206b. If the result of comparison indicates that the compared logic addresses are different from each other, decision is made that the output device subjected to the address comparison is 25= not the output device to be switched, so that the flow comes to an end without doing anything further. If, on the other hand, the result indicates that the compared addresses are the same as each other, Step 503 is reached.
In Step 503, the content of the requirement command data 303 is checked. If the content is the "output ON" requirement, Step 504 is reached. On the other hand, if the content is the "I/O output data"
requirement, Step 506 is reached. In Step 504, comparison is made between the destination logic address 302, whose least significant bit is not masked, of the requirement command 301 and the self logic address, whose least significant bit is not masked, stored in the logic address holding unit 206a or 206b.
If the result of comparison indicates that the compared logic addresses are different from each other, decision is made that the output device subjected to the address comparison is not the output device to be switched in the duplex configuration (The output device is in the stand-by mode.), so that the flow ends without doing anything further.
If, on the other hand, the result is that the compared logic addresses are the same as each other, the output devices 103a-3, 103b-3 in the duplex configuration are deemed to be switched over, so that Step 505 is then reached. In Step 505, the "output ON"
requirement is issued to the interlock devices 205a, 206b. If the decision in Step 503 is the "I/O output data" requirement, the requirement of the "I/O output data" is issued to the I/O output units 203a, 203b is Step 506.
Fig. 8 is a block diagram showing the output devices in duplex configuration included in the process control system according to the second embodiment;
Fig. 9 is a flow chart for the switchover operation taking place between output devices in multiplex configuration, according to the second embodiment;
Fig. 10 is a block diagram of the process control system according to a third embodiment of this invention;
Fig. 11 is a block diagram showing the output devices in multiplex configuration included in the process control system according to the third embodiment;
Fig. 12 schematically shows the format of a requirement command issued from the process control device included in the process control system according to the third embodiment;
Fig. 13 is a flow chart for the switchover operation taking place between output devices according to the third embodiment;
Fig. 14 is a flowchart for the operation of switching over among the output devices in multiplex configuration according to the third embodiment;
Fig. 15 shows graphs illustrating by the state transition the moment of switchover from one output device to another in the multiplex configuration according to the third embodiment;
Fig. 16 is a block diagram of the process control system according to a fourth embodiment;
Fig. 17 shows in block diagram the multiplex configuration of the output devices as the fourth embodiment;
Fig. 18 schematically shows the format of a requirement command issued from the process control device;
Fig. 19 is a flowchart for the operation of switching over among the output devices in multiplex configuration according to the fourth embodiment; and Fig. 20 graphically shows the operations of the multiplexed output devices generating output demands when the process control device issues a requirement command, according to the fourth embodiment.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The first through fourth embodiments of the process control system according to this invention will now be described in detail with reference to Figs. l.
through 20 of the attached drawings.
[Embodiment 11 Figs. 1 through 6 are related to the first embodiment of the process control system according to this invention. Fig. 1 shows a block diagram of the process control system according to the first embodiment of this invention. Fig. 2 is a block diagram showing the output devices in duplex configuration included in the process control system according to the first embodiment. Fig. 3 schematically shows the format of a requirement command issued from the process control device included in the process control system according to the first embodiment. Fi.g. 4 is a flow chart for the operation of the process control device issuing the requirement command, according to the first embodiment. Fig. 5 is a flowchart for the operation of switching over among the output devices in multiplex configuration according to the first embodiment. Fig. 6 shows graphs illustrating by state transition the moment of switchover from one output device to the other in multiplex configuration according to the first embodiment of this invention.
As shown in Fig. 1, the process control system of this invention comprises a process control.
device 101; input and output device mounting units 102a, 102b, each with input and output devices mounted thereon; input devices 103a-1, 103a-2, 103b-1, 103b-2 for inputting data; output devices 103a-3, 103b-3 for outputting data; transmission/reception paths 104a, 104b for transmitting/receiving a switchover requirement command; logic addresses 105a-1 - 105a-3, 105b-1 - 105b-3 assigned respectively to the input devices 103a-1, 103a-2, 103b-1, 103b-2 and the output devices output devices 103a-3, 103b-3; interlock signal buses 106-1, 106-2 for the interlock signals to go through between the output devices 103a-3, 103b-3; an output data transmission channel 107; input and output device mounting slot numbers 108a-1 - 108a-3, 108b-1 -108b-3; and input and output device mounting unit numbers 109a, 109b for uniquely identifying the input and output device mounting units 102a, 102b.
The process control device 101 performs arithmetic operations for controlling the inputs from the input and output devices, delivers outputs to the output devices, and issues a switchover requirement command for the input-output devices in duplex configuration. The combinations of the input and output device mounting unit numbers 109a, 109b for uniquely identifying the input and output device mounting units 102a, 102b and the input and output device mounting slot numbers 108a-1 - 108a-3, 108b-1. -108b-3, give the physical addresses, that is, addresses used in the related arts. In the embodiments of this invention, the logic addresses are used instead of the physical addresses to access the input-output devices.
Here, the logic addresses refer to the ID numbers or codes assigned uniquely to individual input-output devices. The numbers "2", "411, "6", "8", "1011, and 11711 indicated at 105a-1 - 105a-3, 105b-1 - 105b-3 in Fig.1 are the logic addresses, and also referred to as the self logic addresses of the input and output devices.
Here, in input devices 103a-1, 103a-2, 103b-1, 103b-2, and output devices 103a-3, 103b-3, if the logic address, expressed in hexadecimal notation, of a device is different from the logic address, expressed in hexadecimal notation, of another like device only by their least significant bits, they are deemed to be in duplex configu2:-ation. In the example shown in Fig. 1, the output devices 103a-3 and 103b-3 are in duplex configuration since the logic address "6" of the output device 103a-3 is expressed as "Ox0110" in hexadecimal notation whereas the logic address "711 of the output device 103b-3 is expressed as "Ox011l" in hexadecimal notation, so that they differ from each other only by their least significant bits.
Fig. 2 is a block diagram showing the output devices 103a-3 and 103b-3 in duplex configuration, according to the first embodiment of this invention.
As shown in Fig. 2, the output devices 103a-3, 103b-3 respectively include command reception units 201a, 201b for receiving various commands issued from the process control device 101; command judgment units 202a, 202b for judging the commands received by the command reception units 201a, 201b; I/O output units 203a, 203b for delivering the "output" data when the results of judgment made in the command judgment units 202a, 202b indicate the output of the I/O output data; interlock devices 205a, 205b for accepting the "output ON"
requirements when the results of judgment made in the command judgment units 202a, 202b indicate the "output ON"; output switching units 204a, 204b for controlling the ON/OFF of the "output" data delivered from the I/O
output units 203a, 203b in response to the interlocking signals outputted from the interlock devices 205a, 205b; and the logic address holding units 206b for storing the self logic addresses of the output devices 103a-3, 103b-3 themselves. The output switching units 204a, 204b operate in gang with each other in such a manner that one, for example 204a, is in the ON state while the other, for example 204b, is in the OFF state, and vice versa. The switch over between the ON and OFF
states of the output switching units 204a, 204b is controlled by the interlock devices 205a, 205b.
Fig. 3 shows the format of the requirement command 301 issued from the process control device 101.
The format consists of a destination logic address 302 and requirement command data 303.
Fig. 4 is a flow chart for the operation of issuing a switchover requirement command when such a switchover requirement is raised through the manipulation on, for example, a human machine interface (HMI) screen in. the system containing the output devices 103a-3, 103b-3 in duplex configuration, or when the master side output device in the duplex configuration fails. In Step 401, judgment is passed whether or not there is need for switching over between the master and standby for output devices 103a-3, 103b-3. If there is such a need, the requirement command 301 is issued, in Step 402, to the logic address of the output device 103a-3 or 103b-3 which is to serve as the master output device.
Fig. 5 is a flow chart for the operation of switching over between the output devices 103a-3, 103b-3 according to the first embodiment of this invention.
The following description is dedicated to the procedure shown in Fig. 5 for the time being, but concrete examples of the procedure will be described later.
In Step 501, the command reception units 201a, 201b receive the requirement command 301 issued from the process control device 101. In Step 502, comparison is made between the destination logic address 302, whose least significant bit has been masked, of the requirement command 301 received in Step 501 and the self logic address, whose least significant bit has been also masked, stored in the logic address holding unit 206a or 206b. If the result of comparison indicates that the compared logic addresses are different from each other, decision is made that the output device subjected to the address comparison is 25= not the output device to be switched, so that the flow comes to an end without doing anything further. If, on the other hand, the result indicates that the compared addresses are the same as each other, Step 503 is reached.
In Step 503, the content of the requirement command data 303 is checked. If the content is the "output ON" requirement, Step 504 is reached. On the other hand, if the content is the "I/O output data"
requirement, Step 506 is reached. In Step 504, comparison is made between the destination logic address 302, whose least significant bit is not masked, of the requirement command 301 and the self logic address, whose least significant bit is not masked, stored in the logic address holding unit 206a or 206b.
If the result of comparison indicates that the compared logic addresses are different from each other, decision is made that the output device subjected to the address comparison is not the output device to be switched in the duplex configuration (The output device is in the stand-by mode.), so that the flow ends without doing anything further.
If, on the other hand, the result is that the compared logic addresses are the same as each other, the output devices 103a-3, 103b-3 in the duplex configuration are deemed to be switched over, so that Step 505 is then reached. In Step 505, the "output ON"
requirement is issued to the interlock devices 205a, 206b. If the decision in Step 503 is the "I/O output data" requirement, the requirement of the "I/O output data" is issued to the I/O output units 203a, 203b is Step 506.
Now, the flow chart shown in Fig. 5 will be described as it is applied to a concrete example of a procedure. Let it be first assumed for the sake of clarity that the self logic addresses of the output devices 103a-3 and 103b-3 in duplex configuration shown in Fig. 1 are 116" and "7", respectively, and that the destination logic address be "711 as shown in Fig. 3.
Further, for the sake of simplifying the following description, it is also assumed that the destination logic address 302 takes one of the values 115", "6" and 11711 only. In hexadecimal notation, 115" is expressed as "Ox0101", "6" as "Ox01l0", and "7" as "Ox0l11".
As shown in Fig. 5, comparison is made, in Step 502, between the destination logic address 302, whose least significant bit has been masked, and the self logic address stored in the logic address holding unit 206 shown in Fig. 2, whose least significant bit has also been masked. In case of the destination logic address 302 being "5", the LSB-masking (i.e. masking of the least significant bit) renders the destination logic address "5" (i.e. Ox0101) to "OxOlOO".
Therefore, the LSB-masked destination logic address "OxOlOO" is different from either of the LSB-masked version "Ox0l10" of the logic address "6" (i.e. Ox0110) stored in the logic address holding unit 206a and the LSB-masked version "Ox0110" of the logic address "7"
(i.e. Ox0ll1) stored in the logic address holding unit 206b. Accordingly, the "NO" branch is taken in Step 502. In case of the destination logic address 302 being 116" or "711, the LSB-masking gives "Ox0l10" for both "6" and "7". The LSB-masking of the self logic address "6 11 or 117" also gives OXO11O ll Since the LSB-masked version of the destination logic address 302 and the LSB-masked version of the self logic address "6" or "7" are the same as each other, the "YES" branch is taken in Step 502.
As shown in Fig. 3, let it be assumed that the requirement command data 303 is "output ON" and the destination logic address is 117". Then, the destination logic address "7" is the same as the self logic address "711 of the output device 103b-3 so that the "YES" branch is taken in Step 504. As a result, the "output ON" requirement is issued to the interlock device 205b to cause the output device 103b-3 to shift from the standby state to the master state. Also, in Step 504, comparison is made between the destination logic address "7" and the self logic address "6" of the output device 103a-3. Accordingly, the result of comparison indicates that they are different from each other and therefore causes the "NO" branch to be taken, and the flow ends.
Fig. 6 graphically shows the operation of switching the output devices 103a-3 and 103b-3 between their standby and master states when the process control device 101 issues the switchover requirement command. Now, detailed description is made of the switchover of the output devices according to the first embodiment of this invention, in reference to Figs. 1 through 6.
As shown in Fig. 1, it is assumed that the output devices 103a-3 and 103b-3 are in the duplex configuration, that the self logic address 105a-3 of the output device 103a-3 is "6" whereas the self logic address 105b-3 of the output device 103b-3 is 11711, and that the output device 103a-3 is in the master state whereas the output device 103b-3 is in the standby state.
Let it be assumed that a failure occurred in the output device 103a-3. Then, the process control device 101 passes judgment that there is need for the switchover between the master output device and the standby output device, as in Step 401 in Fig.4. In Step 402, the switchover requirement command is issued to the self logic address of the output device which is to serve as master output device. The output device which is now to serve as master output device is the output device 103b-3 that has served as standby output device up to now. Notably, the destination logic address 302 of the issued requirement command 301 is "7" that is the same as the self logic address "7" of the output device 103b-3, and the requirement command data 303 of the issued requirement command 301 is "output ON".
The issued requirement command 301 is received by the output devices 103a-3, 103b-3 to initiate the switchover operation as indicated in the flow chart shown in Fig. 5. In the following are given the descriptions of the switchover operations associated with the output devices 103a-3 and 103b-3 in this order mentioned.
First, in Step 501, the command reception unit 201a of the output device 103a-3 receives the requirement command 301. In Step 502, the command judgment unit 202a masks the least significant bit of the destination logic address 302 of the requirement command 301 whose address value is "7", or "Ox011l" in terms of hexadecimal notation. As a result, the masked value becomes "Ox0110", i.e. "6" in decimal notation.
The command judgment unit 202a also masks the least significant bit of the self logic address fetched from the logic address holding unit 206a. That is, the logic address 105a-3 is masked with "6", i.e. "Ox0110" in hexadecimal notation, of the output device 103a-3.
Thus, the masked result is still "Ox0l10ll, i.e. "6" in decimal notation. The command judgment unit 202a compares both the masked values with each other and decides that they are equal to each other, both being "6 . Accordingly, Step 503 is reached.
Since the requirement command data 303 of the requirement command 301 is "output ON", Step 504 is reached. In Step 504, comparison is made between the destination logic address 302 of the requirement command 301, whose address value is "7" or "OxOlli", and the self logic address fetched from the logic address holding unit 206a, that is, the logic address 105a-3, whose address value is "6", of the output device 103a-3, i.e. "Ox0110ll. The result of the comparison indicates that they are different from each other since they are "7" and "6". Accordingly, the flow comes to the end without executing any further process.
In Step 501, the command reception unit 201b of the output device 103b-3 also receives the requirement command 301. In Step 502, the command judgment unit 202b masks the least significant bit of the destination logic address 302 of the requirement command 301 whose address value is "7", or "Ox011l" in terms of hexadecimal notation. As a result, the masked value becomes "Ox01l0", i.e. 116" in decimal notation.
The command judgment unit 202b also masks the least significant bit of the self logic address fetched from the logic address holding unit 206b, that is, the logic address 105b-3, whose address value is "7", of the output device 103b-3, i.e. "Ox0111 in hexadecimal notation. Thus, the masked result is "Ox01l0", i.e.
"6" in decimal notation. The command judgment unit 202a compares both the masked values with each other and decides that they are equal to each other, both being "6". Accordingly, Step 503 is reached.
Since the requirement command data 303 of the requirement command 301 is "output ON", Step 504 is reached. In Step 504, comparison is made between the destination logic address 302, whose address value is "7", of the requirement command 301 and the self logic address fetched from the logic address holding unit 206b, that is, the logic address 105b-3, whose address value is "711, of the output device 103b-3. The result of the comparison indicates that they are equal to each other so that Step 505 is reached. Then, in Step 505, the interlock device 205b is required to issue the "output ON" signal, which drives the output switching unit 204b into its ON state. Simultaneously, the "output OFF" signal is sent to the interlock device 205a via the interlock signal bus 106-1 so that the output switching unit 204a is turned off.
Consequently, the switchover is performed from the output device 103a-3 to the output device 103b-3: the output device 103b-3 entering into the master state whereas the output device 103a-3 receding into the standby state. The switchover between the master and standby states takes place at a time as shown in Fig.
6, through the simultaneous operations of the interlock deviceds205a, 205b.
As described above, according to the process control system of the present invention, the use of the "logic address" instead of the "physical address"
enables the input-output devices in the multiplex configuration to be installed in separate I/0 device mounting units. This is remarkable difference from the related arts mentioned above where the multiplexed input-output devices must be located adjacent to each other on the same I/O device mounting unit. Namely, If the physical address is used as in the related arts, two kinds of physical numbers such as unit number and slot number are required to be identified. Moreover, the physical number of a certain piece of hardware niust be matched to the physical number of the corresponding piece of software. This leads to complexity in preparatory procedure.
For example, in the duplex configuration of I/0 (input and output) modules (similarly in the multiplex configuration of the input and output devices), it is necessary to identify not only the unit and slot numbers of one device but also the unit and slot numbers of the other device. This complexity in identification is intrinsic since it is indispensable to identify the paired devices in the control of input and output devices in duplex configuration. On the other hand, according to this invention, use is made of the logic address assigned uniquely to each device, and there is no need for identifying two physical numbers (such as a unit number and a slot number) assigned to each device as in the related arts. Thus, laboriousness and complexity can be reduced. This feature and advantage of the present invention is provided in not only the first embodiment of the invention but also the other embodiments of the invention described hereafter.
[Embodiment 21 Figs. 7 - 9 are related to the second embodiment of the process control system according to this invention. Fig. 7 is a block diagram of the process control system according to the second embodiment of this invention. Fig. 8 is a block diagram showing the output devices in duplex configuration included in the process control system according to the second embodiment. Fig. 9 is a flow chart for the switchover operation taking place between output devices in duplex configuration according to the second embodiment.
This second embodiment differs from the first embodiment in that it lacks the interlock signal buses 106-1, 106-2 shown in Fig. 2. In the second embodiment, as shown in Fig. 8, the command judgment units 801a, 801b of output devices 103a, 103b directly drive the output switching units 204a, 204b for the setting of outputs. Therefore, the output devices 103a, 103b also lack the interlock devices 205a, 205b shown in Fig. 2. Except for these differences, the first and second embodiments of this invention are the same as each other.
As shown in Fig. 9, in the flow chart for the switchover operation taking place between output devices 103a, 103b, Steps 501 through 506 are the same as those shown in the flow chart in fig. 5 associated with the first embodiment. Steps 901 and 902 are different ones. In Step 901, if the comparison between the destination logic address 302 of the requirement command 301 and the self logic address of the output device 103 indicates that the logic addresses are the same as each other, the output switching unit 204 is directly driven to the "ON" state. If, on the contrary, the logic addresses are different from each other, the output switching unit 204 is directly driven to the "OFF" state in Step 902. Thus, these steps 901 and 902 enable the settings of the output ON/OFF in either of the output devices 103a, 103b. The switchover procedure performed on the side of the process control device 101 is the same as that shown in the flow chart in Fig. 4 associated with the first embodiment described above.
The switchover operation according to the second embodiment of this invention will now be described in detail. As seen in Fig. 7 showing the process control system according to the second invention of this invention, it is assumed that the output devices 103a-3, 103b-3 are in the duplex configuration, that the self logic address of the output device 103a-3 is "6" whereas the self logic address of the output device 103b-3 is "7", and that the output device 103a-3 is in the master state whereas the output device 103b-3 is in the standby state.
Further, for the sake of simplifying the following description, it is also assumed that the destination logic address 302 takes one of the values 115", "6" and 11711 only. In hexadecimal notation, 115" is expressed as "Ox0101", "6" as "Ox01l0", and "7" as "Ox0l11".
As shown in Fig. 5, comparison is made, in Step 502, between the destination logic address 302, whose least significant bit has been masked, and the self logic address stored in the logic address holding unit 206 shown in Fig. 2, whose least significant bit has also been masked. In case of the destination logic address 302 being "5", the LSB-masking (i.e. masking of the least significant bit) renders the destination logic address "5" (i.e. Ox0101) to "OxOlOO".
Therefore, the LSB-masked destination logic address "OxOlOO" is different from either of the LSB-masked version "Ox0l10" of the logic address "6" (i.e. Ox0110) stored in the logic address holding unit 206a and the LSB-masked version "Ox0110" of the logic address "7"
(i.e. Ox0ll1) stored in the logic address holding unit 206b. Accordingly, the "NO" branch is taken in Step 502. In case of the destination logic address 302 being 116" or "711, the LSB-masking gives "Ox0l10" for both "6" and "7". The LSB-masking of the self logic address "6 11 or 117" also gives OXO11O ll Since the LSB-masked version of the destination logic address 302 and the LSB-masked version of the self logic address "6" or "7" are the same as each other, the "YES" branch is taken in Step 502.
As shown in Fig. 3, let it be assumed that the requirement command data 303 is "output ON" and the destination logic address is 117". Then, the destination logic address "7" is the same as the self logic address "711 of the output device 103b-3 so that the "YES" branch is taken in Step 504. As a result, the "output ON" requirement is issued to the interlock device 205b to cause the output device 103b-3 to shift from the standby state to the master state. Also, in Step 504, comparison is made between the destination logic address "7" and the self logic address "6" of the output device 103a-3. Accordingly, the result of comparison indicates that they are different from each other and therefore causes the "NO" branch to be taken, and the flow ends.
Fig. 6 graphically shows the operation of switching the output devices 103a-3 and 103b-3 between their standby and master states when the process control device 101 issues the switchover requirement command. Now, detailed description is made of the switchover of the output devices according to the first embodiment of this invention, in reference to Figs. 1 through 6.
As shown in Fig. 1, it is assumed that the output devices 103a-3 and 103b-3 are in the duplex configuration, that the self logic address 105a-3 of the output device 103a-3 is "6" whereas the self logic address 105b-3 of the output device 103b-3 is 11711, and that the output device 103a-3 is in the master state whereas the output device 103b-3 is in the standby state.
Let it be assumed that a failure occurred in the output device 103a-3. Then, the process control device 101 passes judgment that there is need for the switchover between the master output device and the standby output device, as in Step 401 in Fig.4. In Step 402, the switchover requirement command is issued to the self logic address of the output device which is to serve as master output device. The output device which is now to serve as master output device is the output device 103b-3 that has served as standby output device up to now. Notably, the destination logic address 302 of the issued requirement command 301 is "7" that is the same as the self logic address "7" of the output device 103b-3, and the requirement command data 303 of the issued requirement command 301 is "output ON".
The issued requirement command 301 is received by the output devices 103a-3, 103b-3 to initiate the switchover operation as indicated in the flow chart shown in Fig. 5. In the following are given the descriptions of the switchover operations associated with the output devices 103a-3 and 103b-3 in this order mentioned.
First, in Step 501, the command reception unit 201a of the output device 103a-3 receives the requirement command 301. In Step 502, the command judgment unit 202a masks the least significant bit of the destination logic address 302 of the requirement command 301 whose address value is "7", or "Ox011l" in terms of hexadecimal notation. As a result, the masked value becomes "Ox0110", i.e. "6" in decimal notation.
The command judgment unit 202a also masks the least significant bit of the self logic address fetched from the logic address holding unit 206a. That is, the logic address 105a-3 is masked with "6", i.e. "Ox0110" in hexadecimal notation, of the output device 103a-3.
Thus, the masked result is still "Ox0l10ll, i.e. "6" in decimal notation. The command judgment unit 202a compares both the masked values with each other and decides that they are equal to each other, both being "6 . Accordingly, Step 503 is reached.
Since the requirement command data 303 of the requirement command 301 is "output ON", Step 504 is reached. In Step 504, comparison is made between the destination logic address 302 of the requirement command 301, whose address value is "7" or "OxOlli", and the self logic address fetched from the logic address holding unit 206a, that is, the logic address 105a-3, whose address value is "6", of the output device 103a-3, i.e. "Ox0110ll. The result of the comparison indicates that they are different from each other since they are "7" and "6". Accordingly, the flow comes to the end without executing any further process.
In Step 501, the command reception unit 201b of the output device 103b-3 also receives the requirement command 301. In Step 502, the command judgment unit 202b masks the least significant bit of the destination logic address 302 of the requirement command 301 whose address value is "7", or "Ox011l" in terms of hexadecimal notation. As a result, the masked value becomes "Ox01l0", i.e. 116" in decimal notation.
The command judgment unit 202b also masks the least significant bit of the self logic address fetched from the logic address holding unit 206b, that is, the logic address 105b-3, whose address value is "7", of the output device 103b-3, i.e. "Ox0111 in hexadecimal notation. Thus, the masked result is "Ox01l0", i.e.
"6" in decimal notation. The command judgment unit 202a compares both the masked values with each other and decides that they are equal to each other, both being "6". Accordingly, Step 503 is reached.
Since the requirement command data 303 of the requirement command 301 is "output ON", Step 504 is reached. In Step 504, comparison is made between the destination logic address 302, whose address value is "7", of the requirement command 301 and the self logic address fetched from the logic address holding unit 206b, that is, the logic address 105b-3, whose address value is "711, of the output device 103b-3. The result of the comparison indicates that they are equal to each other so that Step 505 is reached. Then, in Step 505, the interlock device 205b is required to issue the "output ON" signal, which drives the output switching unit 204b into its ON state. Simultaneously, the "output OFF" signal is sent to the interlock device 205a via the interlock signal bus 106-1 so that the output switching unit 204a is turned off.
Consequently, the switchover is performed from the output device 103a-3 to the output device 103b-3: the output device 103b-3 entering into the master state whereas the output device 103a-3 receding into the standby state. The switchover between the master and standby states takes place at a time as shown in Fig.
6, through the simultaneous operations of the interlock deviceds205a, 205b.
As described above, according to the process control system of the present invention, the use of the "logic address" instead of the "physical address"
enables the input-output devices in the multiplex configuration to be installed in separate I/0 device mounting units. This is remarkable difference from the related arts mentioned above where the multiplexed input-output devices must be located adjacent to each other on the same I/O device mounting unit. Namely, If the physical address is used as in the related arts, two kinds of physical numbers such as unit number and slot number are required to be identified. Moreover, the physical number of a certain piece of hardware niust be matched to the physical number of the corresponding piece of software. This leads to complexity in preparatory procedure.
For example, in the duplex configuration of I/0 (input and output) modules (similarly in the multiplex configuration of the input and output devices), it is necessary to identify not only the unit and slot numbers of one device but also the unit and slot numbers of the other device. This complexity in identification is intrinsic since it is indispensable to identify the paired devices in the control of input and output devices in duplex configuration. On the other hand, according to this invention, use is made of the logic address assigned uniquely to each device, and there is no need for identifying two physical numbers (such as a unit number and a slot number) assigned to each device as in the related arts. Thus, laboriousness and complexity can be reduced. This feature and advantage of the present invention is provided in not only the first embodiment of the invention but also the other embodiments of the invention described hereafter.
[Embodiment 21 Figs. 7 - 9 are related to the second embodiment of the process control system according to this invention. Fig. 7 is a block diagram of the process control system according to the second embodiment of this invention. Fig. 8 is a block diagram showing the output devices in duplex configuration included in the process control system according to the second embodiment. Fig. 9 is a flow chart for the switchover operation taking place between output devices in duplex configuration according to the second embodiment.
This second embodiment differs from the first embodiment in that it lacks the interlock signal buses 106-1, 106-2 shown in Fig. 2. In the second embodiment, as shown in Fig. 8, the command judgment units 801a, 801b of output devices 103a, 103b directly drive the output switching units 204a, 204b for the setting of outputs. Therefore, the output devices 103a, 103b also lack the interlock devices 205a, 205b shown in Fig. 2. Except for these differences, the first and second embodiments of this invention are the same as each other.
As shown in Fig. 9, in the flow chart for the switchover operation taking place between output devices 103a, 103b, Steps 501 through 506 are the same as those shown in the flow chart in fig. 5 associated with the first embodiment. Steps 901 and 902 are different ones. In Step 901, if the comparison between the destination logic address 302 of the requirement command 301 and the self logic address of the output device 103 indicates that the logic addresses are the same as each other, the output switching unit 204 is directly driven to the "ON" state. If, on the contrary, the logic addresses are different from each other, the output switching unit 204 is directly driven to the "OFF" state in Step 902. Thus, these steps 901 and 902 enable the settings of the output ON/OFF in either of the output devices 103a, 103b. The switchover procedure performed on the side of the process control device 101 is the same as that shown in the flow chart in Fig. 4 associated with the first embodiment described above.
The switchover operation according to the second embodiment of this invention will now be described in detail. As seen in Fig. 7 showing the process control system according to the second invention of this invention, it is assumed that the output devices 103a-3, 103b-3 are in the duplex configuration, that the self logic address of the output device 103a-3 is "6" whereas the self logic address of the output device 103b-3 is "7", and that the output device 103a-3 is in the master state whereas the output device 103b-3 is in the standby state.
Let it be assumed that a failure occurred in the output device 103a-3. Then, the process control device 101 issues the switchover requirement command 301 to the self logic address of the output device which is to serve as master output device, as in the first embodiment. The destination logic address 302 of the issued requirement command 301 is "71' that is the same as the self logic address "7" of the output device 103b-3, and the requirement command data 303 of the issued requirement command 301 is "output ON". In response to the issued requirement command 301, the switchover operation is performed'for the output devices 103a-3, 103b-3 as shown in the flow chart in Fig. 9.
The switchover operations associated with the output devices 103a-3 and 103b-3 are described in this order mentioned. Steps 501 - 506 shown in Fig. 9 are the same as those steps denoted by the same reference numerals 501 -506 as shown in the first embodiment in Fig. 5. Concerning the output device 103a-3, comparison is made between the destination logic address 302, whose value is "7", of the requirement command 301 and the self logic address 105a-3, whose value is "6", fetched from the logic address holding unit 206a, in Step 504. The result of comparison is that the logic addresses are different from each other, so that Step 902 is reached. In Step 902, the output switching unit 204a is set to its "OFF" state.
The switchover operations associated with the output devices 103a-3 and 103b-3 are described in this order mentioned. Steps 501 - 506 shown in Fig. 9 are the same as those steps denoted by the same reference numerals 501 -506 as shown in the first embodiment in Fig. 5. Concerning the output device 103a-3, comparison is made between the destination logic address 302, whose value is "7", of the requirement command 301 and the self logic address 105a-3, whose value is "6", fetched from the logic address holding unit 206a, in Step 504. The result of comparison is that the logic addresses are different from each other, so that Step 902 is reached. In Step 902, the output switching unit 204a is set to its "OFF" state.
Next, concerning the output device 103b-3, comparison is made between the destination logic address 302, whose value is "7", of the requirement command 301 and the self logic address 105b-3, whose value is "711, fetched from the logic address holding unit 206b, in Step 504. The result of comparison is that the logic addresses are the same as each other, so that Step 901 is reached. In Step 901, the output switching unit 204b is set to its "ON" state. The ON/OFF operations of the output switching units 204a, 204b are performed simultaneously in response to the reception of the requirement command 301, and therefore the transition of the output device 103a-3 from its master state to the standby state occurs simultaneously with the transition of the output device 103b-3 from its standby state to the master state, as is seen in the state transition graphs in Fig. 6.
LEmbodiment 3]
Figs. 10 through 15 are related to the third embodiment of the process control system according to this invention. Fig. 10 shows a block diagram of the process control system according to the third embodiment of this invention. Fig. 11 shows in block diagram the output devices in multiplex configuration included in the process control system as the third embodiment. Fig. 12 schematically shows the format of a requirement command issued from the process control device included in the process control system as the third embodiment. Fig. 13 is a flow chart for the switchover operation taking place between output devices according to the third embodiment of this invention. Fig. 14 is a flowchart for the operation of the process control device issuing the switchover requirement command to the output devices in multiplex configuration according to the third embodiment of this invention. Fig. 15 shows graphs illustrating by state transitions the moment of switchover from one output device to another in multiplex configuration according to the third embodiment of this invention.
In the process control system as the third embodiment of this invention shown in Fig. 10, a physical or logic address 1003a, a group ID 1004a and an I/0 device mounting slot number 1005a are assigned to an output device 1002a mounted on an I/O device mounting unit 1001a; a physical or logic address 1003b, a group ID 1004b and an I/O device mounting slot number 1005b are assigned to an output device 1002b mounted on an I/O device mounting unit 1001b; and a physical or logic address 1003c, a group ID 1004c and an I/0 device mounting slot number 1005c are assigned to an output device 1002c mounted on an I/0 device mounting unit 1001c. The output devices 1002a, 1002b and 1002c are connected respectively with transmission/reception paths 104a, 104b and 104c for transmitting and receiving the switchover requirement command. The transmission/reception paths 104a, 104b are the same as those denoted by reference numerals 104a, 104b in the first and second embodiments of this invention. The process control device 101 and the output data transmission channel 107 are also the same as those used in the first and second embodiments described above. It should be noted here that if a group ID is assigned to a group of output devices, the address to be assigned to each output device can be either a physical address or a logic address in order to uniquely,identify the output device itself. The output device can be uniquely identified by the combination of the group ID and the physical or logic address.
In Fig. 11 are seen group ID holding units 1101a, 1101b and 1101c; and physical/logic address holding units 1103a, 1103b and 1103c, which are not found in the first and second embodiments. Also, in fig. 11, command judgment units 1102a, 1102b and 1102c perform judgment processes different from those performed by the command judgment units 202a, 202b used in the first and second embodiments. Further, the command reception units, the I/O output units, and the output switching units are the same as those used in the first and second embodiments. Fig. 12 shows the format of the requirement command 1201 issued by the process control device 101, the requirement command 1201 comprising a destination group ID 1202, a destination physical/logic address 1203, and requirement command data 1204.
LEmbodiment 3]
Figs. 10 through 15 are related to the third embodiment of the process control system according to this invention. Fig. 10 shows a block diagram of the process control system according to the third embodiment of this invention. Fig. 11 shows in block diagram the output devices in multiplex configuration included in the process control system as the third embodiment. Fig. 12 schematically shows the format of a requirement command issued from the process control device included in the process control system as the third embodiment. Fig. 13 is a flow chart for the switchover operation taking place between output devices according to the third embodiment of this invention. Fig. 14 is a flowchart for the operation of the process control device issuing the switchover requirement command to the output devices in multiplex configuration according to the third embodiment of this invention. Fig. 15 shows graphs illustrating by state transitions the moment of switchover from one output device to another in multiplex configuration according to the third embodiment of this invention.
In the process control system as the third embodiment of this invention shown in Fig. 10, a physical or logic address 1003a, a group ID 1004a and an I/0 device mounting slot number 1005a are assigned to an output device 1002a mounted on an I/O device mounting unit 1001a; a physical or logic address 1003b, a group ID 1004b and an I/O device mounting slot number 1005b are assigned to an output device 1002b mounted on an I/O device mounting unit 1001b; and a physical or logic address 1003c, a group ID 1004c and an I/0 device mounting slot number 1005c are assigned to an output device 1002c mounted on an I/0 device mounting unit 1001c. The output devices 1002a, 1002b and 1002c are connected respectively with transmission/reception paths 104a, 104b and 104c for transmitting and receiving the switchover requirement command. The transmission/reception paths 104a, 104b are the same as those denoted by reference numerals 104a, 104b in the first and second embodiments of this invention. The process control device 101 and the output data transmission channel 107 are also the same as those used in the first and second embodiments described above. It should be noted here that if a group ID is assigned to a group of output devices, the address to be assigned to each output device can be either a physical address or a logic address in order to uniquely,identify the output device itself. The output device can be uniquely identified by the combination of the group ID and the physical or logic address.
In Fig. 11 are seen group ID holding units 1101a, 1101b and 1101c; and physical/logic address holding units 1103a, 1103b and 1103c, which are not found in the first and second embodiments. Also, in fig. 11, command judgment units 1102a, 1102b and 1102c perform judgment processes different from those performed by the command judgment units 202a, 202b used in the first and second embodiments. Further, the command reception units, the I/O output units, and the output switching units are the same as those used in the first and second embodiments. Fig. 12 shows the format of the requirement command 1201 issued by the process control device 101, the requirement command 1201 comprising a destination group ID 1202, a destination physical/logic address 1203, and requirement command data 1204.
Fig. 13 is a flow chart for the operation of issuing a switchover requirement command when such a switchover requirement is raised through the manipulation on, for example, a human machine interface (HMI) screen in the system containing the output devices 1002a, 1002b and 1002c in triplex configuration in the process control device 101, or when the master side output device in the triplex configuration fails.
In Step 401, judgment is passed whether or not there is need for switching between the master and standby states among the output devices 1002a, 1002b and 1002c.
If there is such a need, the requirement command 1201 is issued, in Step 1301, to the group IDs of the output devices 1002a, 1002b and 1002c, one of which is to serve as the master output device.
Fig. 14 is a flowchart for the operation of switching over among the output devices 1002a, 1002b and 1002c according to the third embodiment of this invention. It is noted here that Steps 501, 503, 504, 506, 901 and 902 are the same as those steps used in the second embodiment shown in Fig. 9. Although, in the first and second embodiments, comparison is made, in Step 502, between the destination logic address 302 of the requirement command 301 with its LSB masked and the self logic address with its LSB masked, the destination group ID 1202 of the requirement command 1201 is compared with the self group ID fetched from the group ID holding units 1101a, 1101b, 1101c in Step 1401 in this third embodiment of the invention. Except for this difference in the comparison operation, the third embodiment is identical with the second embodiment.
Fig. 15 shows graphs illustrating by state transition the moment of switchover of the output devices 1002a, 1002b and 1002c between the master and standby states according to the third embodiment of this invention.
The switchover operation according to the third embodiment of this invention will now be described in detail. As seen in Fig. 10 showing the process control system according to the third embodiment of this invention, it is assumed that the output devices 1002a, 1002b, 1002c are in the triplex configuration, that the group IDs 1104a, 1104b, 114c of the output devices 1002a, 1002b, 1002c are all "3"
whereas the self logic addresses of the output devices 1002a, 1002b, 1002c are "6", "7", 1116", respectively, and that the output device 1002a is in the master state whereas the output devices 1002b, 1002c are in the standby state. It is noted that although either physical address or logic address may be equally used, logic address is chosen here.
Let it be assumed that a failure occurred in the output device 1002a. Then, the process control device 101 issues the switchover requirement command 1201 to the group ID of the output device which is to serve as master output device. The destination group ID of the issued requirement command 1201 is "3" that is the same as the group IDs assigned to the output devices 1002a, 1002b, 1002c, the destination logic address is "711, and the requirement command data of the issued requirement command is "output ON". The issued requirement command 1201 is received by the output devices 1002a, 1002b, 1002c, and the switchover operation is performed for the output devices 1002a, 1002b, 1002c as shown in the flow chart in Fig. 14.
The switchover operations associated with the output devices 1002a, 1002b, 1002c are now described in this order mentioned in reference to the flow chart shown in Fig. 14. Steps 501, 503, 504 and 506 shown in Fig. 14 are the same as those steps denoted by the same reference numerals 501, 503, 504 and 506 as shown in the second embodiment.
Concerning the output device 1002a, comparison is made, in Step 1401, between the destination group ID, whose value is "3", of the requirement command 1201 and the self group ID of the output device 1002a, whose ID value is "311, fetched from the group ID holding unit 1101a. Concerning the output device 1002b, comparison is made, in Step 1401, between the destination group ID, whose ID value is "3", of the requirement command 1201 and the self group ID of the output device 1002b, whose ID value is "3", fetched from the group ID holding unit 1101b. And concerning the output device 1002c, comparison is made, in Step 1401, between the destination group ID, whose ID value is "3", of the requirement command 1201 and the self group ID of the output device 1002c, whose ID
value is "3", fetched from the group ID holding unit 1101c. The comparisons indicate that the group IDs are all the same, so that Step 503 is reached for each of the output devices 1002a, 1002b, 1002c.
The remaining steps of the procedure are identical with those corresponding steps used in the second embodiment. The output device 1002b whose self logic address is deemed to be the same as the destination logic address of the requirement command 1201 in Step 504, is chosen to be a master output device. Accordingly, the output switching unit 204b of the output device 1002b is turned into the "ON" state whereas the output switching units 204a, 204c remain in the "OFF" state. The ON/OFF operations of the output switching units 204a, 204b, 204c, that is, the switchover operations of the output devices 1002a, 1002b, 1002c, are performed simultaneously in response to the reception of the requirement command 1201, and therefore the transitions of the output devices 1002a and 1002c to their standby states occur simultaneously with the transition of the output device 1002b from its standby state to the master state, as is seen in the state transition graphs in Fig. 15.
[Embodiment 4]
In Step 401, judgment is passed whether or not there is need for switching between the master and standby states among the output devices 1002a, 1002b and 1002c.
If there is such a need, the requirement command 1201 is issued, in Step 1301, to the group IDs of the output devices 1002a, 1002b and 1002c, one of which is to serve as the master output device.
Fig. 14 is a flowchart for the operation of switching over among the output devices 1002a, 1002b and 1002c according to the third embodiment of this invention. It is noted here that Steps 501, 503, 504, 506, 901 and 902 are the same as those steps used in the second embodiment shown in Fig. 9. Although, in the first and second embodiments, comparison is made, in Step 502, between the destination logic address 302 of the requirement command 301 with its LSB masked and the self logic address with its LSB masked, the destination group ID 1202 of the requirement command 1201 is compared with the self group ID fetched from the group ID holding units 1101a, 1101b, 1101c in Step 1401 in this third embodiment of the invention. Except for this difference in the comparison operation, the third embodiment is identical with the second embodiment.
Fig. 15 shows graphs illustrating by state transition the moment of switchover of the output devices 1002a, 1002b and 1002c between the master and standby states according to the third embodiment of this invention.
The switchover operation according to the third embodiment of this invention will now be described in detail. As seen in Fig. 10 showing the process control system according to the third embodiment of this invention, it is assumed that the output devices 1002a, 1002b, 1002c are in the triplex configuration, that the group IDs 1104a, 1104b, 114c of the output devices 1002a, 1002b, 1002c are all "3"
whereas the self logic addresses of the output devices 1002a, 1002b, 1002c are "6", "7", 1116", respectively, and that the output device 1002a is in the master state whereas the output devices 1002b, 1002c are in the standby state. It is noted that although either physical address or logic address may be equally used, logic address is chosen here.
Let it be assumed that a failure occurred in the output device 1002a. Then, the process control device 101 issues the switchover requirement command 1201 to the group ID of the output device which is to serve as master output device. The destination group ID of the issued requirement command 1201 is "3" that is the same as the group IDs assigned to the output devices 1002a, 1002b, 1002c, the destination logic address is "711, and the requirement command data of the issued requirement command is "output ON". The issued requirement command 1201 is received by the output devices 1002a, 1002b, 1002c, and the switchover operation is performed for the output devices 1002a, 1002b, 1002c as shown in the flow chart in Fig. 14.
The switchover operations associated with the output devices 1002a, 1002b, 1002c are now described in this order mentioned in reference to the flow chart shown in Fig. 14. Steps 501, 503, 504 and 506 shown in Fig. 14 are the same as those steps denoted by the same reference numerals 501, 503, 504 and 506 as shown in the second embodiment.
Concerning the output device 1002a, comparison is made, in Step 1401, between the destination group ID, whose value is "3", of the requirement command 1201 and the self group ID of the output device 1002a, whose ID value is "311, fetched from the group ID holding unit 1101a. Concerning the output device 1002b, comparison is made, in Step 1401, between the destination group ID, whose ID value is "3", of the requirement command 1201 and the self group ID of the output device 1002b, whose ID value is "3", fetched from the group ID holding unit 1101b. And concerning the output device 1002c, comparison is made, in Step 1401, between the destination group ID, whose ID value is "3", of the requirement command 1201 and the self group ID of the output device 1002c, whose ID
value is "3", fetched from the group ID holding unit 1101c. The comparisons indicate that the group IDs are all the same, so that Step 503 is reached for each of the output devices 1002a, 1002b, 1002c.
The remaining steps of the procedure are identical with those corresponding steps used in the second embodiment. The output device 1002b whose self logic address is deemed to be the same as the destination logic address of the requirement command 1201 in Step 504, is chosen to be a master output device. Accordingly, the output switching unit 204b of the output device 1002b is turned into the "ON" state whereas the output switching units 204a, 204c remain in the "OFF" state. The ON/OFF operations of the output switching units 204a, 204b, 204c, that is, the switchover operations of the output devices 1002a, 1002b, 1002c, are performed simultaneously in response to the reception of the requirement command 1201, and therefore the transitions of the output devices 1002a and 1002c to their standby states occur simultaneously with the transition of the output device 1002b from its standby state to the master state, as is seen in the state transition graphs in Fig. 15.
[Embodiment 4]
Figs. 16 through 20 are related to the fourth embodiment of the process control system according to this invention. Fig. 16 shows a block diagram of the process control system according to a fourth embodiment of this invention.
In this fourth embodiment, the process control system comprises a process control device 101;
I/O device mounting units 1601a, 1601b, 1601c; output devices 1602a, 1602b, 1602c mounted on the I/0 device mounting units 1601a, 1601b, 1601c and incorporating therein their own (i.e. self) group IDs 1401a, 1401b, 1401c, and I/O device mounting slot numbers 1005a, 1005b, 1005c; an output selection device 1603 for comparing the outputs of the output devices 1602a, 1602b, 1602c with one another, and delivering an output standing for the majority of the outputs of the output devices 1602a, 1602b, 1602c according to the majority rule; output data buses 1604a, 1604b, 1604c; an ultimate destination 1605 which the data selected by the output selection device 1603 finally reach; and transmission/reception paths 104a, 104b, 104c for transmitting/receiving the switchover requirement command. The above mentioned "output standing for the majority of the outputs of the output devices 1602a, 1602b, 1602c according to the majority rule" refers to the value which more than one output device 1602a, 1602b or 1602c delivers as output to the output selection device 1603.
In this fourth embodiment, the process control system comprises a process control device 101;
I/O device mounting units 1601a, 1601b, 1601c; output devices 1602a, 1602b, 1602c mounted on the I/0 device mounting units 1601a, 1601b, 1601c and incorporating therein their own (i.e. self) group IDs 1401a, 1401b, 1401c, and I/O device mounting slot numbers 1005a, 1005b, 1005c; an output selection device 1603 for comparing the outputs of the output devices 1602a, 1602b, 1602c with one another, and delivering an output standing for the majority of the outputs of the output devices 1602a, 1602b, 1602c according to the majority rule; output data buses 1604a, 1604b, 1604c; an ultimate destination 1605 which the data selected by the output selection device 1603 finally reach; and transmission/reception paths 104a, 104b, 104c for transmitting/receiving the switchover requirement command. The above mentioned "output standing for the majority of the outputs of the output devices 1602a, 1602b, 1602c according to the majority rule" refers to the value which more than one output device 1602a, 1602b or 1602c delivers as output to the output selection device 1603.
In Fig. 16, the self group IDs 1401a, 1401b, 1401c; the I/O device mounting slot numbers 1005a, 1005b, 1005c; and the transmission/reception paths 104a, 104b, 104c are the same as those items having like names as shown in the third embodiment. The process control device 101 shown in Fig. 16 is also the same as the process control device 101 used in the first through third embodiments of the invention.
Fig. 17 shows a block diagram showing the configuration of the output devices 1602a, 1602b or 1602c according to the fourth embodiment of this invention. In this fourth embodiment shown in Fig. 17, the group ID holding units 1101a,1101b, 11o1c are identical with the corresponding items denoted by like reference numerals showing the third embodiment whereas the command judgment units 1102a, 1102b, 1102c perform judgment processes different from those performed by the corresponding units of the third embodiment.
Further, the command reception units 201a, 201b, 201c, and the I/O output units 203a, 203b, 203c shown in this fourth embodiment in Fig. 17 are identical with the corresponding units used in the first through third embodiments.
Fig. 18 schematically shows the format of an output requirement command 1801 issued from the process control device 101, and the requirement command 1801, consists of a destination group ID 1802 and an output data value 1803.
Fig. 17 shows a block diagram showing the configuration of the output devices 1602a, 1602b or 1602c according to the fourth embodiment of this invention. In this fourth embodiment shown in Fig. 17, the group ID holding units 1101a,1101b, 11o1c are identical with the corresponding items denoted by like reference numerals showing the third embodiment whereas the command judgment units 1102a, 1102b, 1102c perform judgment processes different from those performed by the corresponding units of the third embodiment.
Further, the command reception units 201a, 201b, 201c, and the I/O output units 203a, 203b, 203c shown in this fourth embodiment in Fig. 17 are identical with the corresponding units used in the first through third embodiments.
Fig. 18 schematically shows the format of an output requirement command 1801 issued from the process control device 101, and the requirement command 1801, consists of a destination group ID 1802 and an output data value 1803.
Fig. 19 is a flowchart for the operation of switching over among the output devices 1602a, 1602b, 1602c according to the fourth embodiment of this invention. In Step 1901, the command reception units 201a, 201b, 201c receive the output requirement command 1801 issued from the process control device 101. In Step 1902, comparison is made between the destination group ID 1802 of the output requirement command 1801 received in Step 1901 and each of the self group IDs fetched from the group ID holding units 1101a, ilOlb, ilOlc. If the compared IDs are the same as each other, Step 1903 is reached. If, on the other hand, the compared IDs are different from each other, the flow comes to an end without doing anything at all. In Step 1903, output demands to cause the I/O output units 203a, 203b, 203c to deliver the output data value 1803 are issued to the I/0 output units 203a, 203b, 203c.
Fig. 20 graphically shows the operations of the output devices 1602a, 1602b, 1602c generating output demands when the process control device 101 issues a requirement command.
The switchover operation according to the fourth embodiment of this invention will now be described in detail. As seen in Fig. 16 showing the process control system according to the fourth embodiment of this invention, it is assumed that the output devices 1602a, 1602b, 1602c are in the triplex configuration, and that the group IDs 1401a, 1401b, 1401c of the output devices 1602a, 1602b, 1602c are all 1"3". Now, the process control device 101 issues the output requirement command to the group ID of the output device which is to deliver an output. The issued output requirement command 1801 has a value "13"
for its destination group ID 1802, the value being the same as that assigned as the self group IDs to the output devices 1602a, 1602b, 1602c, and a value "5" for its output data value 1803.
The issued output requirement command 1801 is received by the output devices 1602a, 1602b, 1602c, and the output delivering operation is performed with the output devices as shown in the flow chart in Fig. 19.
The output delivering operation associated with the output device 1602a is described here by way of example in reference to the flow chart shown in Fig. 19.
Concerning the output device 1602a, comparison is made, in Step 1901, between the destination group ID, whose ID value is "31", of the output requirement command 1801 and the self group ID, whose ID value is "3", fetched from the group ID holding unit 1101a of the output device 1602a. Since the compared ID values are the same as each other, Step 1903 is reached.
In Step 1903, the output device 1602a demands the I/0 output unit 203a to deliver the output data value "5" of the output requirement command 1801. The output devices 1602b, 1602c operates in the same way as the output device 1602a. The output data values from the output devices 1602a, 1602b, 1602c are compared in the output selection device 1603. Let it now be assumed that for some cause, the output data value from the output device 1602c as shown in Fig. 20 is "3" that is different from the required data value "5". (Refer to values on vertical axis with regard to the output device 1602c.) In this case, the output selectiori device 1603 delivers an output "5" according to the logic of the majority rule since the outputs of the output devices 1602a, 1602b are both "5" though the output of the output device 1602a is "3". In this way, according to this embodiment, a single output requirement can simultaneously change the data values from the output devices 1602a, 1602b, 1602c in triplex configuration, and also the adopted logic of the majority rule can help improve the reliability of operation.
As described above, in the related arts, the input devices or output devices in duplex configuration are mounted in the adjacent slots in an I/O device mounting unit, and the input-output devices in the duplex configuration are accessed by using physical addresses provided with the unit numbers and the slot numbers. Namely, a certain restriction on the transmission of the interlock signals necessitated the structure of the related art wherein the input-output devices in the duplex configuration must be mounted on the adjacent slots of a mounting unit, and therefore when a failure occurs involving a unit as a whole, the input-output devices in the duplex configuration mounted in the failed unit turn inoperable all together. According to this invention, on the contrary, the input-output devices in multiplex configuration are provided with logic addresses, instead of the physical addresses of the related art, consisting of arbitrary numbers or codes unique to the input-output devices. This constitution aims to eliminate the physical restriction of providing both units and slots within each unit, to improve the degree of freedom in multiplexing, and to improve the resistance to the failure involving a mounting unit itself.
It should be further understood by those skilled in the art that although the foregoing description has been made on embodiments of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.
Fig. 20 graphically shows the operations of the output devices 1602a, 1602b, 1602c generating output demands when the process control device 101 issues a requirement command.
The switchover operation according to the fourth embodiment of this invention will now be described in detail. As seen in Fig. 16 showing the process control system according to the fourth embodiment of this invention, it is assumed that the output devices 1602a, 1602b, 1602c are in the triplex configuration, and that the group IDs 1401a, 1401b, 1401c of the output devices 1602a, 1602b, 1602c are all 1"3". Now, the process control device 101 issues the output requirement command to the group ID of the output device which is to deliver an output. The issued output requirement command 1801 has a value "13"
for its destination group ID 1802, the value being the same as that assigned as the self group IDs to the output devices 1602a, 1602b, 1602c, and a value "5" for its output data value 1803.
The issued output requirement command 1801 is received by the output devices 1602a, 1602b, 1602c, and the output delivering operation is performed with the output devices as shown in the flow chart in Fig. 19.
The output delivering operation associated with the output device 1602a is described here by way of example in reference to the flow chart shown in Fig. 19.
Concerning the output device 1602a, comparison is made, in Step 1901, between the destination group ID, whose ID value is "31", of the output requirement command 1801 and the self group ID, whose ID value is "3", fetched from the group ID holding unit 1101a of the output device 1602a. Since the compared ID values are the same as each other, Step 1903 is reached.
In Step 1903, the output device 1602a demands the I/0 output unit 203a to deliver the output data value "5" of the output requirement command 1801. The output devices 1602b, 1602c operates in the same way as the output device 1602a. The output data values from the output devices 1602a, 1602b, 1602c are compared in the output selection device 1603. Let it now be assumed that for some cause, the output data value from the output device 1602c as shown in Fig. 20 is "3" that is different from the required data value "5". (Refer to values on vertical axis with regard to the output device 1602c.) In this case, the output selectiori device 1603 delivers an output "5" according to the logic of the majority rule since the outputs of the output devices 1602a, 1602b are both "5" though the output of the output device 1602a is "3". In this way, according to this embodiment, a single output requirement can simultaneously change the data values from the output devices 1602a, 1602b, 1602c in triplex configuration, and also the adopted logic of the majority rule can help improve the reliability of operation.
As described above, in the related arts, the input devices or output devices in duplex configuration are mounted in the adjacent slots in an I/O device mounting unit, and the input-output devices in the duplex configuration are accessed by using physical addresses provided with the unit numbers and the slot numbers. Namely, a certain restriction on the transmission of the interlock signals necessitated the structure of the related art wherein the input-output devices in the duplex configuration must be mounted on the adjacent slots of a mounting unit, and therefore when a failure occurs involving a unit as a whole, the input-output devices in the duplex configuration mounted in the failed unit turn inoperable all together. According to this invention, on the contrary, the input-output devices in multiplex configuration are provided with logic addresses, instead of the physical addresses of the related art, consisting of arbitrary numbers or codes unique to the input-output devices. This constitution aims to eliminate the physical restriction of providing both units and slots within each unit, to improve the degree of freedom in multiplexing, and to improve the resistance to the failure involving a mounting unit itself.
It should be further understood by those skilled in the art that although the foregoing description has been made on embodiments of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.
Claims (5)
1. A process control system, comprising:
a process control device for issuing a requirement command to which a logical address, of logical addresses, for indicating a destination is added; and a plurality of multiplexed output devices each of which receives the requirement command and executes a process based on the requirement command;
wherein the logical addresses having a same part thereof is respectively set to the plurality of multiplexed output devices, and wherein each one of the plurality of multiplexed output devices compares the same part of the logical addresses set to the one of the plurality of multiplexed devices performing the comparing with a part of a further logical address which is added to the receive requirement command, if the same part is equal to the part of the further logical address, the requirement command is identified and said logical address is compared with the further logical address added to the requirement command based on a result of the identification, if said logical address is equal to the further logical address added to the requirement command, the process based on the requirement command is executed.
a process control device for issuing a requirement command to which a logical address, of logical addresses, for indicating a destination is added; and a plurality of multiplexed output devices each of which receives the requirement command and executes a process based on the requirement command;
wherein the logical addresses having a same part thereof is respectively set to the plurality of multiplexed output devices, and wherein each one of the plurality of multiplexed output devices compares the same part of the logical addresses set to the one of the plurality of multiplexed devices performing the comparing with a part of a further logical address which is added to the receive requirement command, if the same part is equal to the part of the further logical address, the requirement command is identified and said logical address is compared with the further logical address added to the requirement command based on a result of the identification, if said logical address is equal to the further logical address added to the requirement command, the process based on the requirement command is executed.
2. The process control system of Claim 1, wherein consecutive logical addresses are assigned each to the plurality of multiplexed output devices.
3. A process control system comprising:
a process control device for issuing a requirement command to which an address and a group ID for indicating a destination are added; and a plurality of multiplexed output devices, each of which receives the requirement command and executes a process based on the requirement command, wherein each of the plurality of output devices has a same group ID and a different address, wherein each one of the plurality of multiplexed output devices compare the group ID set to the one of the plurality of multiplexed output devices with a further group ID to which the received requirement command is added, if said group ID is equal to the further group ID to which the command is added, the requirement command is identified and said address to the one of the plurality of multiplexed output devices is compared with a further address to which the requirement command is added based on a result of the identification, if said address is equal to the further address, the process based on the requirement command is performed.
a process control device for issuing a requirement command to which an address and a group ID for indicating a destination are added; and a plurality of multiplexed output devices, each of which receives the requirement command and executes a process based on the requirement command, wherein each of the plurality of output devices has a same group ID and a different address, wherein each one of the plurality of multiplexed output devices compare the group ID set to the one of the plurality of multiplexed output devices with a further group ID to which the received requirement command is added, if said group ID is equal to the further group ID to which the command is added, the requirement command is identified and said address to the one of the plurality of multiplexed output devices is compared with a further address to which the requirement command is added based on a result of the identification, if said address is equal to the further address, the process based on the requirement command is performed.
4. A process control method, comprising:
providing each of a plurality of multiplexed output devices with a logical address, each of the logical address having a same part thereof;
comparing the same part of the logical addresses at each of the plurality of multiplexed output devices with a part of a further logical address which is added to the received requirement command;
if the same part is equal to the part of the further logical address, identifying the requirement command and comparing the logical address with the further logical address added to the requirement command based on a result of the identifying; and if said logical address is equal to the further logical address added to the requirement command, executing the process based on the requirement command.
providing each of a plurality of multiplexed output devices with a logical address, each of the logical address having a same part thereof;
comparing the same part of the logical addresses at each of the plurality of multiplexed output devices with a part of a further logical address which is added to the received requirement command;
if the same part is equal to the part of the further logical address, identifying the requirement command and comparing the logical address with the further logical address added to the requirement command based on a result of the identifying; and if said logical address is equal to the further logical address added to the requirement command, executing the process based on the requirement command.
5. A process control method, comprising:
providing each of a plurality of multiplexed output devices with a group ID which identifies a group of the plurality of multiplexed output devices, which is the same for each of the plurality of multiplexed output devices, and with a logical address corresponding to one of a unique number, code and a physical address representing a combination of a slot and a unit into which the multiplexed output device is mounted, wherein the logical address is different for each of the plurality of multiplexed output devices;
comparing the group ID at each one of the plurality of output devices with a further group ID to which the requirement command is added;
if the group ID is equal to the further group ID to which the requirement command is added, identifying the requirement command and comparing the address at the one of the plurality of multiplexed output devices with a further address to which the requirement command is added based on a result of the identifying; and if the address is equal to the further address, executing the process based on the requirement command.
providing each of a plurality of multiplexed output devices with a group ID which identifies a group of the plurality of multiplexed output devices, which is the same for each of the plurality of multiplexed output devices, and with a logical address corresponding to one of a unique number, code and a physical address representing a combination of a slot and a unit into which the multiplexed output device is mounted, wherein the logical address is different for each of the plurality of multiplexed output devices;
comparing the group ID at each one of the plurality of output devices with a further group ID to which the requirement command is added;
if the group ID is equal to the further group ID to which the requirement command is added, identifying the requirement command and comparing the address at the one of the plurality of multiplexed output devices with a further address to which the requirement command is added based on a result of the identifying; and if the address is equal to the further address, executing the process based on the requirement command.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007114271A JP4701203B2 (en) | 2007-04-24 | 2007-04-24 | Process control system |
| JP2007-114271 | 2007-04-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2629796A1 CA2629796A1 (en) | 2008-10-24 |
| CA2629796C true CA2629796C (en) | 2012-05-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2629796A Active CA2629796C (en) | 2007-04-24 | 2008-04-22 | Process control system and method with multiplexed input-output device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP4701203B2 (en) |
| CA (1) | CA2629796C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5537447B2 (en) * | 2011-01-19 | 2014-07-02 | 株式会社日立製作所 | Multiplexing control system, multiplexing control method, and multiplexing control program |
| JP6714981B2 (en) * | 2015-07-14 | 2020-07-01 | 株式会社東芝 | Multiplex controller |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59112325A (en) * | 1982-12-20 | 1984-06-28 | Hitachi Ltd | Electronic computer system |
| JP2539403B2 (en) * | 1986-12-26 | 1996-10-02 | 株式会社日立製作所 | Process control equipment |
| JPH0291703A (en) * | 1988-09-29 | 1990-03-30 | Toshiba Corp | Multiplex transmission method for programmable controller |
| JP4265252B2 (en) * | 2003-03-26 | 2009-05-20 | パナソニック電工株式会社 | Remote monitoring and control system |
-
2007
- 2007-04-24 JP JP2007114271A patent/JP4701203B2/en not_active Expired - Fee Related
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2008
- 2008-04-22 CA CA2629796A patent/CA2629796C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CA2629796A1 (en) | 2008-10-24 |
| JP4701203B2 (en) | 2011-06-15 |
| JP2008269468A (en) | 2008-11-06 |
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