CA2582243A1 - Low noise hybrid active-passive pixel for different sensor applications - Google Patents

Abstract

Disclosed is a technique for reducing the noise in active matrix sensor pixel circuits and to improve the lifetime at the same time.

Description

FIELD OF THE INVENTION

The present invention generally relates to active matrix sensor arrays for applications ranging from medical to bio-molecular imaging.

SUMMARY OF INVENTION
Disclosed technique reduces the low frequency noise by using switch biasing technique.
It is also able to control the effect of leakage current by reducing the drain-source voltage to zero.

ADVANTAGES
This driving scheme provides low noise, high sensitivity, and low power detection.

FIG. 1 shows a 3-TFT sensor pixel circuit. The pixel circuit composes a two amplifying transistors, Tl and T2, a switch transistor, T3, a storage capacitor, Cs, and a sensor, SI.
The transistor can be fabricated in any technology including CMOS, NMOS, amorphous silicon, nano/micro crystalline silicon, poly crystalline, and liquid-printed and vacuum deposited organic technology. Moreover, the NMOS transistors can be replaced with a PMOS transistor using the concept of complementary circuit design.

The operating cycles of the pixel circuit depicted in FIG. 1 are demonstrated in FIG. 2.
During the first operating cycle, the storage capacitor is charged to a biasing voltage (VP). During the second cycle, the sensor signal is integrated by the storage capacitor.
During the readout cycle, Tl and T2 turn on sequentially. Thus, the output signal is not affected by the sync filter induced by switched biasing and it is essentially equivalent to a single TFT with a DC bias. However, one can use one TFT (Tl or T2) to improve the aperture ratio and use a higher bias voltage to compensate for the gain lost by the switch biasing technique. On the other hand, the noise is reduced significantly due to the reduction of carrier trapping/de-trapping phenomena intrinsic to most transistors.
Moreover, the lifetime of the pixel is improved as well.

The pixel can work in hybrid mode which means it can be passive or active. For passive operation, VB1 and VB2 are chosen to be the voltage applied to Idata and so they are OFF. Therefore, the integrated signal can be read back through Vdata.

FIG. 3 shows a 3-TFT sensor pixel circuit. The pixel circuit composes of two amplifying transistors, T2 and T2, a switch transistor, T3, a storage capacitor, Cs, and a sensor, Sl.
The transistor can be fabricated in any technology including CMOS, NMOS, amorphous silicon, nano/micro crystalline silicon, poly crystalline, and liquid-printed and vacuum-deposited organic technology. Moreover, the NMOS transistors can be replaced with a PMOS transistor using the concept of complementary circuit design.

The operating cycles of the pixel circuit depicted in FIG. 3 are demonstrated in FIG. 4.
During the first operating cycle, the storage capacitor is charged to a biasing voltage (VP) by applying a voltage or current to the data [iJ. When using cunent as the biasing signal, VBl and VB2 should be zero during the first operating cycle while for voltage biasing, they can be as the voltage of data[iJ to reduce power consumption. During the second cycle, the sensor signal is integrated by the storage capacitor. During the readout cycle, Tl and T2 turn on sequentially. Thus, the output signal is not affected by the sync filter induced by the switched biasing and it is essentially equivalent to a single TFT with a DC
bias. However, one can use one TFT (Tl or T2) to improve the aperture ratio and use a higher bias voltage to compensate for the gain lost by switch biasing technique. On the other hand, the noise is reduced significantly due to the reduction of carrier trapping/de-trapping phenomena intrinsic to most transistors. Moreover, the lifetime of the pixel is improved as well.

The pixel can work in hybrid mode which means it can be passive or active. For passive operation, VBl and VB2 are chosen to be the voltage applied to data [i] and so they are OFF. Therefore, the integrated signal can be read back through data [i].

FIG. 5 shows a 2-TFT sensor pixel circuit based on photo TFTs. The pixel circuit composes a two amplifying photo transistors, Tl and T2. The transistor can be fabricated in any technology including CMOS, NMOS, amorphous silicon, nano/micro crystalline silicon, poly crystalline, and liquid-printed and vacuum-deposited organic technology.
Moreover, the NMOS transistors can be replaced with a PMOS transistor using the concept of complementary circuit design.

The operating cycles of the pixel circuit depicted in FIG. 5 are demonstrated in FIG. 6.
During the first integration cycle, TI and T2 turn on sequentially while their channel conductance is modulated as a result of optical interaction. Thus, the output signal is not affected by the sync filter induced by switched biasing and it is essentially equivalent to a single TFT with a DC bias. However, one can use one TFT (Tl or T2) to improve the aperture ratio and use a higher bias voltage to compensate for the gain lost by the switch biasing technique. On the other hand, the noise is reduced significantly due to the reduction of carrier trapping/de-trapping phenomena intrinsic to most transistors.
Moreover, the lifetime of the pixel is improved as well.

Claims