CA2536259A1 - Methods and apparatus for encoding ldpc codes - Google Patents
Methods and apparatus for encoding ldpc codes Download PDFInfo
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- CA2536259A1 CA2536259A1 CA002536259A CA2536259A CA2536259A1 CA 2536259 A1 CA2536259 A1 CA 2536259A1 CA 002536259 A CA002536259 A CA 002536259A CA 2536259 A CA2536259 A CA 2536259A CA 2536259 A1 CA2536259 A1 CA 2536259A1
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- vector
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1182—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the structure of the parity-check matrix is obtained by reordering of a random parity-check matrix
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
Abstract
Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph.
Claims (26)
1. An apparatus for performing encoding operations, the apparatus comprising:
memory including a set of memory locations for storing L sets of Z-bit vectors, where Z is a positive integer greater than one and L is a positive integer;
a vector unit operation processor including an accumulator and output device for passing computed Z-bit vector to the said memory in response to operation instructions; and a switching device coupled to the memory and to the vector unit operation processor, the switching device for passing a Z-bit vector between said memory and said vector unit operation processor in response to switch control information.
memory including a set of memory locations for storing L sets of Z-bit vectors, where Z is a positive integer greater than one and L is a positive integer;
a vector unit operation processor including an accumulator and output device for passing computed Z-bit vector to the said memory in response to operation instructions; and a switching device coupled to the memory and to the vector unit operation processor, the switching device for passing a Z-bit vector between said memory and said vector unit operation processor in response to switch control information.
2. The apparatus of claim 1, further comprising:
an ordering control module coupled to said memory for generating read and write indices; and an operation control module coupled to said vector unit operation processor for generating unit operation instructions.
an ordering control module coupled to said memory for generating read and write indices; and an operation control module coupled to said vector unit operation processor for generating unit operation instructions.
3. The apparatus of claim 2, wherein the ordering control module is further coupled to said switch device for generating said switch control information used to control the switching of said at least one vector.
4. The apparatus of claim 1, wherein the switching device includes circuitry for performing a vector rotation operation to generate a rotated vector.
5. The apparatus of claim 2, wherein the ordering control module stores information on the order of vectors are to be read out of the memory and information on the order of vectors are to be written into the memory.
6. The apparatus of claim 2, wherein the ordering control module further stores information on the rotation to be performed on the read-out vectors from said memory by said switch.
7. The apparatus of claim 2, wherein the ordering control module sequentially generates index identifiers, each identifier controlling the memory to access memory locations corresponding to a vector as part of a single SIMD instruction.
8. The apparatus of claim 7, wherein each identifier is a single memory address.
9. The apparatus of claim 2, wherein said operation control module stores operation instructions, each instruction controlling the operation at said vector unit operation processor.
10. The apparatus of claim 9, wherein the operation control module sequentially generates operation instructions, each instruction controlling said vector unit operation processor to perform instructed operations.
11. The apparatus of claim 2, further comprising an encoder control module coupled to said ordering control module, the encoder control module including means for supplying information to said ordering control module used to control the order in which each of the L vectors is to be read out of said memory, their associated rotations, and the order to be written into said memory.
12. The apparatus of claim 11, wherein the encoder control device is further coupled to said operation control module, the encoder control device including means for supplying information to said operation control module used to generate operation instructions.
13. A method of performing encoding operations, the method comprising:
storing L sets of Z-bit vectors in a memory device, where z is a positive integer greater than one and L is a positive integer;
reading one of said sets of Z bit vectors from said stored L sets of Z bit vectors;
rotating the bits in said read one of said z bit vectors; and operating a vector unit processor to perform a plurality of combining operations to combine the bits of the rotated Z bit vector with a Z-bit vector stored in said vector unit processor to generate a new Z-bit vector.
storing L sets of Z-bit vectors in a memory device, where z is a positive integer greater than one and L is a positive integer;
reading one of said sets of Z bit vectors from said stored L sets of Z bit vectors;
rotating the bits in said read one of said z bit vectors; and operating a vector unit processor to perform a plurality of combining operations to combine the bits of the rotated Z bit vector with a Z-bit vector stored in said vector unit processor to generate a new Z-bit vector.
14. The method of claim 13, further comprising:
storing said new Z bit vector in said memory device in the place of one of the stored L sets of Z bit vectors.
storing said new Z bit vector in said memory device in the place of one of the stored L sets of Z bit vectors.
15. The method of claim 14, wherein said combining operations performed by said vector unit processor are exclusive OR
operations.
operations.
16. The method of claim 15 wherein said encoding method is a low density parity check encoding method.
17. The method of claim 14, further comprising:
executing a set of stored machine executable instructions to control the rotation of the read Z bit vector.
executing a set of stored machine executable instructions to control the rotation of the read Z bit vector.
18. The method of claim 14, further comprising:
using the executed set of stored machine executable instructions to determine which one of said sets of stored Z bit vectors is to be read from memory.
using the executed set of stored machine executable instructions to determine which one of said sets of stored Z bit vectors is to be read from memory.
19. The method of claim 14, further comprising:
using the executed set of stored machine executable instructions to determine when one of said sets of stored Z bit vectors is to be read from memory.
using the executed set of stored machine executable instructions to determine when one of said sets of stored Z bit vectors is to be read from memory.
20. The method of claim 19, further comprising:
using the executed set of stored machine executable instructions to determine which one of the stored L sets of Z
bit vectors is to be replaced by storing the new Z bit vector in said memory device.
using the executed set of stored machine executable instructions to determine which one of the stored L sets of Z
bit vectors is to be replaced by storing the new Z bit vector in said memory device.
21. The method of claim 19, further comprising:
resetting the Z bit vector stored in said vector unit processor at the same time said new Z bit vector is stored.
resetting the Z bit vector stored in said vector unit processor at the same time said new Z bit vector is stored.
22. The method of claim 14, further comprising:
resetting the Z bit vector stored in said vector unit processor at the same time said new Z bit vector is stored.
resetting the Z bit vector stored in said vector unit processor at the same time said new Z bit vector is stored.
23. The method of claim 14, further comprising:
using the executed set of stored machine executable instructions to determine which one of the stored L sets of Z
bit vectors is to be replaced by storing the new Z bit vector in said memory device.
using the executed set of stored machine executable instructions to determine which one of the stored L sets of Z
bit vectors is to be replaced by storing the new Z bit vector in said memory device.
24. ~A method of performing encoding operations, the method comprising:
storing L sets of Z-bit vectors in a memory device, where Z is a positive integer greater than one and L is a positive integer;
reading one of said sets of Z bit vectors from said stored L sets of Z bit vectors;
operating a vector unit processor to perform a plurality of combining operations to combine the bits of the rotated Z bit vector with a Z-bit vector stored in said vector unit processor to generate a new Z-bit vector;
rotating the bits in said new Z bit vector; and storing said rotated new Z bit vector in said memory device in the place of one of the stored L sets of Z bit vectors.
storing L sets of Z-bit vectors in a memory device, where Z is a positive integer greater than one and L is a positive integer;
reading one of said sets of Z bit vectors from said stored L sets of Z bit vectors;
operating a vector unit processor to perform a plurality of combining operations to combine the bits of the rotated Z bit vector with a Z-bit vector stored in said vector unit processor to generate a new Z-bit vector;
rotating the bits in said new Z bit vector; and storing said rotated new Z bit vector in said memory device in the place of one of the stored L sets of Z bit vectors.
25. ~The method of claim 24, wherein said combining operations performed by said vector unit processor are exclusive OR operations; and wherein said encoding method is a low density parity check encoding method.
26. ~The method of claim 25, further comprising:~
executing a set of stored machine executable instructions to control the rotation of the read Z bit vector and to determine which one of the stored L sets of Z bit vectors is to be replaced by storing said rotated new Z bit vector in said memory device.
executing a set of stored machine executable instructions to control the rotation of the read Z bit vector and to determine which one of the stored L sets of Z bit vectors is to be replaced by storing said rotated new Z bit vector in said memory device.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US40481002P | 2002-08-20 | 2002-08-20 | |
| US60/404,810 | 2002-08-20 | ||
| PCT/US2002/040573 WO2004019268A1 (en) | 2002-08-20 | 2002-12-18 | Methods and apparatus for encoding ldpc codes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2536259A1 true CA2536259A1 (en) | 2004-03-04 |
| CA2536259C CA2536259C (en) | 2011-05-24 |
Family
ID=31946766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2536259A Expired - Lifetime CA2536259C (en) | 2002-08-20 | 2002-12-18 | Methods and apparatus for encoding ldpc codes |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU2002364182A1 (en) |
| CA (1) | CA2536259C (en) |
| WO (1) | WO2004019268A1 (en) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7577207B2 (en) | 2002-07-03 | 2009-08-18 | Dtvg Licensing, Inc. | Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes |
| US7020829B2 (en) | 2002-07-03 | 2006-03-28 | Hughes Electronics Corporation | Method and system for decoding low density parity check (LDPC) codes |
| EP1525664B9 (en) | 2002-07-03 | 2015-09-02 | Dtvg Licensing, Inc | Method and system for memory management in low density parity check (ldpc) decoders |
| US20040019845A1 (en) | 2002-07-26 | 2004-01-29 | Hughes Electronics | Method and system for generating low density parity check codes |
| US7864869B2 (en) | 2002-07-26 | 2011-01-04 | Dtvg Licensing, Inc. | Satellite communication system utilizing low density parity check codes |
| CN1947368B (en) | 2004-04-28 | 2010-06-16 | 三星电子株式会社 | Apparatus and method for coding/decoding block low density parity check code with variable block length |
| KR20050118056A (en) | 2004-05-12 | 2005-12-15 | 삼성전자주식회사 | Method and apparatus for channel encoding and decoding in mobile communication systems using multi-rate block ldpc codes |
| US7581157B2 (en) | 2004-06-24 | 2009-08-25 | Lg Electronics Inc. | Method and apparatus of encoding and decoding data using low density parity check code in a wireless communication system |
| US7346832B2 (en) * | 2004-07-21 | 2008-03-18 | Qualcomm Incorporated | LDPC encoding methods and apparatus |
| US7143333B2 (en) * | 2004-08-09 | 2006-11-28 | Motorola, Inc. | Method and apparatus for encoding and decoding data |
| US7188297B2 (en) * | 2004-08-12 | 2007-03-06 | Motorola, Inc. | Method and apparatus for encoding and decoding data |
| WO2006020460A2 (en) * | 2004-08-13 | 2006-02-23 | The Directv Group, Inc. | Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels |
| CN101341659B (en) | 2004-08-13 | 2012-12-12 | Dtvg许可公司 | Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels |
| KR101065693B1 (en) * | 2004-09-17 | 2011-09-19 | 엘지전자 주식회사 | Method of encoding or decoding using LDPC code and method of generating LDPC code |
| JP4820368B2 (en) * | 2004-09-17 | 2011-11-24 | エルジー エレクトロニクス インコーポレイティド | Encoding and decoding method using LDPC code |
| WO2006031062A2 (en) | 2004-09-17 | 2006-03-23 | Lg Electronics Inc. | Method of encoding and decoding using ldpc code and apparatus thereof |
| CN100583651C (en) | 2004-12-22 | 2010-01-20 | Lg电子株式会社 | Apparatus and method for decoding using channel code |
| JP4617985B2 (en) | 2005-04-25 | 2011-01-26 | ソニー株式会社 | Encoding apparatus and encoding method |
| US20070198905A1 (en) * | 2006-02-03 | 2007-08-23 | Nokia Corporation | Transmitter for a communications network |
| CN101796488A (en) | 2007-07-02 | 2010-08-04 | 技术源于创意有限公司 | Generation of parity-check matrices |
| US8612823B2 (en) | 2008-10-17 | 2013-12-17 | Intel Corporation | Encoding of LDPC codes using sub-matrices of a low density parity check matrix |
| US8516351B2 (en) | 2009-07-21 | 2013-08-20 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
| US8516352B2 (en) | 2009-07-21 | 2013-08-20 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
| US8375278B2 (en) | 2009-07-21 | 2013-02-12 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured block codes |
| US9397699B2 (en) | 2009-07-21 | 2016-07-19 | Ramot At Tel Aviv University Ltd. | Compact decoding of punctured codes |
| US8683296B2 (en) | 2011-12-30 | 2014-03-25 | Streamscale, Inc. | Accelerated erasure coding system and method |
| US8914706B2 (en) | 2011-12-30 | 2014-12-16 | Streamscale, Inc. | Using parity data for concurrent data authentication, correction, compression, and encryption |
| US9203434B1 (en) | 2012-03-09 | 2015-12-01 | Western Digital Technologies, Inc. | Systems and methods for improved encoding of data in data storage devices |
| CN104488196B (en) * | 2012-11-05 | 2017-08-01 | 三菱电机株式会社 | Error correction/encoding method and encoder for correcting |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438180B1 (en) * | 1997-05-09 | 2002-08-20 | Carnegie Mellon University | Soft and hard sequence detection in ISI memory channels |
| US6081909A (en) * | 1997-11-06 | 2000-06-27 | Digital Equipment Corporation | Irregularly graphed encoding technique |
| US6195777B1 (en) * | 1997-11-06 | 2001-02-27 | Compaq Computer Corporation | Loss resilient code with double heavy tailed series of redundant layers |
| US6081918A (en) * | 1997-11-06 | 2000-06-27 | Spielman; Daniel A. | Loss resilient code with cascading series of redundant layers |
| US6073250A (en) * | 1997-11-06 | 2000-06-06 | Luby; Michael G. | Loss resilient decoding technique |
| US6163870A (en) * | 1997-11-06 | 2000-12-19 | Compaq Computer Corporation | Message encoding with irregular graphing |
-
2002
- 2002-12-18 WO PCT/US2002/040573 patent/WO2004019268A1/en not_active Application Discontinuation
- 2002-12-18 AU AU2002364182A patent/AU2002364182A1/en not_active Abandoned
- 2002-12-18 CA CA2536259A patent/CA2536259C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| AU2002364182A1 (en) | 2004-03-11 |
| WO2004019268A1 (en) | 2004-03-04 |
| CA2536259C (en) | 2011-05-24 |
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| Date | Code | Title | Description |
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| EEER | Examination request | ||
| MKEX | Expiry |
Effective date: 20221219 |