CA2517641A1 - A bpsk demodulator circuit using an anti-parallel synchronization loop - Google Patents

Abstract

An anti-parallel loop carrier synchronization circuit for coherent binary phase shift keyed (BPSK) demodulation is disclosed. One embodiment comprises an anti-parallel dual phase-locked loop (PLL), which locks the carrier by its upper PLL(0°) and lower PLL
(180°) alternately, according to the data bits contained in the received BPSK signal.

Description

A BPSK DEMODULATOR CIRCUIT USING AN ANTI-PARALLEL
SYNCHRONIZATION LOOP
FIELD OF THE INVENTION
This invention relates to binary phase shift keying (BPSK) based demodulators and applications thereof.
BACKGROUND OF THE INVENTION
Binary phase shift keying (BPSK) can use either coherent or noncoherent techniques depending on what performance is required and which frequency band the system works at. Coherent BPSK has approximately a 3dB advantage over noncoherent BPSK on bit error rate (BER) performance. However, coherent BPSK needs to synchronize and recover the carrier signal with a synchronization circuit in the demodulator.
The squaring loop and the Costas loop are popularly used for this purpose in these systems.
The difference in circuit complexity between the coherent and noncoherent BPSK
becomes less important in systems working at low carrier frequency, since both can be implemented with digital techniques using high speed A/D conversion and digital signal processing (DSP) techniques. At microwave frequencies, however, the coherent method is the preferred demodulation system since the non-coherent technique, such as differential BPSK (DBPSK), strongly depends on the DSP technique for its one-bit delay element, which cannot work at that high frequencies.
A coherent BPSK modulator may be implemented using a multiplier to multiply the data stream with the RF Gamier. In this data stream, bit l and bit 0 are represented by ~ Yz .
FIG. 2.1(a) shows a block diagram of a typical coherent BPSK modulator. An oscillator produces a pure carrier that is fed to a mixer/multiplier. A non-return-zero (NRZ) data (represented by ~ Vz ) is multiplied with the carrier to form the desired BPSK
signal.
Assuming that the un-modulated Garner signal is represented by C(t) = Y cos(r.~~t) (2.1 ) and the NRZ data is represented by + VZ , when bit 1 ) D(t) _ _ YZ , when bit p (2 2 The product of the multiplier will be S(t) =g *D(t)*C(t) =gV,Vz cos(~~t+~p) (2.3) where g is the gain of the multiplier, and _ 0° , whew bit 1 ) 180° , when bit 0 (2.4 It can be seen that the phase of the RF carrier is shifted 180 degrees at the output of the multiplier in accordance with the NRZ data stream, which is shown in FIG. 2.1 (b).
The TX element includes an amplifier, a bandpass filter and an antenna. An additional lowpass filter may be required to filter the NRZ data in order to narrow the transmitted signal spectrum.
A coherent BPSK demodulator requires carrier recovery or so-called carrier synchronization. Some variants of phase-locked Ioop (PLL) were developed for this purpose and popularly used in current systems. One of these is called the squaring loop (FIG. 2.3), in which the incoming BPSK signal is first squared by multiplying the signal with itself to obtain a modulation-free signal at twice the carrier frequency.
A PLL is used to lock the voltage-controlled oscillator (VCO) signal at twice the carrier frequency and thus achieve phase coherence. A frequency divider is used to divide the VCO signal frequency so that after multiplication with the incoming BPSK waveform, the data is recovered.
To describe its operation, we consider the received BPSK signal with the form S(t) =A, cos(w~t + ~p) (2.8) where A, is the amplitude, r~~ is the carrier frequency and the modulation phase rp bears the data information which has a form _ 0° , when bit 1 180° , when bit 0 (2.9) A squaring device such as a multiplier can be used to remove the modulation phase rp .
Assuming the gain of the multiplier is g, the squaring term of the output will be SZ (t) = gA~ cos2 (w~t + rp) _ ~ gA; + ~ gA; cos(2w~t + 2~p) (2.10) where 2~p switches between 0° and 360°. Since 0° and 360° are exactly the same phase and can be ignored in the periodic trigonometric function, the 2rp term is removed from the above squaring term, resulting in SZ (t) _ ~ gA; + ~ gA~ cos(2tv~t) (2.11 ) A band-pass filter tuned at the above double-frequency 2rv~ is necessary after the squaring device to remove the DC term ~ gA; and other harmonic products of the squaring device. Thus, the squaring process removes the signal information contained in the BPSK signal and produces a pure phase-coherent frequency component at twice the frequency of the carrier. This filtered frequency component at 2 r~~ is then used as input to the PLL operating at 2 t~~ . The PLL is locked at this phase-coherent frequency component and then re-establishes the carrier phase at twice the frequency.
For a single PLL using multiplier-type detector the locking point is located at -90°
phase difference;
however, demodulation using the squaring loop requires a zero phase difference between the VCO and the received carrier, so a 90° phase shifter at twice the Garner frequency is desired in the PLL to let the VCO produce the exact carrier phase. The output from the squaring loop above must be frequency-divided by 2 to generate the exact phase-locked carrier for signal demodulation.
The demodulation of a BPSK signal becomes simple after Garner recovery. It can be done using a multiplier to multiply this recovered carrier with the received BPSK signal.
Assuming the recovered phase-locked carrier has the expression S'(t) = AZ cos(~~t) (2.12) Then, the multiplication of this carrier with the received BPSK signal gives S(t) * S' (t) = gA,Az cos(w~t) cos(cv~t + ~p) - g PAZ cos(~p) + g PAZ cos(2~~t + ~p) (2.13) where g is the gain of the multiplier. Note that the above expression contains the data signal D(t)= gA2Az cos(~p) (2.14) where cos(cp) switches between 1 and -1 in accordance with the NRZ data. The high frequency component in the multiplication products as well as harmonic products is removed by the low-pass filter at the output of the demodulator.
Although the squaring device in the squaring loop can remove the data information to recover the carrier from the received BPSK signal, the received noise is also squared.
For additive white Gaussian noise (AWGN), this effectively increases the noise in the loop by 3dB. The squaring loop has a ~ ambiguity at its output phase because it is operating at 2 ~~ ; it cannot distinguish between ~ and 2n for an input phase error. Because of this, the output phase to the multiplier for data demodulation may be in error by ~c radians, which for BPSK would invert the sign of the data and induce continuous data errors. The system needs differential coding prior to modulation and differential decoding after demodulation to solve this problem. In a system using differential coding/decoding, bit l and bit 0 are not represented by two phases, but phase-transition and non-phase transition respectively. Therefore, an inversion of data only causes an error and the following data are not affected by this error. The squaring loop has a further significant disadvantage, which is the need to have the VCO
running at twice the Garner frequency. This is a problem as the carrier reaches the microwave range:

it is more difficult to create a good, low-noise, oscillator at higher frequencies than at lower ones. Furthermore, the need for a frequency divider can increase the power consumption of the circuit, since many dividers are known to sink large amounts of power.
Another circuit that is often used in phase demodulation is the Costas demodulator, developed by J. Costas (see J. Costas, "Synchronous Communications," IEEE
Transactions on Communications, vol.5, pp. 99-105, Mar. 1957.) and illustrated by the block diagram shown in FIG. 2.4. It contains a dual PLL: the upper loop and the lower loop. It is usually assumed that the lower loop works as the locking loop and produces the error voltage to drive the VCO, and the upper loop demodulates the data information and corrects the error voltage of the locking loop through a multiplier.
To understand its operation, we can consider the locking point on the output characteristic curve of the two phase detectors in the dual PLLs, see FIG.
2.5. The two circle points with zero outputs represent the locking loop's outputs at the states of bit 1 and bit 0 respectively, and the star points, the demodulating loop's outputs.
The zero-output point on the right has a negative slope and is not a stable locking point for a single PLL with a positive gain-constant VCO. However, the Costas loop uses a multiplier to correct this point's slope by multiplying the locking loop's output with the demodulating loop's output (- kd @ bit 0). The slope of this point is inverted to be positive by multiplying with the negative value - kd . Thus, this zero-output point (@ bit 0) becomes a stable locking point too and has the same locking characteristic as the left one (@ bit 1) due to the symmetry of the curve. Consequently, the Costas loop can provide a locking process both at the states of bit 1 and bit 0.

A brief mathematical analysis of the Costas loop is given below. It is assumed that the received BPSK signal has the form S(t) = A, cos(w~t + B, + ~p) (2.15) where B, represents the received Garner phase, and rp bears the data information and alters between 0° and 180°. This received signal is multiplied by AZ cos(~~t + B2 ) and - AZ sin(cv~ t + BZ ) in the Costas loop, which are outputs from the VCO
and the 90°
phase shifter respectively. The two products are I (t) = g, S(t) * AZ cos(ayt + BZ ) = g, A, cos(m~t + B, + rp) * AZ cos(w~t +
BZ ) = kd cos(B, - B2 + rp) + kd cos(2w~t + B, + BZ + rp) (2.16) Q(t) _ -gIS(t) * AZ sin(m~t + BZ ) _ -g, A, cos(w~t + B, + ~p) * AZ sin(rv~t +
BZ ) = kd sin(B, - BZ + rp) - kd sin(2~~t + 8, + BZ + tp) (2.17) where g, is the gain of the multipliers in the detectors and kd = g' A, A2 is the detector gain. The double-frequency terms in equations (2.16) and (2.17) are eliminated by the low-pass filters after the multipliers.
An error signal for the VCO control is generated by multiplying the two outputs of the detectors (the low-frequency terms in the above two equations) using another multiplier:
Y ' b'2ka s~~2(B~ _ BZ ) + 2rP~ (2.18) where g2 is the gain of this third multiplier. Note that the data information term 2cp can be eliminated in the above expression since it is either 0° or 360°. Thus, this error signal only consists of the desired term sin[2(B, - BZ )] which has positive slope when the phase error (8, - 62 ) = 0 and can be used to drive the VCO to recover the carrier.
When the phase of the Costas loop is locked, the phase error term ( B, - B2 ) is equal to 0.
Thus, the low-frequency output term at the upper loop becomes I(t) _ 'f~ 2 cos(~p) (2.19) which carnes the demodulated data.
The upper loop was assumed to work as the demodulating loop and the lower loop as the locking loop. This, however, is not always the case. The locking and demodulating functions will be reversed between these two loops if the initial phase of the VCO
changes 90° relative to the Garner phase. This may occur at the beginning of the demodulator operation, or at the re-locking process caused by large phase error from the received BPSK signal. Thus, the receiver requires a decision circuit to determine which loop outputs the demodulated data. Costas used a summer to sum the two detector outputs to overcome this problem. The switching of the functions between the two loops also causes an inversion on the data output, which the summer cannot recognize.
Therefore, a demodulator using the Costas loop also requires differential coding/decoding to solve this data inversion.
The Costas demodulator uses two PLL circuits in parallel that are 90°
out of phase instead of 180°, and a third multiplier circuit. The need for a 90° phase shift requires the use of either a special phase shifter circuit, or a quadrature VCO. In either case, the result of the added components is increased complexity acrd power consumption.
SLfMMARY OF THE INVENTION
In a first aspect the invention provides a BPSK demodulator for use with a BPSK signal.
The demodulator includes a first phase-locked loop for locking to the BPSK
signal and a second phase-locked loop for locking to the BPSK signal. The second phase-locked loop locks to the BPSK signal at a 180° phase difference from the first phase-locked loop.
The first phase-locked loop and the second phase-locked loop are selected such that the first phase-locked loops is in lock at 0° and the second phase-locked loops is in lock at 180°.
The demodulator may also include a selection network for selection of the first and second phase-locked loops. The selection network may have two switches, a comparator, and an inverter. The selection network may have a low-pass filter.
The first and second phase-locked loops may each include a multiplier and a voltage controlled oscillator. The first and second phase-locked loops may each include a low pass filter and a summing circuit. The first and second phase-locked loops may be interconnected to share a single voltage controlled oscillator.
The demodulator may include an automatic gain control circuit front end. The demodulator may include a voltage summer at the VCO front end. The first and second phase-locked loops may each include an amplifier. The first and second phase-locked loops may each include an attenuator.

The demodulator may be implemented in an integrated circuit. A DC offset may be introduced into the phase-locked loops by the summing circuit such that the phase-locked loops have different detected voltage outputs.
In a second aspect the invention provides a method of demodulating a BPSK
signal. The method provides a first phase-locked loop for locking to the BPSK signal;
provides a second phase-locked loop for locking to the BPSK signal. The second phase-locked loop locks to the BPSK signal at a 180° phase difference from the first phase-locked loop. The method also selects the phase-locked loops such that the first phase-locked loops is in lock at 0° and the second phase-locked loops is in lock at 180°.
Selecting the phase-locked loops may include comparing the BPSK signal detected by each of the phase-locked loops to determine the phase of the BPSK signal.
Selecting the phase-locked loops may include opening and closing respective switches in accordance with the determined phase.
The method may include detecting the phase of the BPSK signal in each of the phase-locked loops by multiplying the BPSK signal and a locking signal produced by a voltage controlled oscillator. Detecting the phase may include passing the multiplied signal through a low pass filter and a summing circuit.
The method may include producing the locking signal for both detectors using a single voltage controlled oscillator.
Other aspects, including further demodulators and methods, are evident from the detailed description and FIGS. provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the present invention and to show more were clearly how it may be carried into effect, reference will now be made, by way of example, to the accompanying drawings which show the preferred embodiment of the present invention and in which:
FIG. 2.1 (a) shows the block diagram of a typical coherent BPSK modulator.
FIG. 2.1 (b) shows that in the modulator of FIG. 2.1 (a) the phase of the RF
carrier is shifted 180 degrees at the output of the multiplier in accordance with the NRZ
data stream.
FIG. 2.3 shows a BPSK demodulator using a squaring loop.
FIG. 2.4 shows a BPSK demodulator using a Costas loop.
FIG. 2.5 shows the characteristic of the detectors outputs and the locking process for the phase-locked loop of FIG. 2.4.
FIG. 3.1 shows an anti-parallel loop with two interconnected phased locked loops in accordance with a preferred embodiment of the present invention.
FIG. 3.2 shows a circuit diagram of an embodiment of the BPSK demodulator of FIG.
3.1.
FIG. 3.3 shows characteristic of detector outputs and locking process of the BPSK
demodulator of FIG. 3.1.

FIG. 3.4 a simplified version of the circuit diagram of the BPSK demodulator of FIG.
3.1.
FIG. 4.1 shows a simulated model of the demodulator of FIG. 3.1 for use in simulations.
FIG. 4.2 shows BPSK signal generation in simulations using the model of FIG.
4.1.
FIG. 4.3(a) shows PRBS data for modulation in simulations using the model of FIG.
4.1 and the BPSK signal generation of FIG. 4.2, where 9e =60°.
FIG. 4.3(b) shows outputs of LPFs in the simulations of FIG. 4.3 (a).
FIG. 4.3(c) shows outputs of phase detectors(after voltage summers) in the simulations of FIG. 4.3 (a).
FIG. 4.3(d) shows demodulated PRBS data with inversion (after comparator) in the simulations of FIG. 4.3 (a).
FIG. 4.4(a) shows PRBS data for modulation in simulations using the model of FIG.
4.1 and the BPSK signal generation of FIG. 4.2, where 8e =130°.
FIG. 4.4(b) shows outputs of LPFs in the simulations of FIG. 4.4(a).
FIG. 4.4(c) shows outputs of phase detectors(after voltage summers) in the simulations of FIG. 4.4(a).
FIG. 4.4(d) shows demodulated PRBS data with inversion (after comparator) in the simulations of FIG. 4.4(a).

FIG. 4.5(a) shows PRBS data for modulation in simulations using the model of FIG.
4.1 and the BPSK signal generation of FIG. 4.2, where 8e =220°.
FIG. 4.5(b) shows outputs of LPFs in the simulations of FIG. 4.5(a).
FIG. 4.5(c) shows outputs of phase detectors(after voltage summers) in the simulations of FIG. 4.5(a).
FIG. 4.5(d) shows demodulated PRBS data with inversion (after comparator) in the simulations of FIG. 4.5(a).
FIG. 4.6(a) shows PRBS data for modulation in simulations using the model of FIG.
4.1 and the BPSK signal generation of FIG. 4.2, where Be =300°.
FIG. 4.6(b) shows outputs of LPFs in the simulations of FIG. 4.5(a).
FIG. 4.6(c) shows outputs of phase detectors(after voltage summers) in the simulations of FIG. 4.5(a).
FIG. 4.6(d) shows demodulated PRBS data with inversion (after comparator) in the simulations of FIG. 4.5(a).
FIG. 4.7 shows a more detailed experimental embodiment of the demodulator of FIG.
3.1.
FIG. 4.8 (a) shows experimental results at outputs of the detectors in the embodiment of FIG. 4.7 for Yd~ =O.SV (after the two amplifiers).
FIG. 4.8(b) shows further experimental results including PRBS data for modulation(Channel 1) and demodulated data (Channel 2) .

FIG. 5.1 shows a BER versus Eb/No curve on different DC offset values using the experimental circuit of FIG. 4.7.
FIG. 5.2 shows phase detector output curves before voltage summers in the experimental circuit of FIG. 4.7.
FIG. 5.3(a) shows spikes at the output of switches in simulations where Vd~=0.3V.
FIG. 5.3(b) shows spikes at the output of switches in simulations where Vd~=0.5V.
FIG. 5.4 shows data inversions induced by the spikes of FIG. 5.3(a) and FIG.

5.3(b) (for cos(9e) > 0 case).
FIG. 5.5 shows a further embodiment of the BPSK demodulator of FIG. 3.1 incorporating spike suppression.
FIG. 5.6 shows simulation results with spike suppression( for cos(6e ) > 0 case) of FIG.
5.5.
FIG. 6.1 shows a further embodiment of the BPSK demodulator of FIG. 3.1.
FIG. 6.2 shows an example circuit diagram of the embodiment of FIG. 6.1.
FIG. 6.3(a) shows example waveforms from a Gilbert multiplier (the two large signals with 90° phase difference) and the output of a voltage summer in the circuit of FIG. 6.2 in the case of zero DC offset from the voltage summer.

FIG. 6.3(b) shows example waveforms from a Gilbert multiplier (the two large signals with 90° phase difference) and the output of a voltage summer in the circuit of FIG. 6.2 in the case of 0.1 V DC offset from the voltage summer.
FIG. 6.4 shows an example circuit diagram for a current mirror for the two voltage seers of FIG. 6.2.
FIG. 6.5 shows an example circuit diagram for a complementary differential VCO
for use in the demodulator of FIG. 6.1.
FIG. 6.6(a) shows example waveforms at the outputs of the differential VCO of FIG. 6.5.
FIG. 6.6(b) shows example waveforms of VCO frequency versus control voltage the differential VCO of FIG. 6.5.
FIG. 6.7 shows an example circuit diagram of an NMOS switch and differential comparator implementation for the embodiment of FIG. 6.1.
FIG. 6.8(a) shows simulation results for waveforms at the inputs and the outputs of the differential comparator of FIG. 6.7.
FIG. 6.8(b) shows simulation results for waveforms at the output of the switches and the voltage on varactors of FIG. 6.7.
FIG. 6.9 shows a mufti-band embodiment of the BPSK demodulator of FIG. 6.I .
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to the FIGS., the preferred embodiment provides a novel circuit to demodulate, or extract, the information data signal from a BPSK-modulated Garner. The circuit uses two parallel phase-locked loops (PLLs) in which only one of the loops is in lock at any given time. One loop is in-phase with the carrier at 0° while the other loop is 180° out of phase. If the incoming BPSK signal is at 0°, then the in-phase PLL will be in lock. When the incoming BPSK waveform changes phase from 0° to 180°, the loop with the 180°
phase shift will then come into lock and the other PLL will be out-of lock. A
decision mechanism consisting of a comparator circuit decides whether the 0° or the 180° PLL is in lock and from this information the digital data signal is recovered. This is demonstrated both in simulation and in experiments. This circuit can achieve very high data rates because the time it takes for the PLLs to achieve lock when there is a transition in the phase of the carrier from 0° to 180° is very small since the loop that is out of lock is in 'stand-by' mode, ready to achieve lock when the incoming signal changes phase.
Modulation-demodulation systems and bit error rate (BER) measurements were used to demonstrate performance of the circuit. In the BER measurement, a very long stream of random bits (e.g. 2z3) were sent through the transmitter and then recovered at the receiver using the demodulator circuit. As discussed below, very low error rates were achieved.
Referring to FIG. 3.1, an anti-parallel loop for coherent BPSK carrier synchronization method uses two PLLs with 180° phase difference, resulting in an anti-parallel loop structure. The PLLs are interconnected such that the locking phase alternates between both PLLs according to a selection network that recognizes the phase of the incoming BPSK signal. This can be contrasted with the prior quadrature (90 degree phase shift) loop structure in the Costas loop discussed previously.

The Costas loop uses two PLL circuits in parallel, but the the Costar loop uses two PLLs that are 90° out of phase . The need for a 90° phase shift requires the use of either a special phase shifter circuit in the Costar Loop, or a quadrature VCO. In either case, the result is an increase in complexity and power consumption if a quadrature VCO
is used.
In the demodulator of FIG. 3.1, since only a 180° shift is required, a compact differential VCO may be used. Also, for example, the number of multiplier elements can be reduced to lower circuit complexity and power consumption.
The anti-parallel loop can be implemented using two interconnected PLLs that share a VCO, with an 180° phase shifter in the lower loop and two switches with their control circuit at the VCO input. It is well known that a single PLL can lock to a pure Garner signal without phase switching. With proper control of the switches, an anti-parallel loop with 180° phase difference can provide the locking to the PLLs from a received BPSK
signal, which switches its phase between 0° and 180°. For example, when the received BPSK signal is at 0° phase, the upper switch closes and the lower switch opens, and therefore the output of the upper loop is fed to the VCO and it operates like a single PLL
for the locking. When the received BPSK signal switches its phase to 180°, the upper switch opens and the lower switch closes, and thus the lower loop will operate as the locking loop. Since the two loops have 180° phase difference as consistent to the BPSK
signal phase switching difference, the VCO phase will remain stable during switching of the locking between these two loops, and the VCO output will therefore recover the carrier.
Proper control of the switches is desired for the above operation of the anti-parallel loop.
The control circuit of the switches has two inputs and requires a voltage difference between these two inputs in order to produce the proper control signal. If multiplier-type detectors are used in this anti-parallel loop and the upper loop was assumed to lock, the upper detector outputs zero (it is assumed that the carrier frequency is equal to the centre frequency of the VCO here and in the following description and analysis). The phase difFerence between the two inputs is -90° at this time, according to the detector characteristic shown in FIG. 2.5 (located at the locking point). At the same time, due to the 180° phase shifter at the lower loop, the phase difference for the lower detector is 90°
(located at the unstable point) and also has zero output. Because the inputs of the control circuit come from these two detector outputs, the control circuit would fail to distinguish these two zero inputs and give the proper control signal for the switches.
Two multiplier-type detectors with DC offsets can produce the desired different outputs in this anti-parallel loop and meet the above requirement. FIG. 3.2 gives the circuit diagram of the proposed BPSK demodulator in detail based on the anti-parallel method, where a DC offset Vd~ is introduced into each detector by using a voltage summer, and the control circuit is realized on a comparator and an inverter. It is simple to explain the operation of this demodulator if we assume the upper switch closes (the lower switch opens) and the upper loop works as locking loop first. When the upper loop is locked, the VCO's phase is driven to let the upper detector output a zero voltage, that is, a - Yd~
voltage is produced from the upper multiplier-type detector (excluding the voltage summer), in order to cancel the DC offset Yd~ at the output of the upper voltage summer.
At the same time, the voltage from the lower multiplier-type detector is Yd~
due to the 180° phase difference between the two loops. As a result, the output of the lower voltage summer will be 2 Yd~ , which is also the lower detector output. Thus, this 2 Vd~ voltage output at the lower loop and the zero output at the upper loop are fed to the comparator in the control circuit together to produce a positive signal to close the upper switch (the inverter produces a negative signal to open the lower switch). These switch states are exactly what we assumed at the beginning. When the phase of the received BPSK
signal switches 180°, the upper detector outputs 2 Vd~ and the lower detector outputs zero. The control signal after the comparator is inverted turns on the lower switch only, and then the lower detector's output (zero) is fed to the VCO to lock its phase.
The output of the lower multiplier-type detector Yd~ , relative to the output of the upper detector -Vd~ in the first case above, can be explained in FIG. 3.3. It gives the multiplier-type detector output versus its two input phase difference. The output of the upper multiplier-type detector was pushed from the zero point on the left to - Y~,~
(the locking point) by the upper DC offset Vd~ . Now Iet's consider the lower multiplier-type detector.
Its phase state is located at the opposite point shown in FIG. 3.3, which is 180° away from the locking point of the upper multiplier-type detector. Since this detector output curve is a symmetric cosine function, the opposite point will be at the point with voltage inverted to that of the locking point, i.e. Ird~ .
Note that the input of the VCO remains at zero when the received BPSK signal switches its phase, so the VCO phase remains stable and the input phase difference ( Bd ) of the detector stays at the locking point. Therefore, the data information contained in the BPSK signal is removed by switching the locking loop between the two loops and the carrier is recovered. It should be also noted that the control signal for switching from the comparator is exactly the demodulated data signal, so a coherent BPSK
demodulator is realized based on the anti-parallel method illustrated in FIG. 3.2.

Let's assume again that the received BPSK signal has the form S(t) = A, cos(~~t + B, + ~p) (3.1) where e~ represents the received carrier phase, and ~ bears the data information and switches between 0° and 180°. This received signal is multiplied by AZ cos(r,~~t + Bz ) ~d-AZ cos(c~~t +82 ) ~ v,~ch are the outputs from the VCO and the 180°
phase shifter, respectively, see the redrawn circuit diagram of the proposed BPSK demodulator in FIG.
3.4. The Garner frequency is equal to the centre frequency of the VCO in this analysis.
The case that they are not equal will be discussed at the end of this analysis. The products of the two multipliers are U(t) = S(t) * AZ cos(c~~t + BZ ) = A, cos(r~~t + B, + ~p) * AZ cos(c~~t + BZ ) = kd cos(Be + rp) + kd cos(2~~t + 8, + BZ + ~p) (3.2) L(t) _ -S(t) * AZ cos(w~t + BZ ) _ -A, cos(rv~t + B, + ~p) * AZ cos(~~t + BZ ) - -kd cos(8e + ~p) - kd cos(2~~t + B, + BZ + ~p) (3.3) Where the multipliers are assumed to have a unit gain to simplify the analysis, kd = A'2 Z is the phase detector gain and 6e = B, - BZ is the initial phase difference between the carrier and the VCO. The double-frequency terms in equations (3.2) and (3.3) are eliminated by the low-pass filters. After the low-pass filters, the two low-frequency signals enter the voltage summers and sum with the DC offsets, which results m:

U' (t) = kd cos(9e + ~p) + Yd~ _ ~kd cos(Be ) + Vd~ (3.4) L' (t) _ -kd cos(Be + rp) + Yd~ _ +kd cos(Be ) + Vd~ (3.5) where the data information cp alternates between 0° and 180°, resulting in a"~" sign for the cosine functions. As we can see, the two outputs in equations (3.4) and (3.5) alternate oppositely between two voltage values V, = kd cos(Be ) + Yd~ and V, _ -kd cos(Be ) + Yd~ (3.6) Since the configuration of the control circuit in the anti-parallel loop only allows the detector output with smaller value to pass the switches and enter the VCO, if the initial value of cos(Be ) before locking is negative, the first value ~ above is the smaller one and it is selected as the error voltage Ve to drive the VCO regardless of which loop it is from. Then the error voltage is YB = ~ = kd COS(Be ) + Ydc where the data information cp or the "~" sign in equations (3.4) and (3.5) is eliminated by the control of the switches above. Thus, the VCO phase will remain stable when the phase of the received BPSK signal is switched in accordance with the data information.
When the VCO is locked, its input error voltage is Ye = ~ = 0 , which results in Be = cos-' (-Yd~ ~ ka ) _ - 2 - ~ (3.8) where ~ - sm ~ (Yd~ ~ kd ) . 'This result is consistent with with the location of the locking point in FIG. 3.3. Substituting the ge value in the expression of YZ in equation (3.6) yields the demodulating loop's detector output:
Yz = -kd cos(9e ) + Yd~ = Yd~ + Yd~ = 2Yd~ (3.9) The YZ (i.e. 2Yd~) and v~ (i.e. 0) are then fed to the comparator to produce the data output and the proper control signal.
In the above analysis, the VCO is locked to the upper loop at bit '1' and to the lower loop at bit '0' as the result of c°s(9e ) <0. However, if the initial value of c°s(Be ) before locking is positive, the locking state in the above case will be reversed, i.e. Y2 is the smaller one and is chosen for the error voltage to drive the VCO. When the VCO
is locked, Ye - YZ - 0 , and the phase difference between the Garner and the VCO
is (3.10) a 2 Since the VCO is locked to the lower loop at bit '1', there is an additional 180° phase introduced from the phase shifter to the loop and the phase difference between the lower detector inputs for this case is (3.11) It is still at the same location (the locking point in FIG. 3.3) as in the last case.
Substituting equation (3.10) into equation (3.6) results in Y~ - 2Ya° .
In this case, the output of the comparator is zero in order to turn on the lower switch, which results in an inversion on the data output compared to the last case. Thus, similar to the other synchronization methods, this anti-parallel loop also needs the differential coding/decoding to correct the data inversion.
The two DC offsets are assumed to be the same in the above operation description and the analysis. The proposed demodulator still works when there is a difference between the two DC offsets, which usually comes from the variation of element values in manufacturing. In this case, the detector of the demodulation Ioop will output ~a~i + ~dc2 ) instead of 2vd~ , where ~d~~ and ~dc2 represents the two different DC offsets.
The detector output of the locking loop still keeps zero in this case.
Moreover, if there was a small deviation on the carrier frequency of the input BPSK signal from the centre frequency of the VCO, the detector of the locking loop outputs a small error voltage of ~
when the loop is locked, and the detector output of the demodulation loop becomes ~ 2Yd~ - 8 ~~ or ( Yd~~ + Va~z - 8 ) if the two DC offsets are different. Note that the two detectors still have different outputs to ensure the demodulator operation until S exceeds Y''° , or ~yd~~ + yd°z ) ~ 2 for the case of the different DC offsets.
The embodiments described herein provide a novel synchronization method for a BPSK
demodulator, which contains an anti-parallel loop and two switches with the control circuit. The functional description of the demodulator and the mathematical analysis indicate that the demodulator can recover the carrier and demodulate the data properly.
The introduced DC offset determines the output level of the two detectors.
The BPSK demodulator was demonstrated both in simulations and experiments The proposed BPSK demodulator was simulated in the electronic design automation software known as Advanced Design System (ADS), based on its system-level components, as shown in FIG. 4.1. The center frequency of the VCO was set to 133kHz.
Other features of the VCO are given below:
Gain Constant: 14~ Krad/Volt Output Power: 14 dBm An ideal 180° phase shifter was chosen in this simulation. Two simple RC low-pass filters (LPFs) were used for the loop filters in the phase detectors. The cutoff frequency of the LPFs was carefully chosen according to the data rate in order to avoid inter-symbol interference (ISI) and to have good noise performance at the same time. A data rate of l OKbps was used in these simulations, so a cutoff frequency of 14.4kHz was chosen for the two LPFs. Another consideration for the PLL is the damping factor. An optimized damping factor is 0.7. The multipliers in the phase detectors had the following parameters:
Input power: 14 dBm Output signal: double-sideband Conversion Gain: -7dB
which resulted in a gain of Kd=1 V/rad for the phase detectors and thus 0.72 for the damping factor. The voltage summers for the DC offsets were implemented using two ideal voltage summers. A simple design of these voltage summers will be discussed later in this description. The switches after the voltage summers utilized a single-pole double-throw switch, which had the same function as that of the two switches. This switch was controlled by a comparator implemented using an operational amplifier (OPAMP) and could give proper switching operation for this demodulator.
The modulated BPSK signal used in the simulations came from a multiplication of a carrier source at 133 kHz and a pseudo-random pulse sequence (PRBS) data at 10 kbps, see FIG. 4.2.
The simulations were carried out with different carrier phases while the VCO
initial phase was fixed in order to observe the locking processes in all initial phase differences between the VCO and the carrier. The initial phase of the VCO was BZ =
0° in the simulations while the phases of the carrier were chosen as B, = 60°, 130°, 220° and 300°, which were in the four phase quadrants, respectively. They resulted in the initial phase differences Be = Bl -BZ =60°, 130°, 220° and 300°, which covered all the cases for cos(Be) > 0 and cos(Be) < 0 discussed previously. The DC offsets were Yd~
=0.3Volt.
The simulation results for the case of Be = 60° are presented in FIG.
4.3. As can be seen, the outputs of the two LPFs were ~ Yd~ _ ~0.3Y alternately (FIG. 4.3 (b)), and the detector outputs (after the voltage summers) alternated between 0 Volt and 2Yd~ = 0.6Y (FIG. 4.3(c)), which were expected from the analysis provided previously.
These outputs were accompanied with small components at 266kHz. Furthermore, there were small overshoots after the transitions of these outputs, which were determined by the damping factor of the PLL. The PRBS data was demodulated successfully with an inversion. This result had been predicted in the second case of the mathematical analysis previously, i.e. cos(Be ) > 0 case. As discussed previously, the inversion may be corrected by using additional differential coding/decoding. A locking process at the beginning of the demodulated data caused a sharp transient; however, this is not a problem in communication systems, since a testing data sequence is usually sent before the locking is set up.
Simulation results with other initial phase differences Be =130°, 220° and 300° are presented in FIG. 4..4, FIG. 4.5 and FIG. 4.6, respectively. It can be noted that the locking operation worked well and the demodulator also recovered the PRBS data in these cases. Furthermore, FIG. 4.6 also shows an inversion on its demodulated data because of its positive cos(Be ) initial value, while FIG. 4.4 and FIG. 4.5 have the exact demodulated data due to their negative cos(Be) initial value.
More simulations with different values of Be from the above four cases were conducted and the results agreed with these four cases and the analysis in provided previously, and verified proper operation of the BPSK demodulator.
Based on the above simulations, a circuit was built using packaged integrated circuit components, see FIG. 4.7. Two four-quadrant analog multipliers were chosen for the phase detectors, which had an additional summing input and were utilized for the DC
offsets needed in this demodulator. The VCO was implemented with a digital VCO
with a low-pass filter at its output to reject the harmonics and produce a sinusoid signal. Its center frequency was 133KHz and the measured constant gain was 14~ Krad/volt.
An amplifier with an inversion and unit gain was used for the 180° phase shifter. The cutoff frequency of LPFs for the loop filters was 14.4 KHz. The loss of the multiplier ICs was too large (20dB loss) and resulted in a very small detector gain kd . In order to achieve the optimal damping factor 0.7, an amplifier was introduced in each loop to compensate for the loss of the multipliers. It could be regarded as one part of the phase detector to increase the detector gain. The detector gain kd (including the gain of the amplifier) was measured to be 0.9V/rad in the experiments. The switches were implemented with two N
MOSFETs controlled by the signals from a comparator circuit and an inverter.
An example configuration of the switches will be further discussed later in this description.
The BPSK signal generator used for the verification test was similar to the setup in the simulations. It used a multiplier circuit to multiply a carrier signal (133KHz) with a PRBS NRZ data (lOKbps) coming from HP 3764A digital transmission analyzer (DTA).
The NRZ data from the DTA was transformed to be systematic data ( ~ 2 V) before it went into the multiplier.
A DC voltage Yd~ = 0.04Y was fed to the summing input of each multiplier in the test, which would be equivalent to a DC offset Yd~ = O.SY after the amplifier (considering the amplifier is one part of the detector). FIG. 4.8 presents the experimental waveforms captured from the test. FIG. 4.8(a) gives the outputs of the two detectors.
Note that the two outputs offset with each other and their voltage levels were 0 V and 2Yd~
=1 V, which were expected according the analysis provided previously. The detector outputs before the DC offsets could not be obtained because the voltage summer was integrated in the multiplier ICs. FIG. 4.8(b) gives the modulating PRBS data (Channel 1) used for the test and the successfully-demodulated data (Channel 2) from the BPSK
demodulator.
It should be pointed out that the waveforms shown in FIG. 4.8 were captured at different times and thus contained different data information (the PRBS data varies with time).

The case that the demodulated data would contain an inversion of the modulating PRBS
data was also observed occasionally when the circuit was reset in the experiments. The experiments were in accordance with the analysis of the locking processes concerned with the initial phase differences as discussed previously. A demodulator with variations of the Garner frequency and DC offset as discussed previously was also demonstrated both in simulations and experiments.
The simulation results illustrated the different locking processes of this demodulator regarding all the possible initial phase differences between the VCO and the carrier in the received BPSK signal, which was expected from the mathematical analysis discussed previously. The experiments confirmed the above locking processes. Moreover, the results from the simulations and the experiments demonstrated the relationships between the detector outputs and the introduced DC offsets in the detectors, and the role of the DC
offsets in this demodulator. Noise performance of the demodulator system may depend on the DC offsets, which will be discussed later.
An embodiment using automatic gain control (AGC) will now be described. In the demodulator shown in FIG. 3.2, the dual anti-parallel loop locked to the BPSK
signal (two phase states) can be simplified to a single PLL locked to a pure carrier, given an ideal switching operation from the switches. Thus, the design issues about the phase-locked loop can be applied on this dual loop. The optimal condition for a PLL
is a damping factor of about 0.7, as determined by the detector gain, the gain constant of the VCO and the cutoff frequency of the loop filter according to equation (2.7), which is re-written here:

(5.1) 4kd ko 4k where, k " ko kd is the loop gain.
The performance of the phase detector is concerned with its detector gain kd .
It is defined as:
kd = Vd ~ ed (5.2) where vd is its voltage output and 9d is the phase difference between its two input signals. As discussed previously, for a multiplier-type detector, since the output versus the input phase difference is a cosine function, the detector gain may be approximated to the slope at the locking point when the loop is locked:
kd = gA,Az (5.3) where the detector gain is determined by the multiplier gain g and the two inputs' amplitudes, A1 and A2 . Thus, to keep the detector gain kd constant for an optimal damping factor, the received BPSK signal amplitude and the VCO's output amplitude are required to remain stable at all times. A stable BPSK signal can be achieved by an automatic-gain-control (AGC) circuit before the BPSK demodulator.
Gain constant is important to the VCO and can be defined as:
k = ~~
Ovd where ~r7 is an angular frequency of the VCO output and vd is the VCO control voltage coming from the phase detector. An ideal VCO has a constant ko , which indicates linear frequency tuning for the VCO and ensures a constant damping factor in the phase locking process. However, in a practical circuit, such as a VCO with varactor control, linear frequency tuning is limited to a specific range. The tuning becomes nonlinear and saturated beyond such range. Therefore, the VCO input from the phase detector should not exceed this tuning range.
Another consideration for the VCO is phase noise, since it introduces an additional phase error into the loop and affects the locking. Phase noise is mainly concerned with the Q
factor of the VCO. A LC oscillator with high Q is preferred in the VCO in order to suppress the phase noise, as well as increase the LC tank amplitude.
An embodiment using an amplifier or a voltage attenuator in the loop will now be described. The loop filter may be implemented with any order low-pass filter, while a higher order low-pass filter usually provides better filtering characteristics, but with a more complex structure. In the design of a single PLL, the cutoff frequency of the loop filter is flexible to change in order to achieve the optimal damping factor based on the given detector gain and the gain constant of the VCO. However, as we can see in FIG.
3.2, the loop filter in the anti-parallel loop is also used for data filtering. The choice for the selection of this cutoff frequency is a balance between noise performance where it is desired that the cutoff frequency is as small as possible to reduce the noise bandwidth of the receiver, but too small bandwidth will cause inter-symbol interference (ISI). The cutoff frequency of the loop filter for the simulations and experiments was selected for data filtering characteristics, and was not a variable for optimizing the damping factor.

The cutoff frequency was chosen at a frequency slightly higher than the data rate if RC
low-pass filters are employed.
The problem mentioned above can be solved, for example, by introducing an amplifier (as in the case of the experimental circuit) or a voltage attenuator to change the loop gain k , in order to meet the requirement for the optimal damping factor. The loop gain now has the form k = kakokd (5.4) where ka is the added gain by the amplifier or the voltage attenuator. The voltage attenuator may be implemented with a resistor potentiometer. In this way, the damping factor may be optimized easily, without restricting other performance aspects of the above three loop elements for this purpose.
Example: Switch Tmplementation Using MOSFETs As is well known, a field-effect transistor has advantages for implementation as a switch, such as nearly zero control current, low drain-source resistance in the "on"
state, and high drain-source isolation in the "ofd' state. Besides those advantages, it is also preferred that the switches in this demodulator transmit the detector output (around zero volt when the loop is locked) to the VCO with as low voltage-loss as possible in order to achieve tight locking. Two N MOSFETs in symmetric configuration are suitable for these switches and such an implementation is discussed later in this description.
The comparator in the control circuit amplifies the small voltage-difference signals from the two loop detectors (between 0 and 2 Vd~ ) to the proper level for the control of the switch and the inverter. The inverter inverts the comparator output for the other switch so that only one switch is allowed to be turned-on at any time. For NMOS
switches, the maximal control voltage should exceed the threshold voltage of the NMOSFET to turn on this device completely, while the minimal control voltage should be around zero or less to completely turn off the device.
The DC offset Vd~ in each loop is another consideration in this implementation of the demodulator because it not only introduces voltage difference between the two loops to ensure the proper operation of the control circuit and the switches, but also determines the signal amplitudes from the detectors (between 0 and 2 Vd~ ). Thus the DC
offset Vd~ is a factor in the signal-to-noise ratio (S/N) of the detector outputs and affects system performance.
BER Measurements A bit error rate (BER) measurement on several DC offset values was carried out based on the experimental circuit described previously in this description in order to investigate the effect of DC offset on system performance. A pseudo-random bit sequence (PRBS) with a length of ( 2z3 -1 ) was tested at l Okbps in this measurement. The noise was generated from a noise source with the ability to generate the additive white Gaussian noise (AWGN). The measured BER values versus the bit energy to noise density ratio (Eb/No) on different DC offsets is shown in FIG. 5.1, as well as a theoretical BER
curve for BPSK. For the measurement results, the Eb/No is calculated from Eb l No = S , BW (5.5) N 2 f$

where S/N is the input signal to noise ratio, BW is the input noise bandwidth (double sideband) of the demodulator and fB is the bit rate. The theoretical curve is calculated by the probability of bit error for a BPSK demodulator BER = Q No =_ ~ erf ~ °o ~ (5.6) As seen in FIG. 5.1, the measured BER curve is close to the theoretical curve when the DC offset went up. The theoretical curve illustrates the ideal result available from a BPSK demodulator. The measurement result indicated that better BER performance could be achieved by use of larger DC offset in the anti-parallel loop demodulators.
DC Offset Considerations Since the loop outputs before the voltage summers cannot exceed ~ kd , which is the maximal output range of the multiplier-type detector, the DC offsets fed to the voltage summers cannot go over kd accordingly. Otherwise, the output of the multiplier-type detector would not compensate the DC offset to produce zero voltage for locking and therefore the VCO would lose locking. When the DC offset Y~~ goes up to the vicinity of the maximal value kd , the slope of the detector output versus its two inputs' phase difference decreases, see FIG. 5.2. The reduced slope decreases the detector gain, and as a result, increases the damping factor of the loop according to equation (5.1). A large damping factor makes the response of the loop slow (over-damped case) and easy to lose locking.

Hence the vicinity of the maximal value is not suitable for the DC offset in this case.
According to FIG. 5.2, the DC offset Vd~ may go up to 70% of the maximal value ( kd ) without much change of the slope; nevertheless, the headroom for the DC offset is further reduced due to spikes at the switches' output. In the analysis discussed previously, two voltage levels were assumed at the outputs of the detectors, OV and 2 Vd~ .
With proper selection by the switches, only the lower voltage OV is fed to the VCO. This is not the case when the distortion effect of the loop filters on the detector outputs is considered.
The loop filters have low-pass characteristics and smoothen the detector outputs (digital signals) as well as reject higher harmonics. 'This smoothing operation distorts the detector outputs by increasing their rise time and fall time. The outputs of the detector thus cannot be regarded to have only two voltage levels. As a result of the increased rise/fall time, there will be spikes on the output of the switches to the VCO.
FIG. 5.3 illustrates the existence of these spikes both in the simulations and the experiments. The spikes occurred at every data transition and reached one half of the DC offset Yd~ . If not addressed, these spikes can deviate the VCO phase and force the locking point to go over the negative peak on the left (shown in FIG. 5.2) to the other negative slope (not shown), and then lose locking if the DC offset was set higher than 0.5 kd . The re-locking process may lock the VCO to the other phase of the received BPSK signal and induce an inversion on the data output; hence, continuous errors could occur. FIG. 5.4 shows spike-induced data inversions in the simulations with DC offsets of 0.7V ( kd =1 V), where the inversions occur at 0.3ms and 0.8ms .
A further embodiment using another LPF will now be described The spikes at the VCO input might cause inversion of the data output when the DC offset goes over one half of kd . 'This limits increasing the DC offset value to provide better BER performance. Introducing another low-pass filter after the switches can suppress the spikes. This is shown in the demodulator of FIG. 5.5. The cutoff frequency of this filter determines how much the spike amplitude can be reduced, and would typically be set to lower than the data rate (maximal repeating frequency of the spike). This configuration can significantly suppress the spikes and extend the headroom of the DC offset to allow better BER performance. The introduced low-pass filter can be seen as one part of the loop filter in calculating loop parameters such as the damping factor in the equation (5.1).
The loop noise bandwidth, which is concerned with the loop gain k and the cutoff frequency of the loop filter, is required to be larger than the phase noise bandwidth of the carrier generator in the transmitter side in order to make the loop fast enough to acquire the phase of the carrier with noise, so there is a lower limit for the cutoff frequency of the introduced LPF.
FIG. 5.6 shows the simulation result based on the demodulator of FIG. 5.5, where the DC
offset was 0.7V ( kd =1 V) and the cutoff frequency of the introduced LPF was 5 KHz.
The loop gain was re-arranged to optimize the damping factor according to the introduced LPF compared to FIG. 5.4. It is noted that the spikes were suppressed by the LPF and there was no inversion induced by the spikes (the demodulated data kept its original inversion for cos(9e ) > 0 case). In this way, the headroom for the DC offsets may be increased.
Except for the distortion of the loop filters, larger spikes may als come from noise. If the DC offsets are set close to the kd, they may cause sporadic inversions on the demodulator output, even though they are suppressed by the third LPF. The sporadic inversion can induce continuous bit errors of the following data to the DTA
analyser in the experiments. If desired, this can be addressed by differential coding/decading before the modulator and after the demodulator respectively, which can correct continuous bit errors caused by sporadic data inversions.
Example: Design Methodology Based on the considerations and the variations discussed above, a preferred design methodology may be summarized as:
1. Design the multipliers and the voltage summers. The inputs and outputs of the multipliers require matching circuits at microwave frequency.
2. Design the VCO at the desired centre frequency. A linear tuning range is preferred. The output amplitude of the VCO meets the requirement of the multiplier input.
3. Design the loop filters. According to the data rate, choose the appropriate cutoff frequency, usually at a frequency equal to or a little higher than the data rate.
4. Design the low-pass filter at the input of the VCO to suppress the spikes.
Its cutoff frequency can be set to lower than the data rate. At the same time, the total noise bandwidth of the loop should be larger than the phase noise bandwidth of the carrier generator in the modulator.

5. Optimize the damping factor to 0.7 according to equation (5.1), where its cutoff frequency tc~L requires adjustment by considering the contribution of the introduced LPF at the input of the VCO.

6. Choose as large a DC offset as the system can tolerate to achieve the best system performance. The offset determines the two loop outputs.

7. Design the switches and their control circuit. The required comparator gain is determined by the difference between the loop output amplitude and the desired control signal amplitude of the switches.
Example: IC Implementation An integrated circuit (IC) embodiment of an anti-parallel loop BPSK
demodulator based on CMOS technology, including possible IC implementations of certain parts of the demodulator, will now be described. A compact structure of the demodulator can be achieved by making full use of current IC technologies, such as an integrated Gilbert multiplier, differential VCO and CMOS switches. A mufti-band demodulator based on the above compact topology will also be discussed.
A compact IC design of an anti-parallel loop demodulator based on available integrated-circuit elements is presented in FIG. 6.1, where the multipliers for the detectors are implemented on two Gilbert-cell mixers, which are usually used for analog phase detectors. Their differential input signals come from a differential VCO. The differential-signal lines (two lines) from the VCO to the lower multiplier are twisted once before they enter the multiplier, by which a 180° phase shift is produced. This can be done easily in IC implementation and thus eliminates the use of other phase shifting devices.
The demodulator makes the best of this configuration to reduce the system complexity. The voltage summers for the DC offsets are integrated into the Gilbert multipliers in FIG. 6.1.
The switches are implemented with two N channel MOSFETs as demonstrated in the experiments and their control signals are from a differential comparator, thus the inverter is saved. The two loop filters may be any order low-pass filters while a RC
low-pass filter is the simplest. The third LPF at the VCO input may also be realized with a RC
low-pass filter. More details about the above designs based on the TSMC 0.18um CMOS
models will now be discussed.
As a multiplier-type mixer, the Gilbert cell in theory has perfect isolation among the three signals LO, RF and IF, due to its balanced structure. Thus the Gilbert cell does not require extra filters as required for isolation in other mixers. These features make it very suitable for the voltage multiplier in the analog phase detector. FIG. 6.2 shows a Gilbert multiplier with a voltage summer for the loop DC offset.
In FIG. 6.2, the multiplier uses a common Gilbert cell topology. The bias current for the Gilbert cell is realized on a current minor circuit. The LO signal coming from the differential VCO and the received RF signal are fed to the Gilbert multiplier, mixed with each other and output to the following voltage summer. The voltage summer can be achieved easily using a differential pair biased by a current mirror circuit.
The control voltage of the current mirror Vc is for the loop DC offset and it controls the current IS
flowing through the differential pair and the IS relies on Yc by IS=vcRyss (6.1) c Then the DC offset or the DC voltage Yd~ at the outputs of the voltage summer is related to the control voltage Y~ by Ydc - Ydd I d 2 R4 - Ydd ~ 2s R4 - ~ (YC - YSS ) -F- Ydd C
By choosing 2 as the ratio of the above resistor R4 and Rc , the voltages Ydd and Y~ are cancelled if Ydd = -Yss ~ ~d it results finally in Yd~ _ -Yc (6.3) Thus the output of the voltage summer will sum the signals from the Gilbert cell with the inversion of the control signal Y~ . In a practical design, in addition to the DC mixing product, the output from the Gilbert cell also contains a DC bias which needs to be compensated at the voltage summer, the above resistor ratio cannot be set to 2 ideally.
Therefore, there will be a coefficient less than 1 before the Yc in equation (6.3).
In simulations performed using the TSMC 0.18um CMOS models, the frequencies of the LO signal and the RF signal were 1.SGHz, which is at L-band of INMARSAT
systems and the GPS system. Their amplitudes were set to 0.4V. Larger inputs would cause signal distortion as observed in the simulations. FIG. 6.3 shows the inputs of the Gilbert multiplier (the two large signals) and the output of the voltage summer (the small signal) at OV and O.1V DC offsets, respectively. The two large signals illustrate the RF signal and the LO signal, and they were set to 90° phase shifted from each other (orthogonal), so the multiplication of these two signals yields no DC product as illustrated in FIG. 6.3(a), in which no DC offset was added at the voltage summer. FIG. 6.3(b) shows the voltage summer's output when there is a DC offset of 0.1 V introduced by its control voltage V~ .
The phase difference between the two multiplier inputs still keeps 90°
for the comparison.
The detector gain accompanying this multiplier is 60mV/rad, so the above DC
offsets should be adjusted accordingly.
Since the two DC offsets at the dual loop are the same, the current mirrors of the two voltage summers may be combined with only one control voltage, as shown in FIG. 6.4.
This configuration not only simplifies the circuitry for the DC offsets, but also eliminates the possible difference between the two DC offsets, which can result from resistance variation introduced during IC manufacturing.
There are two main topologies for a differential VCO; cross-coupled and differential Colpitts. The cross-coupled topology is preferred by designers due to its relatively good phase noise and ease of implementation.
FIG. 6.5 shows an exemplary complementary cross-coupled differential VCO based on MOSFETs and MOS varactors. Compared to the NMOS-only cross-coupled topology, this complementary version using both PMOS and NMOS can provide higher transconductance for a given current and lower noise due to its symmetric rise time and fall time on the output signal. A width ratio for two types of MOSFETs should be selected correctly in order to compensate for the speed discrepancy due to different mobility and threshold voltages of two transistors. Two transistors (one PMOS
at the top and one NMOS at the bottom) are used for the current bias, instead of only one NMOS
for this purpose in other works. This symmetric configuration can remove the DC
voltage applied to the varactors from the supplies in order to achieve direct varactor control with only a high value resistor Rv , as illustrated in FIG. 6.5;
otherwise it would require an extra DC offset for varactor control. The high value resistor R,, can provide isolation between the RF path and the external control circuit. As discussed previously, a large input signal is not suitable for the Gilbert multiplier, so maximal output from the VCO was not pursued in this embodiment. This simplifies other issues in the design of the VCO, such as requirements of output capacity, Q factor of the LC
oscillator and signal distortion.
A simulation circuit of this complementary differential VCO was built based on the 1.8V
models of transistors and MOSFET varactors in TSMC 0.18um CMOS. According to their parameters, the width ratio of PMOS and NMOS FETs was set to about 1.5.
A SnH
inductor with a Q factor of 6.7 was used in the LC oscillator, which is consistent with the parameters provided by the TSMC for their spiral inductors. The centre frequency of the LC oscillator was around l.SGHz. FIG. 6.6 shows the outputs and the VCO
frequency versus the control voltage in the simulations. The two outputs offset from each other with very small distortion and thus meet the requirement for the differential signal. The VCO linear tuning range was (1.31.9) GHz and its gain constant ko at zero control voltage was calculated to be ( 0.9 x 2~ ) Grad/sec/volt.
For a single PLL based on the above values of the detector gain kd and the VCO
gain constant ko , a loop filter with a cutoff frequency of 106MHz would be required to achieve the optimal loop damping factor (0.7). However, for a demodulator with a data rate lower than 106Mbps, it will need a voltage attenuator, such as a potentiometer, at the input of the VCO to lower the loop gain. Hence, the cutoff frequency of the loop filter can be decreased for the data filtering purpose without affecting the damping factor. For instance, if a loop filter with a l4MHz cutoff frequency is used at each loop for a data rate of l OMbps (GPS P-code uses 10.23Mbps), a potentiometer with a voltage ratio of 7.6 or (17.6dB loss) is required for the optimal damping factor. An attenuator with larger loss will be required if a lower data rate is used for this demodulator system. The third LPF at the input of VCO may also require a lower loop gain due to its effect on the cutoff frequency of the loop filter. This has been discussed previously.
As discussed previously, two N type MOSFETs in the symmetric configuration are suitable to implement the switches. The two offset control signals of these switches can come from a differential comparator. FIG. 6.7 gives an example design of the NMOS
switches and the differential comparator. The comparator contains a differential pair and two common-source amplifiers. In the comparator, the two inputs coming from the detector outputs are amplified to proper level for control of the switches.
The differential pair and the following two amplifiers may be biased to their threshold region to achieve high gain, and thus high sensitivity for the comparator. With the control of the switching signal from the comparator, the smaller voltage output (zero volt when locked) in the two outputs of the detectors are selected by the switches and applied to the VCO
before passing a LPF.
Simulations of this circuit based on TSMC 0.18 CMOS models are shown in FIGS
6.8(a)-FIG. 6.8(d). In these simulations, the inputs of the differential comparator were two offset pulses switching between 0 V and 40 mV, and the equivalent data rate was 1 OMbps. The amplitudes of the pulses were increased to between 0.1 V and 1.1 V by the comparator (FIG. 6.8(a)). The first waveform in FIG. 6.8(b) shows that the smaller voltage output {0V) in the two inputs was successfully picked out and presented at output of the NMOS switches, but with the spikes at the transitions of the input signals. As mentioned previously, these spikes are concerned with the smoothing operation of loop filters on the digital outputs of the detectors, and introducing a LPF after the switches can reduce the amplitude of these spikes and minimize their effect on the VCO. The spikes were significantly suppressed by an introduced LPF with a cutoff frequency 4.4MHz in the simulations; see the second waveform in FIG. 6.8(b).
Example: Mufti-band Communication System In a multiple-band communication system, a receiver should be able to work at all frequency channels with some extra frequency tuning elements. Receivers re-use most of their elements in mufti-band operations in order to simplify the circuitry and save cost.
The cost of expanding a system to a mufti-band system depends on how many elements need frequency tuning and how easy it is to implement this tuning.
As we can see in the IC designs of embodiments of the demodulator of the invention, only the VCO is highly dependent on the carrier frequency, which requires frequency tuning for mufti-band use. More specifically, only the centre frequency of the LC
oscillator in the VCO needs to be tuned. Thus a mufti-band BPSK demodulator system can be realized from the demodulator embodiments described herein. FIG. 6.9 gives a diagram of an example of a mufti-band demodulator. Compared to the single-band version, another voltage summer is introduced at the input of the VCO to tune the VCO
centre frequency accordingly. As simulated, the designed VCO has 1.3---1.9GHz linear tuning range, so there is 600MHz bandwidth available for the channels of the mufti-band system. More bandwidth may be realized if the system is implement several varactor networks and switches.
Summary As described above, BPSK demodulators according to the principles described herein have a compact structure and easily-implemented elements compared to prior designs, and thus are suitable for IC implementation. Moreover, a compact mufti-band demodulator may also be realized.
With easily-integrated characteristics, demodulators of the invention may be used in, for example, IhIMARSAT systems, GPS systems RFID systems and next-generation digital radio systems.
BER performance of the BPSK demodulators may be further improved by differential coding/decoding to overcome the problem of data inversion in the re-locking process caused by sporadic noise.
It will be understood by those skilled in the art that this description is made with reference to preferred embodiments and that it is possible to make other embodiments employing the principles of the invention which fall within its spirit and scope as defined by the following claims. For example, it is to be recognized that the IC
design topology described herein is an example only and other topologies could be created to implement the embodiments described herein, each such implementation falling within one or more of the following claims. Similarly, other embodiments could be created by persons skilled in the art based on the principles described herein, which embodiments can be implemented in one or more IC topologies. Such embodiments will also fall within the following claims.

Claims (19)

1. A BPSK demodulator for use with a BPSK signal, the demodulator comprising:
a first phase-locked loop for locking to the BPSK signal; and a second phase-locked loop for locking to the BPSK signal, which second phase-locked loop locks to the BPSK signal at a 180° phase difference from the first phase-locked loop;
wherein the first phase-locked loop and the second phase-locked loop are selected such that the first phase-locked loop is in lock at 0° and the second phase-locked loop is in lock at 180°.

2. The demodulator of claim 1 further comprising a selection network for selection of the first and second phase-locked loops.

3. The demodulator of claim 2 wherein the selection network comprises two switches, a comparator, and an inverter.

4. The demodulator of claim 1 wherein the first and second phase-locked loops each further comprise a multiplier and a voltage controlled oscillator.

5. The demodulator of claim 1 wherein the first and second phase-locked loops each further comprise a low pass filter and a summing circuit.

6. The demodulator of claim 1 wherein the first and second phase-locked loops are interconnnected to share a single voltage controlled oscillator.

7. The demodulator of claim 6 further comprising an automatic gain control circuit front end.

8. The demodulator of claim 2 wherein the selection network further comprises a low-pass filter.

9. The demodulator of claim 6 further comprising a voltage summer at the VCO front end.

10. The demodulator of claim 6 wherein the first and second phase-locked loops each further comprise an amplifier.

11. The demodulator of claim 6 wherein the first and second phase-locked loops each further comprise an attenuator.

12. The demodulator of claim 6 implemented in an integrated circuit.

13. The demodulator of claim 5 wherein a DC offset is introduced into the phase-locked loops by the summing circuit such that the phase-locked loops have different voltage outputs.

14. A method of demodulating a BPSK signal comprising:
providing a first phase-locked loop for locking to the BPSK signal;
providing a second phase-locked loop for locking to the BPSK
signal, which second phase-locked loop locks to the BPSK signal at a 180°
phase difference from the first phase-locked loop; and selecting the phase-locked loops such that the first phase-locked loop is in lock at 0° and the second phase-locked loop is in lock at 180°.

15. The method of claim 14 wherein selecting the phase-locked loops further comprises comparing the BPSK signal detected by each of the phase-locked loops to determine the phase of the BPSK signal.

16. The method of claim 15 wherein selecting the phase-locked loops further comprises opening and closing respective switches in accordance with the determined phase.

17. The method of claim 14 further comprising detecting the phase of the BPSK signal in each of the phase-locked loops by multiplying the BPSK
signal and a locking signal produced by a voltage controlled oscillator.

18. The method of claim 17 wherein detecting the phase further comprises passing the multiplied signal through a low pass filter and a summing circuit.

19. The method of claim 17 further comprising producing the locking signal for both detectors using a single voltage controlled oscillator.