CA2468800A1 - Systeme de calcul reconfigurable intensif a virgule flottante pour applications iteratives - Google Patents

Systeme de calcul reconfigurable intensif a virgule flottante pour applications iteratives Download PDF

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Publication number
CA2468800A1
CA2468800A1 CA002468800A CA2468800A CA2468800A1 CA 2468800 A1 CA2468800 A1 CA 2468800A1 CA 002468800 A CA002468800 A CA 002468800A CA 2468800 A CA2468800 A CA 2468800A CA 2468800 A1 CA2468800 A1 CA 2468800A1
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CA
Canada
Prior art keywords
instruction
floating point
computing system
processing elements
processing element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002468800A
Other languages
English (en)
Inventor
Shrirang Madhav Yardi
Thomas P. Kelliher
Benjamin Bishop
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
University of Georgia Research Foundation Inc UGARF
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Georgia Research Foundation Inc UGARF filed Critical University of Georgia Research Foundation Inc UGARF
Publication of CA2468800A1 publication Critical patent/CA2468800A1/fr
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

L'invention concerne un système de calcul reconfigurable permettant une exécution accélérée d'applications itératives intensives à virgule flottante. Ce système de calcul reconfigurable comprend une pluralité d'éléments de traitement interconnectés (20) montés, un système de traitement hôte permettant d'afficher des sorties en temps réel de calculs à virgule flottante effectués par les éléments de traitement (20), et une interface permettant de connecter les éléments de traitement au système hôte. Chacun des éléments de traitement interconnectés (20) comprend une unité fonctionnelle à virgule flottante (22), une mémoire d'opérande (24), une mémoire de commande (26) et une unité de commande (28). Ladite unité fonctionnelle à virgule flottante (22) comprend une fonction de multiplication/accumulation. Ladite mémoire d'opérande (24) comprend une pluralité de banques de mémoire RAM statique. Lesdits éléments de traitement (20) sont interconnectés au moyen d'une mise en oeuvre voisine ou hiérarchique la plus proche. Un ensemble d'instructions effectuées par ladite unité fonctionnelle à virgule flottante (22) comprend des instructions arithmétiques, ainsi que des instructions de commande et de communication. Ladite interface peut être mise en oeuvre en tant qu'interface de bus PCI au moyen d'un réseau de portes programmable par l'utilisateur ou en tant qu'interface de bus AGP.
CA002468800A 2001-12-06 2002-12-06 Systeme de calcul reconfigurable intensif a virgule flottante pour applications iteratives Abandoned CA2468800A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US33834701P 2001-12-06 2001-12-06
US60/338,347 2001-12-06
PCT/US2002/038645 WO2003050697A1 (fr) 2001-12-06 2002-12-06 Systeme de calcul reconfigurable intensif a virgule flottante pour applications iteratives

Publications (1)

Publication Number Publication Date
CA2468800A1 true CA2468800A1 (fr) 2003-06-19

Family

ID=23324454

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002468800A Abandoned CA2468800A1 (fr) 2001-12-06 2002-12-06 Systeme de calcul reconfigurable intensif a virgule flottante pour applications iteratives

Country Status (4)

Country Link
EP (1) EP1451701A1 (fr)
AU (1) AU2002360469A1 (fr)
CA (1) CA2468800A1 (fr)
WO (1) WO2003050697A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7840826B2 (en) 2007-05-31 2010-11-23 Vns Portfolio Llc Method and apparatus for using port communications to switch processor modes
CN113760817B (zh) * 2017-03-28 2024-05-24 上海山里智能科技有限公司 一种综合计算系统
CN118092853B (zh) * 2024-04-26 2024-07-19 中科亿海微电子科技（苏州）有限公司 基于risc-v浮点超越函数指令集扩展方法及装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5802290A (en) * 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US5892962A (en) * 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US6289434B1 (en) * 1997-02-28 2001-09-11 Cognigine Corporation Apparatus and method of implementing systems on silicon using dynamic-adaptive run-time reconfigurable circuits for processing multiple, independent data and control streams of varying rates
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6408382B1 (en) * 1999-10-21 2002-06-18 Bops, Inc. Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture

Also Published As

Publication number Publication date
WO2003050697A1 (fr) 2003-06-19
AU2002360469A1 (en) 2003-06-23
EP1451701A1 (fr) 2004-09-01

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Legal Events

Date Code Title Description
FZDE Discontinued