CA2367878A1 - Systeme de memoire vive dynamique ampic - Google Patents

Systeme de memoire vive dynamique ampic Download PDF

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Publication number
CA2367878A1
CA2367878A1 CA002367878A CA2367878A CA2367878A1 CA 2367878 A1 CA2367878 A1 CA 2367878A1 CA 002367878 A CA002367878 A CA 002367878A CA 2367878 A CA2367878 A CA 2367878A CA 2367878 A1 CA2367878 A1 CA 2367878A1
Authority
CA
Canada
Prior art keywords
data
resource
ampic
stale
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002367878A
Other languages
English (en)
Inventor
Richard F. Conlin
Douglas E. Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nexabit Networks Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2367878A1 publication Critical patent/CA2367878A1/fr
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)

Abstract

L'invention concerne un appareil et un procédé destinés à améliorer la performance d'une mémoire vive dynamique interne multi-ports mise en antémémoire (AMPIC DRAM) et analogue au moyen d'une technique interne de validation de données à l'intérieur des mémoires AMPIC afin de garantir que seules les données demandées valides en sont renvoyées, ou des données non valables correctement étiquetées. L'invention concerne également une technique d'identification de données erronées lues à partir de dispositifs de mémoire AMPIC dans le système.
CA002367878A 1999-03-26 1999-03-26 Systeme de memoire vive dynamique ampic Abandoned CA2367878A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB1999/000529 WO2000058840A1 (fr) 1999-03-26 1999-03-26 Systeme de memoire vive dynamique ampic

Publications (1)

Publication Number Publication Date
CA2367878A1 true CA2367878A1 (fr) 2000-10-05

Family

ID=11004838

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002367878A Abandoned CA2367878A1 (fr) 1999-03-26 1999-03-26 Systeme de memoire vive dynamique ampic

Country Status (4)

Country Link
EP (1) EP1204925A1 (fr)
AU (1) AU2742999A (fr)
CA (1) CA2367878A1 (fr)
WO (1) WO2000058840A1 (fr)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5655103A (en) * 1995-02-13 1997-08-05 International Business Machines Corporation System and method for handling stale data in a multiprocessor system
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration

Also Published As

Publication number Publication date
AU2742999A (en) 2000-10-16
EP1204925A1 (fr) 2002-05-15
WO2000058840A1 (fr) 2000-10-05

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