CA2319239A1 - Multi-port random access memory - Google Patents

Multi-port random access memory Download PDF

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Publication number
CA2319239A1
CA2319239A1 CA002319239A CA2319239A CA2319239A1 CA 2319239 A1 CA2319239 A1 CA 2319239A1 CA 002319239 A CA002319239 A CA 002319239A CA 2319239 A CA2319239 A CA 2319239A CA 2319239 A1 CA2319239 A1 CA 2319239A1
Authority
CA
Canada
Prior art keywords
port
random access
read
ram
access memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002319239A
Other languages
French (fr)
Other versions
CA2319239C (en
Inventor
Garnet Frederic Randall Gibson
Steven William Wood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/565,267 external-priority patent/US5561638A/en
Priority claimed from US08/644,081 external-priority patent/US5612923A/en
Application filed by Individual filed Critical Individual
Priority claimed from CA 2176675 external-priority patent/CA2176675C/en
Publication of CA2319239A1 publication Critical patent/CA2319239A1/en
Application granted granted Critical
Publication of CA2319239C publication Critical patent/CA2319239C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Static Random-Access Memory (AREA)

Abstract

A multi-port RAM (random access memory) including an array of RAM cells. Each RAM cell has a core cell with a single-ended, pseudo-differential write access port and differential, indirect access read ports.
The architecture of the features of the mufti-port RAM allows direct scaling of the number of write and read access ports to any practical limit with no adverse effects on cell stability margins and therefore data integrity. Also, disclosed is a design detail for an innovative time multiplexed read port architecture implemented as part of a high-speed 9-port time slot interchange random access memory. It provides a practical, high-speed, low-power and area efficient read port structure to allow eight random access reads per clock cycle. Because all timing is internally generated from a single rising clock transition of a system clock signal, no special control or clocking is required externally to the memory.
CA002319239A 1995-07-27 1996-05-15 Multi-port random access memory Expired - Fee Related CA2319239C (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US157895P 1995-07-27 1995-07-27
US60/001,578 1995-07-27
US185695P 1995-08-03 1995-08-03
US60/001,856 1995-08-03
US08/565,267 US5561638A (en) 1995-11-30 1995-11-30 Multi-port SRAM core array
US08/565,267 1995-11-30
US08/644,081 US5612923A (en) 1996-05-09 1996-05-09 Multi-port random access memory
US08/644,081 1996-05-09
CA 2176675 CA2176675C (en) 1995-07-27 1996-05-15 Multi-port random access memory

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CA 2176675 Division CA2176675C (en) 1995-07-27 1996-05-15 Multi-port random access memory

Publications (2)

Publication Number Publication Date
CA2319239A1 true CA2319239A1 (en) 1997-01-28
CA2319239C CA2319239C (en) 2004-03-30

Family

ID=27508595

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002319239A Expired - Fee Related CA2319239C (en) 1995-07-27 1996-05-15 Multi-port random access memory

Country Status (1)

Country Link
CA (1) CA2319239C (en)

Also Published As

Publication number Publication date
CA2319239C (en) 2004-03-30

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