CA2316443A1 - Synchronisation par cartographie d'un signal module .delta.-. sigma. a sautillement de deplacement de frequences - Google Patents
Synchronisation par cartographie d'un signal module .delta.-. sigma. a sautillement de deplacement de frequences Download PDFInfo
- Publication number
- CA2316443A1 CA2316443A1 CA 2316443 CA2316443A CA2316443A1 CA 2316443 A1 CA2316443 A1 CA 2316443A1 CA 2316443 CA2316443 CA 2316443 CA 2316443 A CA2316443 A CA 2316443A CA 2316443 A1 CA2316443 A1 CA 2316443A1
- Authority
- CA
- Canada
- Prior art keywords
- input
- output
- delta
- sigma
- modulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
- H03M7/3033—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
- H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
- H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Time-Division Multiplex Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA 2316443 CA2316443A1 (fr) | 2000-08-21 | 2000-08-21 | Synchronisation par cartographie d'un signal module .delta.-. sigma. a sautillement de deplacement de frequences |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA 2316443 CA2316443A1 (fr) | 2000-08-21 | 2000-08-21 | Synchronisation par cartographie d'un signal module .delta.-. sigma. a sautillement de deplacement de frequences |
Publications (1)
Publication Number | Publication Date |
---|---|
CA2316443A1 true CA2316443A1 (fr) | 2002-02-21 |
Family
ID=4166927
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA 2316443 Abandoned CA2316443A1 (fr) | 2000-08-21 | 2000-08-21 | Synchronisation par cartographie d'un signal module .delta.-. sigma. a sautillement de deplacement de frequences |
Country Status (1)
Country | Link |
---|---|
CA (1) | CA2316443A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7298808B1 (en) | 2003-04-29 | 2007-11-20 | Pmc-Sierra, Inc. | Cascaded jitter frequency shifting Δ-Σ modulated signal synchronization mapper |
-
2000
- 2000-08-21 CA CA 2316443 patent/CA2316443A1/fr not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7298808B1 (en) | 2003-04-29 | 2007-11-20 | Pmc-Sierra, Inc. | Cascaded jitter frequency shifting Δ-Σ modulated signal synchronization mapper |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0248551B1 (fr) | Synchronisation de signaux de données asynchrones | |
EP1811670B1 (fr) | Oscillateur contrôlé numériquement et procédé pour établir une horloge d'évènement | |
EP0626117B1 (fr) | Desynchronisateur et procede pour supprimer le sautillement de l'indicateur dans un desynchronisateur | |
EP0732015A1 (fr) | Appareil et procede pour l'elimination des sautillements de mappage | |
US4771426A (en) | Isochronous clock reconstruction | |
US5276688A (en) | Circuit arrangement for bit rate adjustment | |
US6819725B1 (en) | Jitter frequency shifting Δ-Σ modulated signal synchronization mapper | |
US5737373A (en) | Control method and apparatus for suppressing jitter | |
US7702946B2 (en) | Digital clock filter circuit for a gapped clock of a non-isochronous data signal having a selected one of at least two nominal data rates | |
US7298808B1 (en) | Cascaded jitter frequency shifting Δ-Σ modulated signal synchronization mapper | |
US5768328A (en) | Method and a receiver circuit for desynchronization in a digital transmission system | |
CA2316443A1 (fr) | Synchronisation par cartographie d'un signal module .delta.-. sigma. a sautillement de deplacement de frequences | |
US7440533B2 (en) | Modulated jitter attenuation filter | |
KR0184916B1 (ko) | 완전한 2차 디지탈 위상 동기 루프 및 그것을 이용한 디스터핑 회로 | |
EP0941589B1 (fr) | Procede et circuit pour produire un signal d'horloge de systeme | |
SE518361C2 (sv) | Dämpning av pekarjitter i en desynkronisator | |
EP1034632B1 (fr) | Procede de transfert de signaux de donnees ainsi que procede et appareil de desynchronisation de signaux pdh | |
JP3313318B2 (ja) | Pll回路 | |
EP0947050B1 (fr) | Boucle numerique a phase asservie et son procede de commande, et procede et circuit de reception pour desynchronisation dans un systeme de transmission numerique | |
JP2840569B2 (ja) | 局間クロック同期回路 | |
US5581493A (en) | Device for filtering positive dejustification jitter of a digital bit stream and application thereof to filtering positive and positive-negative dejustification jitter of a digital bit stream | |
US20020025014A1 (en) | Jitter reducing apparatus using digital modulation technique | |
EP0943193B1 (fr) | Procede et circuit pour produire un signal d'horloge central | |
EP0522797A2 (fr) | Désynchroniseur de signaux numériques synchrones vers des signaux numériques asynchrones | |
KR100297854B1 (ko) | 위상 동기 루프의 발진기 제어용 d/a 변환기_ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
FZDE | Dead |