CA2312355A1 - Method and device for testing digital protection devices - Google Patents
Method and device for testing digital protection devices Download PDFInfo
- Publication number
- CA2312355A1 CA2312355A1 CA002312355A CA2312355A CA2312355A1 CA 2312355 A1 CA2312355 A1 CA 2312355A1 CA 002312355 A CA002312355 A CA 002312355A CA 2312355 A CA2312355 A CA 2312355A CA 2312355 A1 CA2312355 A1 CA 2312355A1
- Authority
- CA
- Canada
- Prior art keywords
- buffered
- signals
- data processing
- protection devices
- digital current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/04—Details with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned
- H02H3/044—Checking correct functioning of protective arrangements, e.g. by simulating a fault
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Emergency Protection Circuit Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to a method and configuration for testing digital protection devices in which a data processing energy supply network is emulated by means of pulsed output of digital current and voltage signals.
To this end, utilizing one such method, corresponding currents and voltages are constructed and supplied to a protection device which is to be tested. In order to test protection devices as realistically as possible with comparatively simple data processing equipment, the fetched out digital current and voltage signals (J', U') are first buffered in succession at the beginning of the testing of the protection device (6). After achieving a predetermined consistency of the buffered signals (I z, U z), the respective oldest buffered signals (I z, U z) are read out in a clock-pulse manner and most recent fetched out signals (J', U') are buffered. In the occurrence of a tripping signal, reading out is continued in a pulsed manner and data processing network specific digital current and voltage signals are fetched out and buffered.
To this end, utilizing one such method, corresponding currents and voltages are constructed and supplied to a protection device which is to be tested. In order to test protection devices as realistically as possible with comparatively simple data processing equipment, the fetched out digital current and voltage signals (J', U') are first buffered in succession at the beginning of the testing of the protection device (6). After achieving a predetermined consistency of the buffered signals (I z, U z), the respective oldest buffered signals (I z, U z) are read out in a clock-pulse manner and most recent fetched out signals (J', U') are buffered. In the occurrence of a tripping signal, reading out is continued in a pulsed manner and data processing network specific digital current and voltage signals are fetched out and buffered.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19740425A DE19740425A1 (en) | 1997-09-10 | 1997-09-10 | Method and arrangement for testing digital protection devices |
DE19740425.1 | 1997-09-10 | ||
PCT/DE1998/002692 WO1999013350A1 (en) | 1997-09-10 | 1998-09-04 | Method and configuration for testing digital protection devices |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2312355A1 true CA2312355A1 (en) | 1999-03-18 |
CA2312355C CA2312355C (en) | 2007-11-06 |
Family
ID=7842332
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002312355A Expired - Fee Related CA2312355C (en) | 1997-09-10 | 1998-09-04 | Method and device for testing digital protection devices |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1012616B1 (en) |
AT (1) | ATE216781T1 (en) |
CA (1) | CA2312355C (en) |
DE (2) | DE19740425A1 (en) |
WO (1) | WO1999013350A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107947742B (en) * | 2017-12-11 | 2021-07-02 | 湖南时变通讯科技有限公司 | Time sequence protection circuit for controlling depletion type power device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DD150947A1 (en) * | 1980-05-19 | 1981-09-23 | Heinz Clemens | METHOD FOR COMPUTER-ASSISTED PROTECTION RELAY TESTING WITH CONTROLLABLE POWER SUPPLY BENCHMARKS |
JPH05111141A (en) * | 1991-10-15 | 1993-04-30 | Tokyo Gas Co Ltd | Relay testing device |
-
1997
- 1997-09-10 DE DE19740425A patent/DE19740425A1/en not_active Withdrawn
-
1998
- 1998-09-04 DE DE59803930T patent/DE59803930D1/en not_active Expired - Fee Related
- 1998-09-04 AT AT98954163T patent/ATE216781T1/en not_active IP Right Cessation
- 1998-09-04 EP EP98954163A patent/EP1012616B1/en not_active Expired - Lifetime
- 1998-09-04 CA CA002312355A patent/CA2312355C/en not_active Expired - Fee Related
- 1998-09-04 WO PCT/DE1998/002692 patent/WO1999013350A1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
WO1999013350A1 (en) | 1999-03-18 |
CA2312355C (en) | 2007-11-06 |
EP1012616B1 (en) | 2002-04-24 |
EP1012616A1 (en) | 2000-06-28 |
DE19740425A1 (en) | 1999-03-11 |
ATE216781T1 (en) | 2002-05-15 |
DE59803930D1 (en) | 2002-05-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |