CA2312355A1 - Method and device for testing digital protection devices - Google Patents

Method and device for testing digital protection devices Download PDF

Info

Publication number
CA2312355A1
CA2312355A1 CA002312355A CA2312355A CA2312355A1 CA 2312355 A1 CA2312355 A1 CA 2312355A1 CA 002312355 A CA002312355 A CA 002312355A CA 2312355 A CA2312355 A CA 2312355A CA 2312355 A1 CA2312355 A1 CA 2312355A1
Authority
CA
Canada
Prior art keywords
buffered
signals
data processing
protection devices
digital current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002312355A
Other languages
French (fr)
Other versions
CA2312355C (en
Inventor
Steffen Kaiser
Wilhelm Winter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens Aktiengesellschaft
Steffen Kaiser
Wilhelm Winter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft, Steffen Kaiser, Wilhelm Winter filed Critical Siemens Aktiengesellschaft
Publication of CA2312355A1 publication Critical patent/CA2312355A1/en
Application granted granted Critical
Publication of CA2312355C publication Critical patent/CA2312355C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/273Tester hardware, i.e. output processing circuits
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02Details
    • H02H3/04Details with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned
    • H02H3/044Checking correct functioning of protective arrangements, e.g. by simulating a fault

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to a method and configuration for testing digital protection devices in which a data processing energy supply network is emulated by means of pulsed output of digital current and voltage signals.
To this end, utilizing one such method, corresponding currents and voltages are constructed and supplied to a protection device which is to be tested. In order to test protection devices as realistically as possible with comparatively simple data processing equipment, the fetched out digital current and voltage signals (J', U') are first buffered in succession at the beginning of the testing of the protection device (6). After achieving a predetermined consistency of the buffered signals (I z, U z), the respective oldest buffered signals (I z, U z) are read out in a clock-pulse manner and most recent fetched out signals (J', U') are buffered. In the occurrence of a tripping signal, reading out is continued in a pulsed manner and data processing network specific digital current and voltage signals are fetched out and buffered.
CA002312355A 1997-09-10 1998-09-04 Method and device for testing digital protection devices Expired - Fee Related CA2312355C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19740425A DE19740425A1 (en) 1997-09-10 1997-09-10 Method and arrangement for testing digital protection devices
DE19740425.1 1997-09-10
PCT/DE1998/002692 WO1999013350A1 (en) 1997-09-10 1998-09-04 Method and configuration for testing digital protection devices

Publications (2)

Publication Number Publication Date
CA2312355A1 true CA2312355A1 (en) 1999-03-18
CA2312355C CA2312355C (en) 2007-11-06

Family

ID=7842332

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002312355A Expired - Fee Related CA2312355C (en) 1997-09-10 1998-09-04 Method and device for testing digital protection devices

Country Status (5)

Country Link
EP (1) EP1012616B1 (en)
AT (1) ATE216781T1 (en)
CA (1) CA2312355C (en)
DE (2) DE19740425A1 (en)
WO (1) WO1999013350A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107947742B (en) * 2017-12-11 2021-07-02 湖南时变通讯科技有限公司 Time sequence protection circuit for controlling depletion type power device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD150947A1 (en) * 1980-05-19 1981-09-23 Heinz Clemens METHOD FOR COMPUTER-ASSISTED PROTECTION RELAY TESTING WITH CONTROLLABLE POWER SUPPLY BENCHMARKS
JPH05111141A (en) * 1991-10-15 1993-04-30 Tokyo Gas Co Ltd Relay testing device

Also Published As

Publication number Publication date
WO1999013350A1 (en) 1999-03-18
CA2312355C (en) 2007-11-06
EP1012616B1 (en) 2002-04-24
EP1012616A1 (en) 2000-06-28
DE19740425A1 (en) 1999-03-11
ATE216781T1 (en) 2002-05-15
DE59803930D1 (en) 2002-05-29

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