CA2311888A1 - Automatic data transmission rate-controlling device and method for prevention of generation of an overflow in ethernet switch - Google Patents
Automatic data transmission rate-controlling device and method for prevention of generation of an overflow in ethernet switch Download PDFInfo
- Publication number
- CA2311888A1 CA2311888A1 CA002311888A CA2311888A CA2311888A1 CA 2311888 A1 CA2311888 A1 CA 2311888A1 CA 002311888 A CA002311888 A CA 002311888A CA 2311888 A CA2311888 A CA 2311888A CA 2311888 A1 CA2311888 A1 CA 2311888A1
- Authority
- CA
- Canada
- Prior art keywords
- transmission rate
- data
- ethernet switch
- external terminal
- terminal unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9084—Reactions to storage capacity overflow
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Small-Scale Networks (AREA)
Abstract
Disclosed is a device of automatically controlling a data transmission rate for preventing a generation of an overflow in an Ethernet switch having a pair of ports each supporting a variety of transmission rates, comprising: one or more line interface logic circuits coupled to an external terminal unit, through one of the pair of ports, adapted to automatically set a transmission rate of the external terminal unit coupled to one of the pair of ports to a predetermined one of the transmission rates supported by the Ethernet switch, and adapted to interface data transmitted between the external terminal unit and the Ethernet switch; a line transmission rate controller coupled to the one or more line interface logic circuits, adapted to generate a control signal for reducing the transmission rate of data inputted to the Ethernet switch from the external terminal unit for application to the line interface logic circuit upon generation of an overflow within the Ethernet switch due to congestion of the inputted data, the transmission rate of the inputted data being reduced in such a fashion that it corresponds to a transmission rate at which the data is outputted from the Ethernet switch; and a buffer memory coupled to the line transmission rate controller, adapted to temporarily store data transmitted through the line interface logic circuit therein depending on the control of the line transmission rate controller. The Ethernet switch supporting a variety of transmission rates of the present invention provides advantages that the transmission rate of the input port is automatically controlled to correspond to that of the output port, thereby preventing loss of data due to generation of an overflow over a data transmission path, and reduction of data throughput in an entire communication network.
Description
P8906/STN (23728/1999) AUTOMATIC DATA TRANSMISSION RATE-CONTROLLING
DEVICE AND METHOD FOR PREVENTION OF GENERATION OF AN
OVERFLOW IN ETHERNET SWITCH
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to Ethernet switches, and more particularly to a device and method of automatically controlling a data transmission rate for preventing a generation of an overflow in Ethernet switches.
DEVICE AND METHOD FOR PREVENTION OF GENERATION OF AN
OVERFLOW IN ETHERNET SWITCH
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to Ethernet switches, and more particularly to a device and method of automatically controlling a data transmission rate for preventing a generation of an overflow in Ethernet switches.
2. Description of the Related Art Fig. 1 is a schematic block diagram illustrating the construction of a conventional Ethernet network system. In the Ethernet network system, Ethernet switches 102 and 104 may be one of 100Base-T of IEEE 802.3u and 1000Base-T of IEEE 802.3ab, respectively. The Ethernet switches 102 and 104 support a line the identical port of which has various transmission rates. Thus, an Ethernet switch 1 S device may include ports having a data transmission rate of up to 10 Mbps, 100 Mbps, 1000Mbps or 1 Gbps. Generally, the Ethernet switch 102 is provided with a line of a lower transmission rate coupled to an external terminal such as a personal computer (PC) 100, and a line of a higher transmission rate coupled to a server (not shown) or the other Ethernet switch 104.
At this time, communication between ports having the same transmission rate, i.e., communication between a port of 10 Mbps and a port of 10 Mbps, and P8906/STN (23728/1999) communication between a port of 100 Mbps and a port of 100 Mbps do not permit data congestion to be generated except for a special case, like a case in which data is transmitted from several input ports to one output port, such as a port aggregation, etc.
However, there has been a problem, in that, when data is transmitted from the port of 100 Mbps to the port of 10 Mbps, or from the port of 1000 Mbps to the port of 100 Mbps, a generation of an overflow due to the data congestion causes inevitable accumulation of data in the Ethernet switch.
That is, for example, if a transmission rate in a connection line between ports of the external terminal, i.e., PC 100 and the Ethernet switch 102 is 100 Mbps, and that in a connection line between ports of the Ethernet switches 102 and 104 is 10 Mbps, data continuously transmitted, at the transmission rate of 100 Mbps from the PC 100 to the Ethernet switch 102 always are accumulated in the Ethernet switch 102. At this time, in the case that the Ethernet switch 102 employs a shared buffer, this affects directly other ports of the Ethernet switch 102, thereby steeply reducing data throughput in an entire communication network.
SUMMARY OF THE INVENTION
Therefore, an object of the invention is to provide a device and method of automatically controlling a data transmission rate for preventing a generation of an overflow in Ethernet switches.
In accordance with one embodiment of the present invention, this object is accomplished by providing a device of automatically controlling a data transmission rate for preventing a generation of an overflow in an Ethernet switch having a pair of ports each supporting a variety of transmission rates, comprising:
P8906/STN (23728/1999) at least one line interface logic circuit coupled to an external terminal unit, through one of the pair of ports, adapted to automatically set a transmission rate of the external terminal unit coupled to one of the pair of ports to a predetermined one of the S transmission rates supported by the Ethernet switch, and adapted to interface data transmitted between the external terminal unit and the Ethernet switch;
a line transmission rate controller coupled to the at least one line interface logic circuit, adapted to generate a control signal for reducing the transmission rate of data inputted to the Ethernet switch from the external terminal unit for application to the line interface logic circuit upon generation of an overflow within the Ethernet switch due to congestion of the inputted data, the transmission rate of the inputted data being reduced in such a fashion that it corresponds to a transmission rate at which the data are outputted from the Ethernet switch; and a buffer memory coupled to the line transmission rate controller, adapted to temporarily store data transmitted through the line interface therein depending on the control of the line transmission rate controller.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:
Fig. 1 is a schematic block diagram illustrating the construction of an Ethernet network system according to a prior art;
Fig. 2 is a block diagram illustrating the construction of an automatic transmission rate-controlling device according to a preferred embodiment of the present invention; and P8906/STN (23728/1999) Fig. 3 is a flowchart illustrating the process of implementing an automatic transmission rate controlling operation according to a preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
S Reference will now be made in greater detail to the preferred embodiments of the present invention. In the following description of the present invention, numerous specific details, such as concrete process routines, are set forth to provide a more thorough understanding of the present invention. It will be apparent, however, to those skilled in the art that the invention may be practiced otherwise than according to the previously mentioned specific details. The detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.
Fig. 2 is a block diagram illustrating the inner construction of an automatic transmission rate-controlling device of an Ethernet switch according to a preferred embodiment of the present invention.
Refernng to Fig. 2, the automatic transmission rate-controlling device is illustrated, which includes a plurality of line interface logic circuits 200 to 202, a line transmission rate controller 204, and a buffer 206.
The line interface logic circuit 202 is a physical layer section, which is adapted to connect an external terminal unit such as PC 100 and an Ethernet switch 102. The Ethernet switch 102 has a pair of ports "A" and "B" each supporting a variety of transmission rates. The line interface logic circuit 202 is also coupled to each of the P8906/STN (23728/1999) pair of ports "A" and "B", and performs communication together with the external terminal unit 100 coupled to each of the ports "A" and "B". During the communication between the line interface logic circuit 202 and the external terminal unit 100, the line interface logic circuit 202 regulates automatically a transmission rate of data inputted from the external terminal unit 100 to the Ethernet switch 102, and writes the set transmission rate in a register therein. That is, because the Ethernet switch 102 is designed in such a fashion that each of the ports supports all the transmission rates of lOMbps/100Mbps, the transmission rate of the external terminal unit coupled to each of the ports should be automatically controlled to correspond to a predetermined one of the transmission rates supported by the Ethernet switch 102.
The line interface logic circuit 202 controls automatically a transmission rate of data inputted from the external terminal unit 100 to the Ethernet switch 102 in such a fashion that the transmission rate of the external terminal unit 100 corresponds to the transmission rate supported by the Ethernet switch 102 by using an automatic transmission rate-setting function.
The line transmission rate controller 204 receives packet data inputted from the external terminal unit 100 to the line interface logic circuit through each of the ports, stores temporarily the packet data in the buffer 206 through a predetermined data processing operation, and transmits the packet data read-out from the buffer 206 to an associated port. Also, the line transmission rate controller 204 evaluates a transmission rate of data inputted/outputted to/from the buffer 206. If a transmission rate of data inputted to the buffer 206 is higher than that of data outputted from the buffer 206 so that congestion of data causes an overflow within the Ethernet switch, the line transmission rate controller 204 controls the line interface logic circuit 200 to reduce the transmission rate of data inputted from the external terminal unit 100 to the line interface logic circuit 200 in such a fashion that the transmission rate of the P8906/STN (23728/1999) inputted data corresponds to a transmission rate at which the data are outputted from the Ethernet switch.
Figs. 3 is a flowchart illustrating the process of implementing an automatic transmission rate-controlling operation upon generation of an overflow within the Ethernet switch due to congestion of data inputted to a line interface logic circuit according to a preferred embodiment of the present invention.
The automatic transmission rate-controlling operation according to a preferred embodiment of the present invention will be described in detail hereinafter with reference to Fig. 2 and 3.
In the description of a preferred embodiment of the present invention, for the purpose of its convenience, suppose that a transmission rate of data inputted from the external terminal unit 100 to the line interface logic circuit 202 through an input port A
is 100Mbps and that of data outputted to other Ethernet switch 104 from the line interface logic circuit 204 through an output port B is l OMbps.
First, at step 300, if the external terminal unit such as PC 100 is connected to the Ethernet switch 102 through the input port "A", the line transmission rate controller 204 allows an activated bit of an automatic transmission rate-setting function of a PHY control register included in the line interface logic circuit 202 to be set to a logic "high", i.e., a logic value of "1 ", and sets an optimum transmission rate for transmitting data between the external terminal unit 100 and the Ethernet switch 102 by using the automatic transmission rate-setting function of the line interface logic circuit 202. That is, as described in an embodiment of the present invention, if the port "A" is a port of a combined lOMbps/100Mbps and the external terminal unit P8906/STN (23728/1999) is also a port of a combined lOMbps/100Mbps, the line interface logic circuit 200 sets the transmission rate to 100Mbps depending on the automatic transmission rate-setting function. Accordingly, data is transmitted from the external terminal unit 100 to the Ethernet switch 102 through the port "A" at the set transmission rate. And then, the S program proceeds to subsequent step 302 at which the line transmission rate controller 204 determines whether or not the line interface logic circuit 200 receives the data transmitted from the external terminal unit 100 through the port "A". If it is determined at step 302 that the data is received from the external terminal unit 200, the program proceeds to step 304 where the line transmission rate controller 204 stores temporarily the received data in the buffer 206. At subsequent step 306, the line transmission rate controller 204 allows the data stored in the buffer 206 to be read-out and transmitted to an associated destination node through the port "B". And then, at next step 308, the line transmission rate controller 204 determines whether or not there is generated an overflow due to data congestion. As described above, in the case that the Ethernet switch is a switch employing a shared buffer, the overflow is an undesirable phenomenon which affects directly other ports of the Ethernet switch 102 so that data throughput is reduced steeply in an entire communication network.
In other words, if the transmission rate of data inputted to the Ethernet switch 102 from the external terminal 100 is higher than that of data outputted from the Ethernet switch 102, the just inputted data is not outputted to the associated destination node, but is accumulated in the buffer 206 of the Ethernet switch 102. As a result, the line transmission rate controller 204 monitors data stream over a data transmission path and compares the transmission rate of the inputted data with the transmission rate of the outputted data to determine if there is generated an overflow owing to data congestion.
If it is determined at the step 308 that there is not generated the overflow, the _ g _ P8906/S1'N (23728/1999) program returns to the previous step 302 where the line transmission rate controller 204 performs the following steps 302 through 308 again. If, on the other hand, it is determined at step 308 that there is generated an overflow, the program proceeds to step 310 at which the line transmission rate controller 204 generates a control signal for reducing the transmission rate of data inputted to the Ethernet switch 102 from the external terminal unit 100 for application to the line interface logic circuit 200. The transmission rate of the inputted data is reduced in such a fashion that it corresponds to a transmission rate at which the data is outputted from the Ethernet switch 102. That is, the line interface logic circuit 200 allows a bit value of a transmission rate of the PHY control register therein to be set to a logic "low", i.e., a logic value of "0"
according to the control signal, and an activated bit of the automatic transmission rate-setting function is also set to a logic value of "0" so that the transmission rate of the inputted data is reduced to lOMbps. As a result, the program proceeds to step 312 at which the line interface logic circuit 200 executes the transmission rate-reducing operation according to the control signal so that the transmission rate of the input port "A" set between the external terminal unit 100 and the Ethernet switch 102 is controlled to correspond to that of the output port "B".
As described above, the Ethernet switch supporting a variety of transmission rates of the present invention provides advantages that the transmission rate of the input port is automatically controlled to correspond to that of the output port, thereby preventing loss of data due to generation of an overflow over a data transmission path, and reduction of data throughput in an entire communication network.
While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment, but, on the contrary, it is P8906/STN (23728/1999) intended to cover various modifications within the spirit and scope of the appended claims.
At this time, communication between ports having the same transmission rate, i.e., communication between a port of 10 Mbps and a port of 10 Mbps, and P8906/STN (23728/1999) communication between a port of 100 Mbps and a port of 100 Mbps do not permit data congestion to be generated except for a special case, like a case in which data is transmitted from several input ports to one output port, such as a port aggregation, etc.
However, there has been a problem, in that, when data is transmitted from the port of 100 Mbps to the port of 10 Mbps, or from the port of 1000 Mbps to the port of 100 Mbps, a generation of an overflow due to the data congestion causes inevitable accumulation of data in the Ethernet switch.
That is, for example, if a transmission rate in a connection line between ports of the external terminal, i.e., PC 100 and the Ethernet switch 102 is 100 Mbps, and that in a connection line between ports of the Ethernet switches 102 and 104 is 10 Mbps, data continuously transmitted, at the transmission rate of 100 Mbps from the PC 100 to the Ethernet switch 102 always are accumulated in the Ethernet switch 102. At this time, in the case that the Ethernet switch 102 employs a shared buffer, this affects directly other ports of the Ethernet switch 102, thereby steeply reducing data throughput in an entire communication network.
SUMMARY OF THE INVENTION
Therefore, an object of the invention is to provide a device and method of automatically controlling a data transmission rate for preventing a generation of an overflow in Ethernet switches.
In accordance with one embodiment of the present invention, this object is accomplished by providing a device of automatically controlling a data transmission rate for preventing a generation of an overflow in an Ethernet switch having a pair of ports each supporting a variety of transmission rates, comprising:
P8906/STN (23728/1999) at least one line interface logic circuit coupled to an external terminal unit, through one of the pair of ports, adapted to automatically set a transmission rate of the external terminal unit coupled to one of the pair of ports to a predetermined one of the S transmission rates supported by the Ethernet switch, and adapted to interface data transmitted between the external terminal unit and the Ethernet switch;
a line transmission rate controller coupled to the at least one line interface logic circuit, adapted to generate a control signal for reducing the transmission rate of data inputted to the Ethernet switch from the external terminal unit for application to the line interface logic circuit upon generation of an overflow within the Ethernet switch due to congestion of the inputted data, the transmission rate of the inputted data being reduced in such a fashion that it corresponds to a transmission rate at which the data are outputted from the Ethernet switch; and a buffer memory coupled to the line transmission rate controller, adapted to temporarily store data transmitted through the line interface therein depending on the control of the line transmission rate controller.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:
Fig. 1 is a schematic block diagram illustrating the construction of an Ethernet network system according to a prior art;
Fig. 2 is a block diagram illustrating the construction of an automatic transmission rate-controlling device according to a preferred embodiment of the present invention; and P8906/STN (23728/1999) Fig. 3 is a flowchart illustrating the process of implementing an automatic transmission rate controlling operation according to a preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
S Reference will now be made in greater detail to the preferred embodiments of the present invention. In the following description of the present invention, numerous specific details, such as concrete process routines, are set forth to provide a more thorough understanding of the present invention. It will be apparent, however, to those skilled in the art that the invention may be practiced otherwise than according to the previously mentioned specific details. The detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.
Fig. 2 is a block diagram illustrating the inner construction of an automatic transmission rate-controlling device of an Ethernet switch according to a preferred embodiment of the present invention.
Refernng to Fig. 2, the automatic transmission rate-controlling device is illustrated, which includes a plurality of line interface logic circuits 200 to 202, a line transmission rate controller 204, and a buffer 206.
The line interface logic circuit 202 is a physical layer section, which is adapted to connect an external terminal unit such as PC 100 and an Ethernet switch 102. The Ethernet switch 102 has a pair of ports "A" and "B" each supporting a variety of transmission rates. The line interface logic circuit 202 is also coupled to each of the P8906/STN (23728/1999) pair of ports "A" and "B", and performs communication together with the external terminal unit 100 coupled to each of the ports "A" and "B". During the communication between the line interface logic circuit 202 and the external terminal unit 100, the line interface logic circuit 202 regulates automatically a transmission rate of data inputted from the external terminal unit 100 to the Ethernet switch 102, and writes the set transmission rate in a register therein. That is, because the Ethernet switch 102 is designed in such a fashion that each of the ports supports all the transmission rates of lOMbps/100Mbps, the transmission rate of the external terminal unit coupled to each of the ports should be automatically controlled to correspond to a predetermined one of the transmission rates supported by the Ethernet switch 102.
The line interface logic circuit 202 controls automatically a transmission rate of data inputted from the external terminal unit 100 to the Ethernet switch 102 in such a fashion that the transmission rate of the external terminal unit 100 corresponds to the transmission rate supported by the Ethernet switch 102 by using an automatic transmission rate-setting function.
The line transmission rate controller 204 receives packet data inputted from the external terminal unit 100 to the line interface logic circuit through each of the ports, stores temporarily the packet data in the buffer 206 through a predetermined data processing operation, and transmits the packet data read-out from the buffer 206 to an associated port. Also, the line transmission rate controller 204 evaluates a transmission rate of data inputted/outputted to/from the buffer 206. If a transmission rate of data inputted to the buffer 206 is higher than that of data outputted from the buffer 206 so that congestion of data causes an overflow within the Ethernet switch, the line transmission rate controller 204 controls the line interface logic circuit 200 to reduce the transmission rate of data inputted from the external terminal unit 100 to the line interface logic circuit 200 in such a fashion that the transmission rate of the P8906/STN (23728/1999) inputted data corresponds to a transmission rate at which the data are outputted from the Ethernet switch.
Figs. 3 is a flowchart illustrating the process of implementing an automatic transmission rate-controlling operation upon generation of an overflow within the Ethernet switch due to congestion of data inputted to a line interface logic circuit according to a preferred embodiment of the present invention.
The automatic transmission rate-controlling operation according to a preferred embodiment of the present invention will be described in detail hereinafter with reference to Fig. 2 and 3.
In the description of a preferred embodiment of the present invention, for the purpose of its convenience, suppose that a transmission rate of data inputted from the external terminal unit 100 to the line interface logic circuit 202 through an input port A
is 100Mbps and that of data outputted to other Ethernet switch 104 from the line interface logic circuit 204 through an output port B is l OMbps.
First, at step 300, if the external terminal unit such as PC 100 is connected to the Ethernet switch 102 through the input port "A", the line transmission rate controller 204 allows an activated bit of an automatic transmission rate-setting function of a PHY control register included in the line interface logic circuit 202 to be set to a logic "high", i.e., a logic value of "1 ", and sets an optimum transmission rate for transmitting data between the external terminal unit 100 and the Ethernet switch 102 by using the automatic transmission rate-setting function of the line interface logic circuit 202. That is, as described in an embodiment of the present invention, if the port "A" is a port of a combined lOMbps/100Mbps and the external terminal unit P8906/STN (23728/1999) is also a port of a combined lOMbps/100Mbps, the line interface logic circuit 200 sets the transmission rate to 100Mbps depending on the automatic transmission rate-setting function. Accordingly, data is transmitted from the external terminal unit 100 to the Ethernet switch 102 through the port "A" at the set transmission rate. And then, the S program proceeds to subsequent step 302 at which the line transmission rate controller 204 determines whether or not the line interface logic circuit 200 receives the data transmitted from the external terminal unit 100 through the port "A". If it is determined at step 302 that the data is received from the external terminal unit 200, the program proceeds to step 304 where the line transmission rate controller 204 stores temporarily the received data in the buffer 206. At subsequent step 306, the line transmission rate controller 204 allows the data stored in the buffer 206 to be read-out and transmitted to an associated destination node through the port "B". And then, at next step 308, the line transmission rate controller 204 determines whether or not there is generated an overflow due to data congestion. As described above, in the case that the Ethernet switch is a switch employing a shared buffer, the overflow is an undesirable phenomenon which affects directly other ports of the Ethernet switch 102 so that data throughput is reduced steeply in an entire communication network.
In other words, if the transmission rate of data inputted to the Ethernet switch 102 from the external terminal 100 is higher than that of data outputted from the Ethernet switch 102, the just inputted data is not outputted to the associated destination node, but is accumulated in the buffer 206 of the Ethernet switch 102. As a result, the line transmission rate controller 204 monitors data stream over a data transmission path and compares the transmission rate of the inputted data with the transmission rate of the outputted data to determine if there is generated an overflow owing to data congestion.
If it is determined at the step 308 that there is not generated the overflow, the _ g _ P8906/S1'N (23728/1999) program returns to the previous step 302 where the line transmission rate controller 204 performs the following steps 302 through 308 again. If, on the other hand, it is determined at step 308 that there is generated an overflow, the program proceeds to step 310 at which the line transmission rate controller 204 generates a control signal for reducing the transmission rate of data inputted to the Ethernet switch 102 from the external terminal unit 100 for application to the line interface logic circuit 200. The transmission rate of the inputted data is reduced in such a fashion that it corresponds to a transmission rate at which the data is outputted from the Ethernet switch 102. That is, the line interface logic circuit 200 allows a bit value of a transmission rate of the PHY control register therein to be set to a logic "low", i.e., a logic value of "0"
according to the control signal, and an activated bit of the automatic transmission rate-setting function is also set to a logic value of "0" so that the transmission rate of the inputted data is reduced to lOMbps. As a result, the program proceeds to step 312 at which the line interface logic circuit 200 executes the transmission rate-reducing operation according to the control signal so that the transmission rate of the input port "A" set between the external terminal unit 100 and the Ethernet switch 102 is controlled to correspond to that of the output port "B".
As described above, the Ethernet switch supporting a variety of transmission rates of the present invention provides advantages that the transmission rate of the input port is automatically controlled to correspond to that of the output port, thereby preventing loss of data due to generation of an overflow over a data transmission path, and reduction of data throughput in an entire communication network.
While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment, but, on the contrary, it is P8906/STN (23728/1999) intended to cover various modifications within the spirit and scope of the appended claims.
Claims (2)
1. A device of automatically controlling a data transmission rate for preventing a generation of an overflow in an Ethernet switch having a pair of ports each supporting a variety of transmission rates, comprising:
one or more line interface logic circuits coupled to an external terminal unit, through one of the pair of ports, adapted to automatically set a transmission rate of the external terminal unit coupled to one of the pair of ports to a predetermined one of the transmission rates supported by the Ethernet switch, and adapted to interface data transmitted between the external terminal unit and the Ethernet switch;
a line transmission rate controller coupled to the one or more line interface logic circuits, adapted to generate a control signal for reducing the transmission rate of data inputted to the Ethernet switch from the external terminal unit for application to the line interface logic circuit upon generation of an overflow within the Ethernet switch due to congestion of the inputted data, the transmission rate of the inputted data being reduced in such a fashion that it corresponds to a transmission rate at which the data is outputted from the Ethernet switch; and a buffer memory coupled to the line transmission rate controller, adapted to temporarily store data transmitted through the line interface logic circuit therein depending on the control of the line transmission rate controller.
one or more line interface logic circuits coupled to an external terminal unit, through one of the pair of ports, adapted to automatically set a transmission rate of the external terminal unit coupled to one of the pair of ports to a predetermined one of the transmission rates supported by the Ethernet switch, and adapted to interface data transmitted between the external terminal unit and the Ethernet switch;
a line transmission rate controller coupled to the one or more line interface logic circuits, adapted to generate a control signal for reducing the transmission rate of data inputted to the Ethernet switch from the external terminal unit for application to the line interface logic circuit upon generation of an overflow within the Ethernet switch due to congestion of the inputted data, the transmission rate of the inputted data being reduced in such a fashion that it corresponds to a transmission rate at which the data is outputted from the Ethernet switch; and a buffer memory coupled to the line transmission rate controller, adapted to temporarily store data transmitted through the line interface logic circuit therein depending on the control of the line transmission rate controller.
2. A method of automatically controlling a data transmission rate for preventing a generation of an overflow in an Ethernet switch having a pair of ports each supporting a variety of transmission rates, comprising:
automatically setting a transmission rate of an external terminal unit coupled to one of the pair of ports to a predetermined one of the transmission rates supported by the Ethernet switch;
temporarily storing data inputted to the Ethernet switch from the external terminal unit at the set transmission rate in a buffer memory, and then transmitting the stored data to a destination node; and generating a control signal for reducing the transmission rate of data inputted to the Ethernet switch from the external terminal unit for application to the line interface logic circuit upon generation of an overflow due to congestion of the inputted data, the transmission rate of the inputted data being reduced in such a fashion that it corresponds to a transmission rate at which the data is outputted from the Ethernet switch.
automatically setting a transmission rate of an external terminal unit coupled to one of the pair of ports to a predetermined one of the transmission rates supported by the Ethernet switch;
temporarily storing data inputted to the Ethernet switch from the external terminal unit at the set transmission rate in a buffer memory, and then transmitting the stored data to a destination node; and generating a control signal for reducing the transmission rate of data inputted to the Ethernet switch from the external terminal unit for application to the line interface logic circuit upon generation of an overflow due to congestion of the inputted data, the transmission rate of the inputted data being reduced in such a fashion that it corresponds to a transmission rate at which the data is outputted from the Ethernet switch.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR23728/1999 | 1999-06-23 | ||
| KR1019990023728A KR20010003431A (en) | 1999-06-23 | 1999-06-23 | Apparatus and method for automatically controlling rate to prevent overflow in a eithernet switch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2311888A1 true CA2311888A1 (en) | 2000-12-23 |
Family
ID=19594567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002311888A Abandoned CA2311888A1 (en) | 1999-06-23 | 2000-06-16 | Automatic data transmission rate-controlling device and method for prevention of generation of an overflow in ethernet switch |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2001036559A (en) |
| KR (1) | KR20010003431A (en) |
| CN (1) | CN1291028A (en) |
| CA (1) | CA2311888A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11659447B2 (en) | 2018-08-08 | 2023-05-23 | Telefonaktiebolaget Lm Ericsson (Publ) | Flow control for integrated access backhaul (IAB) networks |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4577670B2 (en) * | 2008-03-13 | 2010-11-10 | Ｎｅｃアクセステクニカ株式会社 | Communication apparatus and data transmission control method |
| KR101055499B1 (en) * | 2009-01-22 | 2011-08-08 | 엘지에릭슨 주식회사 | Adaptive Clock Synchronization Control in Multistage Ethernet Switch Architecture |
| CN104489854A (en) * | 2014-12-22 | 2015-04-08 | 贵州省健康茶科技有限公司 | Lagerstroemia speciosa preservative |
| KR102095164B1 (en) * | 2019-10-31 | 2020-03-30 | 주식회사 애즈원 | Electronic display system with modified ethernet network for a plurality of display units |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01145414A (en) * | 1987-12-02 | 1989-06-07 | Musashi Seimitsu Ind Co Ltd | Connecting structure for arm to ball joint housing |
| JPH0832612A (en) * | 1994-07-13 | 1996-02-02 | Hitachi Cable Ltd | Ethernet switch |
| KR970024275A (en) * | 1995-10-10 | 1997-05-30 | 김광호 | Transistor with increased safe operating area and manufacturing method thereof |
| KR0147471B1 (en) * | 1995-11-24 | 1998-08-17 | 문정환 | Ethernet with the capability of sensing the data rate |
-
1999
- 1999-06-23 KR KR1019990023728A patent/KR20010003431A/en active IP Right Grant
-
2000
- 2000-06-15 JP JP2000180427A patent/JP2001036559A/en active Pending
- 2000-06-16 CA CA002311888A patent/CA2311888A1/en not_active Abandoned
- 2000-06-23 CN CN00118890A patent/CN1291028A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11659447B2 (en) | 2018-08-08 | 2023-05-23 | Telefonaktiebolaget Lm Ericsson (Publ) | Flow control for integrated access backhaul (IAB) networks |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001036559A (en) | 2001-02-09 |
| KR20010003431A (en) | 2001-01-15 |
| CN1291028A (en) | 2001-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6167029A (en) | System and method for integrated data flow control | |
| US7961606B2 (en) | Packet flow control in switched full duplex ethernet networks | |
| US6393489B1 (en) | Media access control architectures and network management systems | |
| US6782429B1 (en) | Dynamic communication path selection for data transmission between computers | |
| US7450509B2 (en) | Adaptive flow control method and apparatus | |
| US6085248A (en) | Media access control transmitter and parallel network management system | |
| EP0573204B1 (en) | Network connection method | |
| US7573821B2 (en) | Data packet rate control | |
| US6735629B1 (en) | Method and apparatus for real-time protocol analysis using an active and adaptive auto-throtting CPU allocation front end process | |
| US20030147347A1 (en) | Method for congestion control and associated switch controller | |
| US5230067A (en) | Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto | |
| US5797042A (en) | Method and apparatus for adjusting the buffering characteristic in the pipeline of a data transfer system | |
| EP1941640B1 (en) | Method, circuitry and system for transmitting data at different rates | |
| US6928055B2 (en) | Network interface unit | |
| US7130271B1 (en) | Relaying apparatus | |
| CA2311888A1 (en) | Automatic data transmission rate-controlling device and method for prevention of generation of an overflow in ethernet switch | |
| US7298703B1 (en) | Hysteresis method for reducing control code transmission between a line card and a switching fabric | |
| US7471630B2 (en) | Systems and methods for performing selective flow control | |
| US6819675B2 (en) | Self-route multi-memory expandable packet switch with overflow processing means | |
| US20040257991A1 (en) | Backpressure history mechanism in flow control | |
| EP1106003A1 (en) | Method and system for prioritised congestion control in a switching hub | |
| CA1325284C (en) | Data bus control circuit and technique including data latching for optimizing bus utilization | |
| US20010008528A1 (en) | Communication path control method and repeating apparatus | |
| JP3152136B2 (en) | Switching hub | |
| JPH09149067A (en) | Switching hub |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Dead |