CA2310670A1 - Atm switching device for high data rates - Google Patents
Atm switching device for high data rates Download PDFInfo
- Publication number
- CA2310670A1 CA2310670A1 CA002310670A CA2310670A CA2310670A1 CA 2310670 A1 CA2310670 A1 CA 2310670A1 CA 002310670 A CA002310670 A CA 002310670A CA 2310670 A CA2310670 A CA 2310670A CA 2310670 A1 CA2310670 A1 CA 2310670A1
- Authority
- CA
- Canada
- Prior art keywords
- databus
- devices
- subscriber
- atm
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3009—Header conversion, routing tables or routing tags
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
- H04L49/105—ATM switching elements
- H04L49/107—ATM switching elements using shared medium
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention relates to an ATM switching device having an interconnecting device arranged on a central base assembly (BBG). The interconnecting device has an interconnecting module (X15) with a high-frequency databus (DB0, DB1) for connecting subscriber connection devices. The base assembly (BBG) has a number of connection positions (SLOT0,..., SLOT7) for contacting subscriber connection devices and a number of multiplexer devices (MUX0,..., MUX3) arranged in a near area of the interconnecting module (X15). The multiplexer devices are connected to the interconnecting module (X15) on one side via the high-frequency databus (DB0, DB1), and are connected to at least one respective subscriber connection device on the other side via a subscriber connection device individual databus (TB0,..., TB7).
Description
Description ATM switching device for high data rates Due to the increasing demand for the transmission of visual information in modern communications technology, such as, for example, still and moving images in video telephone applications or the representation of high-resolution graphics on modern personal computers, the significance of transmission and switching technologies for high data transmission rates (greater than 100 Mbit/s) is increasing. The asynchronous transfer mode (ATM) is a familiar data transmission method for high data rates.
At present, data transmission based on the asynchronous transfer mode provides for a variable transmission bit rate of up to 622 Mbit/s.
Known switching devices including those based on the asynchronous transfer mode are usually of modular construction. As a rule, a multiplicity of modules which, for example, implement an interface connecting subscriber lines or a central controller can be plugged in on a central connector assembly common to all modules, a so-called "backplane" and are connected to one another via this backplane. The resultant modularity of the switching devices provides for, among other things, easy adaptability of a switching device to different configurations and simplified fault analysis in a case of servicing.
In this arrangement, the circuit switching devices (e. g. switching networks) of switching systems, in particular, are arranged on one or more separate circuit switching assemblies which can also be plugged in on the backplane.
From the data sheet "MOS INTEGRATED CIRCUIT
~PD98410", NEC Corporation, 1997, Document No.
512624EJ1VODS00 (1st edition), Int. File Reference: PCT/DE98/03425 a large-scale integrated circuit switching chip is known which allows addressing of a number of subscriber-related interfaces via a high-frequency ATM-specific bus interface (UTOPIA: Universal Test &
Operations PHY Interface for ATM).
In EP 0 506 134 A1, an ATM switching device is described which exhibits a circuit switching unit comprising a databus and a multiplexer device. The multiplexer device connects the databus to subscriber - lines for input signals via serial/parallel converters.
The databus in connected to subscriber lines for output signals via address-controller-controlled storage devices and via parallel/serial converters.
The present invention is based on the object of developing an ATM switching device of modular construction, in which a multiplicity of subscriber line devices can be connected, in such a way that a large-scale integrated circuit switching chip designed for ATM applications can be used.
According to the invention, this object is achieved by means of the features of claim 1.
To provide for better understanding of the functions and operation of an ATM switching device, it appears to be necessary to discuss known principles in greater detail once more.
In the transmission method known as asynchronous transfer mode (ATM), fixed-length data packets, so-called cells, are used for transporting the data. An ATM cell is composed of the so-called cell "header", which contains the switching data relevant to the transport of an ATM cell and has a length of five bytes, and the so-called "payload" field which has a length of 48 bytes.
AMENDED SHEET
IPEA/EP
- 2a -Int. File Reference: PCT/DE98/03425 When a connection is being set up in the switching technology designed in accordance with the asynchronous transfer mode, interconnection tables containing the switching and routing information consisting of a virtual channel identifier - called VCI
in the text which follows - and a virtual path identifier - called VPI in the text which follows - are set up in the respective ATM switching device by exchanging signaling information before the beginning of the transmission of useful data in an ATM
communication network. In the interconnection AMENDED SHEET
IPEA/EP
' CA 02310670 2000-OS-18 tables, a VCI value is allocated to the virtual channel identifier and a VPI value is allocated to the virtual path identifier. The switching data or routing information, respectively, entered in the interconnection tables specify how the virtual paths or, respectively, virtual transmission channels contained in the virtual paths of the incoming and outgoing connections at the ATM switching device are coordinated with one another by the signaling, i.e.
which input is linked to which output by switching operations. ATM cells transferred via these virtual connections have switching data, consisting essentially of a VPI value and a VCI value, in the header . The ATM
header data are processed, i.e. the switching data arranged therein are detected and weighted, at the input of an ATM switching device. The ATM cells are then switched by a circuit switching device, arranged in the ATM switching device, to an output representing a particular destination by using the routing information stored in the interconnection table.
When the circuit switching device is arranged on a separate circuit switching assembly, a high-frequency databus (clock rate > 50 MHz) of the large-scale integrated circuit switching chip, which connects a large-scale integrated circuit switching chip to subscriber line devices, would have, for structural reasons, a length of approximately 30 to 40 cm, even in relatively small switching devices, which length is too great for the required clock rate for reasons of line theory. An additional aggravating factor is that when a number of subscriber line devices are in contact with the high-frequency databus, an additional reduction in bus length is required in order to maintain the conditions required by line theory.
The arrangement according to the invention then provides the advantage that, when the large-scale integrated circuit switching chip is arranged ' ~ ~ GR 97 P 2929 - 4 -on a base assembly and multiplexer devices are interposed between the large-scale integrated circuit switching chip and the subscriber line devices, the length of the high-frequency databus - which connects the large-scale integrated circuit switching chip to the multiplexer devices, can be kept very short.
In addition, the high-frequency databus is decoupled in time from the subscriber-line-device-individual databuses by interposing the multiplexer devices, so that each individual subscriber, line-device-individual databus can be operated at a lower clock rate which, if necessary, can be predetermined individually by the subscriber line device. In addition, a pure point-to-point connection, i.e. only two connections per connecting line, is produced between a multiplexer device and a subscriber line device. The resultant, more advantageous line characteristics provide for a length of the subscriber-line-device-individual databus which is more generous compared with the high-frequency databus.
Advantageous further developments of the invention are specified in the subclaims.
In the text which follows, an illustrative embodiment of the invention is explained in greater detail with reference to the drawing, in which:
Figure 1 shows a structural diagram for the diagrammatic representation of the essential functional units of a circuit switching chip designed in accordance with the asynchronous transfer mode;
Figure 2 shows a structural diagram for the diagrammatic representation of the essential functional units arranged on a base assembly of a ' CA 02310670 2000-OS-18 switching device according to the invention.
Figure 1 shows a diagrammatic representation of the essential functional units of a large-scale integrated circuit switching chip X15. The circuit switching chip X15 is connected to a high-frequency databus DB via an input interface ESS and an output interface ASS. In addition, the circuit switching chip X15 is connected to a first memory - not shown in the drawing - via a first interface DSS and to a second memory - not shown in the drawing - containing switching data or, respectively, routing information, via a second interface HSS.
ATM cells arriving are forwarded via the input interface ESS to an input separator IS which separates the header and the payload of the incoming ATM cell from one another. The data of the payload are forwarded via the first interface DSS to the first memory where they are temporarily stored. The switching data located in the header of the ATM cell are partly forwarded to a control unit QQ, and the VCI value contained in the switching data and the VPI value are forwarded to the second memory via the second interface HSS. Using the routing information stored in the form of interconnection tables in the second memory, the VCI
value and the VPI value are reweighted for forwarding to the ATM cell.
If an arbitration unit A of the circuit switching chip X15 signals to the control unit QQ that a subscriber line device - not shown in the drawing - which is connected via the databus DB is requesting data, the control unit QQ checks whether ATM
cells allocated to this subscriber line device have been temporarily stored. If this is so, the header previously separated, containing the reweighted ' CA 02310670 2000-OS-18 r VCI value and the reweighted VPI value, and the associated payload are combined in an output selector OS, and written onto the databus DB via the output interface ASS.
Figure 2 shows a diagrammatic representation of the essential functional units arranged on a base assembly BBG of a switching device according to the invention. The base assembly BBG exhibits a large-scale integrated circuit switching chip X15 which is connected to a first memory MEM1 and a second memory MEM2 via in case one memory databus. The first memory MEM1 is used for temporarily storing useful information stored in an ATM cell. In the second memory MEM2, routing information for the ATM cells to be switched is stored in the form of switching tables. For a connection to subscriber line devices, not shown in the drawing, the circuit switching chip X15 has a first and a second high-frequency (50 MHz clock rate) databus DBO, DB1 having a width of 16 bits.
The base assembly BBG has eight connection slots SLOTO,...,SLOT7 to provide contact with subscriber line units, and four multiplexes devices MUXO,...,MUX3 arranged in close vicinity to the circuit switching chip X15. A first and a second multiplexes device MUXO, MUX1 are connected via the first high-frequency databus DBO, and a third and a fourth multiplexes device MUX2, MUX3 are connected via the second high-frequency databuses DB1, to the circuit switching chip X15. The length of the first and the second high-frequency databuses DBO, DB1 is minimized by arranging the multiplexes devices MUXO,..., MUX3 in close vicinity to the circuit switching chip X15.
' CA 02310670 2000-OS-18 To connect subscriber line devices to the circuit switching chip X15, a first connection slot SLOTO is connected via a first subscriber-line-device-individual databus TBO, and a second connection slot SLOT1 is connected via a second subscriber-line-device-individual databus TB1, to the first multiplexes device MUXO. Analogously, the third to eighth connection slots SLOT2,...,SLOT7 are connected to the second to fourth multiplexes devices MUX1,...,MUX3. Since hitherto only eight-bit-wide chips have been known for ATM-specific chips, a subscriber-line-device-individual databus TBO,...,TB7 is composed of two separate eight-bit-wide databuses.
Connecting a subscriber line device to a multiplexes device MUXO,...,MUX3 via a separate subscriber-line-device-individual databus TBO,...,TB7 produces a defined point-to-point connection between this subscriber line device and the associated multiplexes device MUXO,...,MUX3. The associated advantageous line characteristics make it possible to transmit data via a longer transmission link.
Due to the fact that the subscriber-line-device-individual databuses TBO,...,TB7 are decoupled in time from the first and second high-frequency databuses DBO, DBl, which is achieved by the multiplexes devices MUXO,...,MUX3, each subscriber-line-device-individual databus TBO, ..., TB7 can be operated at a separate, lower clock rate predetermined by the respective subscriber line device.
At present, data transmission based on the asynchronous transfer mode provides for a variable transmission bit rate of up to 622 Mbit/s.
Known switching devices including those based on the asynchronous transfer mode are usually of modular construction. As a rule, a multiplicity of modules which, for example, implement an interface connecting subscriber lines or a central controller can be plugged in on a central connector assembly common to all modules, a so-called "backplane" and are connected to one another via this backplane. The resultant modularity of the switching devices provides for, among other things, easy adaptability of a switching device to different configurations and simplified fault analysis in a case of servicing.
In this arrangement, the circuit switching devices (e. g. switching networks) of switching systems, in particular, are arranged on one or more separate circuit switching assemblies which can also be plugged in on the backplane.
From the data sheet "MOS INTEGRATED CIRCUIT
~PD98410", NEC Corporation, 1997, Document No.
512624EJ1VODS00 (1st edition), Int. File Reference: PCT/DE98/03425 a large-scale integrated circuit switching chip is known which allows addressing of a number of subscriber-related interfaces via a high-frequency ATM-specific bus interface (UTOPIA: Universal Test &
Operations PHY Interface for ATM).
In EP 0 506 134 A1, an ATM switching device is described which exhibits a circuit switching unit comprising a databus and a multiplexer device. The multiplexer device connects the databus to subscriber - lines for input signals via serial/parallel converters.
The databus in connected to subscriber lines for output signals via address-controller-controlled storage devices and via parallel/serial converters.
The present invention is based on the object of developing an ATM switching device of modular construction, in which a multiplicity of subscriber line devices can be connected, in such a way that a large-scale integrated circuit switching chip designed for ATM applications can be used.
According to the invention, this object is achieved by means of the features of claim 1.
To provide for better understanding of the functions and operation of an ATM switching device, it appears to be necessary to discuss known principles in greater detail once more.
In the transmission method known as asynchronous transfer mode (ATM), fixed-length data packets, so-called cells, are used for transporting the data. An ATM cell is composed of the so-called cell "header", which contains the switching data relevant to the transport of an ATM cell and has a length of five bytes, and the so-called "payload" field which has a length of 48 bytes.
AMENDED SHEET
IPEA/EP
- 2a -Int. File Reference: PCT/DE98/03425 When a connection is being set up in the switching technology designed in accordance with the asynchronous transfer mode, interconnection tables containing the switching and routing information consisting of a virtual channel identifier - called VCI
in the text which follows - and a virtual path identifier - called VPI in the text which follows - are set up in the respective ATM switching device by exchanging signaling information before the beginning of the transmission of useful data in an ATM
communication network. In the interconnection AMENDED SHEET
IPEA/EP
' CA 02310670 2000-OS-18 tables, a VCI value is allocated to the virtual channel identifier and a VPI value is allocated to the virtual path identifier. The switching data or routing information, respectively, entered in the interconnection tables specify how the virtual paths or, respectively, virtual transmission channels contained in the virtual paths of the incoming and outgoing connections at the ATM switching device are coordinated with one another by the signaling, i.e.
which input is linked to which output by switching operations. ATM cells transferred via these virtual connections have switching data, consisting essentially of a VPI value and a VCI value, in the header . The ATM
header data are processed, i.e. the switching data arranged therein are detected and weighted, at the input of an ATM switching device. The ATM cells are then switched by a circuit switching device, arranged in the ATM switching device, to an output representing a particular destination by using the routing information stored in the interconnection table.
When the circuit switching device is arranged on a separate circuit switching assembly, a high-frequency databus (clock rate > 50 MHz) of the large-scale integrated circuit switching chip, which connects a large-scale integrated circuit switching chip to subscriber line devices, would have, for structural reasons, a length of approximately 30 to 40 cm, even in relatively small switching devices, which length is too great for the required clock rate for reasons of line theory. An additional aggravating factor is that when a number of subscriber line devices are in contact with the high-frequency databus, an additional reduction in bus length is required in order to maintain the conditions required by line theory.
The arrangement according to the invention then provides the advantage that, when the large-scale integrated circuit switching chip is arranged ' ~ ~ GR 97 P 2929 - 4 -on a base assembly and multiplexer devices are interposed between the large-scale integrated circuit switching chip and the subscriber line devices, the length of the high-frequency databus - which connects the large-scale integrated circuit switching chip to the multiplexer devices, can be kept very short.
In addition, the high-frequency databus is decoupled in time from the subscriber-line-device-individual databuses by interposing the multiplexer devices, so that each individual subscriber, line-device-individual databus can be operated at a lower clock rate which, if necessary, can be predetermined individually by the subscriber line device. In addition, a pure point-to-point connection, i.e. only two connections per connecting line, is produced between a multiplexer device and a subscriber line device. The resultant, more advantageous line characteristics provide for a length of the subscriber-line-device-individual databus which is more generous compared with the high-frequency databus.
Advantageous further developments of the invention are specified in the subclaims.
In the text which follows, an illustrative embodiment of the invention is explained in greater detail with reference to the drawing, in which:
Figure 1 shows a structural diagram for the diagrammatic representation of the essential functional units of a circuit switching chip designed in accordance with the asynchronous transfer mode;
Figure 2 shows a structural diagram for the diagrammatic representation of the essential functional units arranged on a base assembly of a ' CA 02310670 2000-OS-18 switching device according to the invention.
Figure 1 shows a diagrammatic representation of the essential functional units of a large-scale integrated circuit switching chip X15. The circuit switching chip X15 is connected to a high-frequency databus DB via an input interface ESS and an output interface ASS. In addition, the circuit switching chip X15 is connected to a first memory - not shown in the drawing - via a first interface DSS and to a second memory - not shown in the drawing - containing switching data or, respectively, routing information, via a second interface HSS.
ATM cells arriving are forwarded via the input interface ESS to an input separator IS which separates the header and the payload of the incoming ATM cell from one another. The data of the payload are forwarded via the first interface DSS to the first memory where they are temporarily stored. The switching data located in the header of the ATM cell are partly forwarded to a control unit QQ, and the VCI value contained in the switching data and the VPI value are forwarded to the second memory via the second interface HSS. Using the routing information stored in the form of interconnection tables in the second memory, the VCI
value and the VPI value are reweighted for forwarding to the ATM cell.
If an arbitration unit A of the circuit switching chip X15 signals to the control unit QQ that a subscriber line device - not shown in the drawing - which is connected via the databus DB is requesting data, the control unit QQ checks whether ATM
cells allocated to this subscriber line device have been temporarily stored. If this is so, the header previously separated, containing the reweighted ' CA 02310670 2000-OS-18 r VCI value and the reweighted VPI value, and the associated payload are combined in an output selector OS, and written onto the databus DB via the output interface ASS.
Figure 2 shows a diagrammatic representation of the essential functional units arranged on a base assembly BBG of a switching device according to the invention. The base assembly BBG exhibits a large-scale integrated circuit switching chip X15 which is connected to a first memory MEM1 and a second memory MEM2 via in case one memory databus. The first memory MEM1 is used for temporarily storing useful information stored in an ATM cell. In the second memory MEM2, routing information for the ATM cells to be switched is stored in the form of switching tables. For a connection to subscriber line devices, not shown in the drawing, the circuit switching chip X15 has a first and a second high-frequency (50 MHz clock rate) databus DBO, DB1 having a width of 16 bits.
The base assembly BBG has eight connection slots SLOTO,...,SLOT7 to provide contact with subscriber line units, and four multiplexes devices MUXO,...,MUX3 arranged in close vicinity to the circuit switching chip X15. A first and a second multiplexes device MUXO, MUX1 are connected via the first high-frequency databus DBO, and a third and a fourth multiplexes device MUX2, MUX3 are connected via the second high-frequency databuses DB1, to the circuit switching chip X15. The length of the first and the second high-frequency databuses DBO, DB1 is minimized by arranging the multiplexes devices MUXO,..., MUX3 in close vicinity to the circuit switching chip X15.
' CA 02310670 2000-OS-18 To connect subscriber line devices to the circuit switching chip X15, a first connection slot SLOTO is connected via a first subscriber-line-device-individual databus TBO, and a second connection slot SLOT1 is connected via a second subscriber-line-device-individual databus TB1, to the first multiplexes device MUXO. Analogously, the third to eighth connection slots SLOT2,...,SLOT7 are connected to the second to fourth multiplexes devices MUX1,...,MUX3. Since hitherto only eight-bit-wide chips have been known for ATM-specific chips, a subscriber-line-device-individual databus TBO,...,TB7 is composed of two separate eight-bit-wide databuses.
Connecting a subscriber line device to a multiplexes device MUXO,...,MUX3 via a separate subscriber-line-device-individual databus TBO,...,TB7 produces a defined point-to-point connection between this subscriber line device and the associated multiplexes device MUXO,...,MUX3. The associated advantageous line characteristics make it possible to transmit data via a longer transmission link.
Due to the fact that the subscriber-line-device-individual databuses TBO,...,TB7 are decoupled in time from the first and second high-frequency databuses DBO, DBl, which is achieved by the multiplexes devices MUXO,...,MUX3, each subscriber-line-device-individual databus TBO, ..., TB7 can be operated at a separate, lower clock rate predetermined by the respective subscriber line device.
Claims (4)
1. An ATM switching device for high data rates, comprising a circuit switching unit which exhibits a central integrated circuit switching chip (X15), arranged on a base assembly (BBG), and at least one high-frequency databus (DB0, DB1), wherein a number of connection slots (SLOT0,...,SLOT7) for making contact with subscriber line devices are provided on the base assembly (BBG), and wherein a number of multiplexer devices (MUX0,...,MUX3) are arranged on the base assembly (BBG), which multiplexer devices are connected, on the one hand, to the central integrated circuit switching chip (X15) via a high-frequency databus (DB0, DB1) and, on the other hand, are connected to in each case at least one subscriber line device via a subscriber-line-device-individual databus (TB0,...,TB7).
2. The ATM switching device as claimed in claim 1, characterized in that the multiplexer devices (MUX0,...,MUX3) are arranged in close vicinity to the circuit switching chip (X15) on the base assembly (BBG).
3. The ATM switching device as claimed in one of the preceding claims, characterized in that the subscriber line devices make contact with the connection slots ( SLOT0, ..., SLOT7 ) via a plug-in connection.
4. The ATM switching device as claimed in one of the preceding claims, characterized in that a 16-bit-wide databus is provided as high-frequency databus (DB0, DB1), and in that the subscriber-line-device-individual databus (TB0,...,TB7) is composed of two separate 8-bit-wide databuses.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19751559A DE19751559A1 (en) | 1997-11-20 | 1997-11-20 | ATM exchange arrangement for high data transfer speed |
| DE19751559.2 | 1997-11-20 | ||
| PCT/DE1998/003425 WO1999027748A2 (en) | 1997-11-20 | 1998-11-19 | Atm switching device for high data speeds |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2310670A1 true CA2310670A1 (en) | 1999-06-03 |
Family
ID=7849380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002310670A Abandoned CA2310670A1 (en) | 1997-11-20 | 1998-11-19 | Atm switching device for high data rates |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1033060B1 (en) |
| JP (1) | JP2001524794A (en) |
| CN (1) | CN1138442C (en) |
| CA (1) | CA2310670A1 (en) |
| DE (2) | DE19751559A1 (en) |
| WO (1) | WO1999027748A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10203806A1 (en) * | 2002-01-31 | 2003-08-14 | Siemens Ag | Communications system transmitting data packets via network, separates useful- from routing information, which is processed separately, relieving resources |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2635243B1 (en) * | 1988-08-05 | 1994-01-14 | Lmt Radio Professionnelle | PACKET SWITCHER FOR ASYNCHRONOUS DATA TRANSFER IN A DIGITAL TRANSMISSION NETWORK |
| CA2064323C (en) * | 1991-03-29 | 1997-12-30 | Takatoshi Kurano | Atm cell multiplexing device capable of reducing an accessing speed to a fifo memory thereof |
| US5475679A (en) * | 1994-12-08 | 1995-12-12 | Northern Telecom Limited | Large capacity ATM switch |
| US5668798A (en) * | 1995-04-05 | 1997-09-16 | International Business Machines Corporation | Multiplexed TC sublayer for ATM switch |
-
1997
- 1997-11-20 DE DE19751559A patent/DE19751559A1/en not_active Withdrawn
-
1998
- 1998-11-19 CA CA002310670A patent/CA2310670A1/en not_active Abandoned
- 1998-11-19 EP EP98965084A patent/EP1033060B1/en not_active Expired - Lifetime
- 1998-11-19 CN CNB988114097A patent/CN1138442C/en not_active Expired - Fee Related
- 1998-11-19 JP JP2000522758A patent/JP2001524794A/en not_active Withdrawn
- 1998-11-19 WO PCT/DE1998/003425 patent/WO1999027748A2/en active IP Right Grant
- 1998-11-19 DE DE59812132T patent/DE59812132D1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE59812132D1 (en) | 2004-11-18 |
| JP2001524794A (en) | 2001-12-04 |
| WO1999027748A2 (en) | 1999-06-03 |
| CN1138442C (en) | 2004-02-11 |
| DE19751559A1 (en) | 1999-05-27 |
| EP1033060B1 (en) | 2004-10-13 |
| EP1033060A2 (en) | 2000-09-06 |
| CN1279875A (en) | 2001-01-10 |
| WO1999027748A3 (en) | 1999-07-22 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |