CA2308937A1 - Method and apparatus for interconnection of flow-controlled communication - Google Patents
Method and apparatus for interconnection of flow-controlled communication Download PDFInfo
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- CA2308937A1 CA2308937A1 CA002308937A CA2308937A CA2308937A1 CA 2308937 A1 CA2308937 A1 CA 2308937A1 CA 002308937 A CA002308937 A CA 002308937A CA 2308937 A CA2308937 A CA 2308937A CA 2308937 A1 CA2308937 A1 CA 2308937A1
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Abstract
A method or system or apparatus provides improved digital communication. In one aspect, flow control in performed by receiving status preprended to data units in a combined data channel, where the status data indicated the available status of a number of far end receiving channels. Thus data may be sent only to available receiving channels. In a further aspect, a frequency reference may also be transmitted by including data in data units in a combined channel. In a further aspect, an active channel can be selected among two redundant channels by use of an active bit in said data units. The invention has particular applications to ATM-type communication systems and may also be used in other communication systems.
Claims (59)
1. A method of flow control in a digital communications system wherein data flows in a first direction in a channel and in a second opposite direction in multiple channels comprising:
in a transferred data unit in said first direction, including a portion of data indicating available/not-available status of a set of channels in said second direction;
prior to selecting a channel in said second direction for transmitting a data unit, checking status of said channel as indicated in said portion; and selecting a channel for transmission from among channels indicated available in said portion.
in a transferred data unit in said first direction, including a portion of data indicating available/not-available status of a set of channels in said second direction;
prior to selecting a channel in said second direction for transmitting a data unit, checking status of said channel as indicated in said portion; and selecting a channel for transmission from among channels indicated available in said portion.
2. The method according to claim 1 wherein there is a delay between reception of said portion and said selecting and wherein sufficient buffering is provided on said second channels to compensate for said delay.
3. The method according to claim 1 wherein said portion indicates status of a part of possible channels in said second direction and wherein multiple data units in said first direction must be received to update status of all channels in said second direction.
4. The method according to claim 1 wherein said portion comprises a set of bit-flags, the state of each bit flag indicating available/not-available status of one of said channels in said second direction.
5. The method according to claim 1 wherein said status indicates space available in a buffer for a second direction channel and wherein a number of spare buffer locations are available to compensate for a delay in signaling said status.
6. The method according to claim 1 wherein a cell transmitted on a link includes a bit-oriented code (BOC) portion, wherein BOCs are used to carry predefined or user-defined signaling.
7. The method according to claim 6 wherein bit oriented codes are transmitted as a repeating 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero.
8. The method according to claim 1 wherein:
said flow control is per logical channel;
said portion comprises multiple bits per data unit used to indicate downstream status; and wherein said per logical channel flow control uses a simple XON/XOFF control.
said flow control is per logical channel;
said portion comprises multiple bits per data unit used to indicate downstream status; and wherein said per logical channel flow control uses a simple XON/XOFF control.
9. The method according to claim 1 further comprising:
including in said data units a timing reference independent of a serial link bit rate.
including in said data units a timing reference independent of a serial link bit rate.
10. The method according to claim 1 wherein each data unit transmitted contains downstream status information.
11. The method according to claim 10 wherein each data unit transmitted in said first direction contains 16 bits of information that convey the status for 16 of 32 active channels in said second direction.
12. The method according to claim 1 wherein a separate overhead bit per data unit conveys buffer status of a far-end microprocessor port.
13. A method for downstream data flow control comprising:
placing cells for downstream channels into a plurality of buffers, said buffers grouped into sets of buffers;
for a set of said sets, scheduling a cell out of said set and transmitting said cell to an access module, said access module serving a plurality of channels; said scheduling comprising:
eliminating from a scheduling round a channel that is presenting a far-end buffer full status; and performing an access algorithm among remaining eligible channels to share a downstream link.
placing cells for downstream channels into a plurality of buffers, said buffers grouped into sets of buffers;
for a set of said sets, scheduling a cell out of said set and transmitting said cell to an access module, said access module serving a plurality of channels; said scheduling comprising:
eliminating from a scheduling round a channel that is presenting a far-end buffer full status; and performing an access algorithm among remaining eligible channels to share a downstream link.
14. The method according to claim 13 wherein said plurality of buffers comprises at least a single cell buffer for each channel and wherein said sets are each assigned to a link, said link providing a serial data connection from a scheduler to an access module.
15. The method according to claim 13 wherein scheduling of a cell is performed when a previous cell has been fully transmitted from a buffer over a link.
16. The method according to claim 13 further comprising:
when there is no data in any buffer in a set of buffers, generating a stuff cell for said set and transmitting said stuff cell on a link for said set.
when there is no data in any buffer in a set of buffers, generating a stuff cell for said set and transmitting said stuff cell on a link for said set.
17. A method for upstream data flow control comprising:
placing cells for upstream transmission from a plurality of logical channels into a plurality of shared buffers; and servicing said shared buffers with a weighted round-robin algorithm to present said cells to an upstream bus master as a single cell stream.
placing cells for upstream transmission from a plurality of logical channels into a plurality of shared buffers; and servicing said shared buffers with a weighted round-robin algorithm to present said cells to an upstream bus master as a single cell stream.
18. The method according to claim 17 wherein when an upstream buffer has less than a preset number of empty cell buffers, said upstream buffer deasserts a cell available bit sent in system overhead of a corresponding downstream link and wherein a far end device begins sending stuff cells upon indication that the upstream buffer is unavailable.
19. The method according to claim 18 wherein said present number is three, allowing for two additional cells to be accepted after a cell available bit is deasserted.
20. A method for providing a timing reference over a serial data unit stream comprising:
determining an edge of a reference clock signal at a transmit location;
including in cells transmitted in said serial stream a timing reference field wherein said field value represents a number of bytes after a predetermined point at which a timing reference edge occurs; and recovering at a receive location said reference clock signal from said serial stream.
determining an edge of a reference clock signal at a transmit location;
including in cells transmitted in said serial stream a timing reference field wherein said field value represents a number of bytes after a predetermined point at which a timing reference edge occurs; and recovering at a receive location said reference clock signal from said serial stream.
21. The method according to claim 20 wherein if no occurs during a data unit, setting said timing reference field to a null value.
22. The method according to claim 20 wherein any frequency less than the data unit rate can be transmitted.
23. The method according to claim 20 wherein a recovered clock is generated one cell period later than the inserted timing.
24. The method according to claim 20 wherein a recovered clock has a resolution limited to one byte and therefore some fitter is recovered clock signal may be present.
25. The method according to claim 24 further comprising applying a local phase locked loop as said receive location to remove fitter.
26. The method according to claim 20 wherein every data unit transmitted over said link contains a timing reference portion.
27. A method for upstream data transfer between a plurality of ports and a higher-speed data device comprising:
receiving data units from a plurality of ports at a multi-port controller and tagging said data with a port id;
transferring said tagged data over a serial link to an upstream handler; and wherein said ports operate as bus slaves and a multi-port controller operates as bus master and data is transmitted on a digital bus from said ports to said multi-port controller.
receiving data units from a plurality of ports at a multi-port controller and tagging said data with a port id;
transferring said tagged data over a serial link to an upstream handler; and wherein said ports operate as bus slaves and a multi-port controller operates as bus master and data is transmitted on a digital bus from said ports to said multi-port controller.
28. The method according to claim 27 wherein said data is buffered at said plurality of ports until read by said multi-port controller.
29. The method according to claim 27 wherein said data is held at said plurality of ports until it is read by said multi-port controller.
30. The method according to claim 27 wherein said data is transferred to an upstream handler over both an active and a standby serial link.
31. The method according to claim 27 wherein said data is transferred by a multi-port controller as soon as it is read from a port.
32. The method according to claim 27 wherein said tagging is accomplished by cell prepend.
33. The method according to claim 27 wherein said data units comprise ATM
cells.
cells.
34. The method according to claim 27 wherein said ports comprise xDSL modems.
35. The method according to claim 27 wherein said serial link connects an access line card to a WAN uplink card.
36. The method according to claim 27 wherein, in response to back-pressure, a multi-port controller will temporarily suspend sending data on a serial link from all ports.
37. The method according to claim 27 further comprising:
receiving data from said serial link at an upstream handler;
at said upstream handler, placing received data in a per serial link buffer.
receiving data from said serial link at an upstream handler;
at said upstream handler, placing received data in a per serial link buffer.
38. The method according to claim 27 further comprising:
at said upstream handler, servicing serial links in a round robin fashion; and as a data cell is received by said upstream handler, tagged said data cell with a serial link ID and an uplink handler ID.
at said upstream handler, servicing serial links in a round robin fashion; and as a data cell is received by said upstream handler, tagged said data cell with a serial link ID and an uplink handler ID.
39. The method according to claim 38 wherein said tagging is accomplished by cell prepend.
40. A method for downstream data transfer between a higher-speed data device and a plurality of ports comprising:
receiving data units destined for a plurality of ports over a serial link, said data units tagged with a port id;
placing a data unit in one of a plurality of per port buffers, based on said tag;
removing the port ID of said data unit; and transferring data from one of said per port buffers to a respective port when said port is available to receive data.
receiving data units destined for a plurality of ports over a serial link, said data units tagged with a port id;
placing a data unit in one of a plurality of per port buffers, based on said tag;
removing the port ID of said data unit; and transferring data from one of said per port buffers to a respective port when said port is available to receive data.
41. The method according to claim 40 wherein said tagging is accomplished by cell prepend.
42. The method according to claim 40 wherein said data units comprise ATM
cells.
cells.
43. The method according to claim 40 wherein said ports comprise xDSL modems.
44. The method according to claim 40 wherein said serial link connects an access line card to a WAN uplink card.
45. The method according to claim 40 wherein said ports operate as bus slaves and said buffers are managed by a mufti-port scheduler operating as a bus master for transfer of data units from said buffers to said ports.
46. The method according to claim 40 wherein as bus master, said mufti-port scheduler polls available status lines of ports for which it has a downstream cell buffered to determine port availability.
47. The method according to claim 40 wherein said multi-port scheduler asserts per-port back-pressure over said serial link when a per-port buffer begins to fill.
48. The method according to claim 40 wherein said back-pressure is sent via embedded overhead on an upstream data serial link.
49. The method according to claim 40 wherein said data is transferred to said plurality of ports over both an active and a standby serial link.
50. The method according to claim 40 wherein, in response to per-port back-pressure, a network layer will temporarily suspend sending data directed to that port.
51. The method according to claim 40 wherein a core handler provides 256 proxy cell ready signals that can be used directly by an ATM traffic management device to schedule cells directed to particular ports.
52. The method according to claim 40 wherein as the VORTEX receives a downstream cell from the ATM layer the in-band prepended address is decoded and used to route the cell to the appropriate link and the appropriate PHY buffer.
53. The method according to claim 40 wherein data units carry an active traffic indication and wherein in a downstream data unit, the indication is a request to accept data and in an upstream data unit, the indication is an acknowledgement that data is being accepted.
54. The method according to claim 53 wherein active traffic indications from a pair of links are used to determine the source of data accepted by the multiply port scheduler.
55. A communication system comprising:
an up-link module providing centralized traffic management for a plurality of access line cards, said up-link module comprising:
an upstream cell interface receiving upstream cell traffic and able to read downstream channel status data from received upstream data; and downstream traffic management performing per port flow control of downstream traffic based on said status data;
a plurality of access line modules connecting to a plurality of subscribe loop interfaces;
and a plurality of cell interconnection for connecting said access line modules to said up-link module.
an up-link module providing centralized traffic management for a plurality of access line cards, said up-link module comprising:
an upstream cell interface receiving upstream cell traffic and able to read downstream channel status data from received upstream data; and downstream traffic management performing per port flow control of downstream traffic based on said status data;
a plurality of access line modules connecting to a plurality of subscribe loop interfaces;
and a plurality of cell interconnection for connecting said access line modules to said up-link module.
56. A system according to claim 55 further comprising:
a network interface module for connecting said up-link module to a high-speed network:
and an high-speed network for transporting data to and from said uplink module.
a network interface module for connecting said up-link module to a high-speed network:
and an high-speed network for transporting data to and from said uplink module.
57. A logic device for communicating traffic in a line module comprising:
an interface for connecting to a plurality of subscriber links, said interface able to receive available/not-available status from said subscriber links; and an interface for generating a combined cell stream to a WAN up-link device, said interface able to insert a portion into cells in said combined cell stream, said portion indicating status for a plurality of subscriber links.
an interface for connecting to a plurality of subscriber links, said interface able to receive available/not-available status from said subscriber links; and an interface for generating a combined cell stream to a WAN up-link device, said interface able to insert a portion into cells in said combined cell stream, said portion indicating status for a plurality of subscriber links.
58. The device according to claim 57 further comprising:
a second, spare interface for generating a combined cell stream to a WAN up-link device.
a second, spare interface for generating a combined cell stream to a WAN up-link device.
59. A fixed computer readable medium containing computer interpretable instructions describing a circuit layout for an integrated circuit that, when constructed according to said descriptions, will configure a logic apparatus to perform the method described in claim 1.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13495999P | 1999-05-19 | 1999-05-19 | |
| US60/134,959 | 1999-05-19 | ||
| US13668099P | 1999-05-28 | 1999-05-28 | |
| US60/136,680 | 1999-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2308937A1 true CA2308937A1 (en) | 2000-11-19 |
Family
ID=26832845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002308937A Abandoned CA2308937A1 (en) | 1999-05-19 | 2000-05-19 | Method and apparatus for interconnection of flow-controlled communication |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2308937A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003017711A1 (en) | 2001-08-17 | 2003-02-27 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and system for flow control for route switching |
-
2000
- 2000-05-19 CA CA002308937A patent/CA2308937A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003017711A1 (en) | 2001-08-17 | 2003-02-27 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and system for flow control for route switching |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |