CA2301970A1 - Method and system for high speed equalization - Google Patents
Method and system for high speed equalization Download PDFInfo
- Publication number
- CA2301970A1 CA2301970A1 CA 2301970 CA2301970A CA2301970A1 CA 2301970 A1 CA2301970 A1 CA 2301970A1 CA 2301970 CA2301970 CA 2301970 CA 2301970 A CA2301970 A CA 2301970A CA 2301970 A1 CA2301970 A1 CA 2301970A1
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- Prior art keywords
- equalizer
- block
- tap
- sub
- real
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03592—Adaptation methods
- H04L2025/03598—Algorithms
- H04L2025/03605—Block algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03592—Adaptation methods
- H04L2025/03726—Switching between algorithms
- H04L2025/03732—Switching between algorithms according to the convergence state
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0038—Correction of carrier offset using an equaliser
- H04L2027/004—Correction of carrier offset using an equaliser the equaliser providing control signals
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
A system and method that assumes the presence of both pre and post-cursor Inter Symbol Interference (ISI) in the equivalent complex baseband channel impulse response is disclosed. The multipath channel model used in the simulations assumes the presence of multipath components of strength 15 dB down from the peak at ~ 20 ns. The equalizer system includes, an off line equalizer sub-block that operates in block processing mode and performs tap update recursions, and a real-time equalizer sub-block that operates as a fixed tap filter, except at tap updates instants that happen periodically and are up-loaded from the off line equalizer sub-block.
Description
Method and System for High Speed Equalization FIELD OF THE INVENTION
The present invention relates to a method and system for high speed equalization. In particular, the present invention relates to a method and system for compensation of Inter Symbol Interference (ISI) present in a communications signal.
BACKGROUND OF THE INVENTION
An equalizer is employed to compensate for the Inter Symbol Interference (ISI) present in the received signal. The main sources of ISI are the multipath effects introduced by the channel, and the non-linearities in the amplifiers at both the transmitter and the receiver. The choice of the equalizer structure depends on the nature of the channel impairments.
At high data rates such as 1 SS Mbits per second, the highest operating clock frequency of the equalizer becomes close to the data-sampling rate.
Hardware realization of the multipliers and adders result in pipeline delays that are based on the number of hardware clock cycles available for performing computations. Given the maximum operating clock frequency of the system, we have a limited number of hardware clock cycles between consecutive data samples at the higher data rates. Each multiply and add operation inside the feedback loops of the equalizer will therefore, introduce pipeline delays.
The hardware pipeline delay involved in the computation of tap adaptation equations makes real-time tap adaptation unrealizable.
It is therefore desirable to provide a system and method for reducing the computation time of tap adaptation equations to allow tap adaptation to occur in real-time.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a high-speed equalizer system that includes an off line equalizer sub-block that operates in block processing mode and performs tap update recursions. According to a further aspect of the present invention, the equalizer system includes a real-time equalizer sub-block that operates as a fixed tap filter. In yet a further aspect of the present invention, the real-time equalizer sub-block does not operate as a fixed tap filter during tap updates instants that happen periodically, at which time updates are up-loaded from the off line equalizer sub-block.
The system of the present invention compensates for Inter Symbol Interference (ISI) through implementation of real-time and non real-time equalizer sub-blocks within an equalizer system, and the use of Constant Modulus Algorithm (CMA) and Decision-Directed (DD) tap update algorithms.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
Figure 1 is a block diagram of a system incorporating the equalizer system of the present invention;
Figure 2 is a flow diagram showing the synchronization process;
Figure 3 shows the tap update recursion formulas for CMA and DD
modes;
Figure 4 is a block diagram of a system incorporating a real-time and off line equalizer sub-blocks of the present invention;
Figure 5 is a flow diagram showing the operation of the real-time equalizer sub-block of the present invention;
Figure 6 is a flow diagram showing the operation of the off line equalizer sub-block of the present invention;
Figure 7 is a detailed block diagram of the off line equalizer sub-block of the present invention;
The present invention relates to a method and system for high speed equalization. In particular, the present invention relates to a method and system for compensation of Inter Symbol Interference (ISI) present in a communications signal.
BACKGROUND OF THE INVENTION
An equalizer is employed to compensate for the Inter Symbol Interference (ISI) present in the received signal. The main sources of ISI are the multipath effects introduced by the channel, and the non-linearities in the amplifiers at both the transmitter and the receiver. The choice of the equalizer structure depends on the nature of the channel impairments.
At high data rates such as 1 SS Mbits per second, the highest operating clock frequency of the equalizer becomes close to the data-sampling rate.
Hardware realization of the multipliers and adders result in pipeline delays that are based on the number of hardware clock cycles available for performing computations. Given the maximum operating clock frequency of the system, we have a limited number of hardware clock cycles between consecutive data samples at the higher data rates. Each multiply and add operation inside the feedback loops of the equalizer will therefore, introduce pipeline delays.
The hardware pipeline delay involved in the computation of tap adaptation equations makes real-time tap adaptation unrealizable.
It is therefore desirable to provide a system and method for reducing the computation time of tap adaptation equations to allow tap adaptation to occur in real-time.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a high-speed equalizer system that includes an off line equalizer sub-block that operates in block processing mode and performs tap update recursions. According to a further aspect of the present invention, the equalizer system includes a real-time equalizer sub-block that operates as a fixed tap filter. In yet a further aspect of the present invention, the real-time equalizer sub-block does not operate as a fixed tap filter during tap updates instants that happen periodically, at which time updates are up-loaded from the off line equalizer sub-block.
The system of the present invention compensates for Inter Symbol Interference (ISI) through implementation of real-time and non real-time equalizer sub-blocks within an equalizer system, and the use of Constant Modulus Algorithm (CMA) and Decision-Directed (DD) tap update algorithms.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
Figure 1 is a block diagram of a system incorporating the equalizer system of the present invention;
Figure 2 is a flow diagram showing the synchronization process;
Figure 3 shows the tap update recursion formulas for CMA and DD
modes;
Figure 4 is a block diagram of a system incorporating a real-time and off line equalizer sub-blocks of the present invention;
Figure 5 is a flow diagram showing the operation of the real-time equalizer sub-block of the present invention;
Figure 6 is a flow diagram showing the operation of the off line equalizer sub-block of the present invention;
Figure 7 is a detailed block diagram of the off line equalizer sub-block of the present invention;
Figure 8 is a block diagram showing the structure of a complex FIR filter implementation of the equalizer system, according to an embodiment of the present invention;
Figure 9 is a block diagram showing the Constant Modulus Algorithm (CMA) error computation;
Figure 10 is a block diagram showing the Decision Directed (DD) error computation; and Figure 11 is a block diagram showing the tap adaptation process DETAILED DESCRIPTION OF THE INVENTION
The equalizer system is implemented as a complex adaptive filter with 8-taps. The input to the FFE is the complex signal (I and Q channels) from the interpolator block. The FFE taps are also complex values. The equalizer system will operate in symbol-spaced mode. LMS tap update algorithms are employed. Two types of tap update algorithms are implemented. The Constant Modulus Algorithm (CMA) allows initial tap updates in the presence of Garner phase and frequency offset.
The Decision-Directed (DD) tap update mode is implemented to complete the convergence of the equalizer system tap update process. The Garner acquisition mode precedes the equalizer system DD-mode as explained subsequently.
Provisions are also made to bypass/freeze the equalizer system where not needed, such as in satellite communication applications.
Figure 1 shows the equalizer system and its interconnectivity with other blocks.
The equalizer system works in collaboration with carrier recovery system. The equalizer system output is fed to the phase de-rotator. The phase de-rotator de-rotates the received signal constellation to counter the phase and frequency offsets. The Garner recovery block provides the de-rotator with estimates of the angular correction to be applied to the received signal samples.
Figure 9 is a block diagram showing the Constant Modulus Algorithm (CMA) error computation;
Figure 10 is a block diagram showing the Decision Directed (DD) error computation; and Figure 11 is a block diagram showing the tap adaptation process DETAILED DESCRIPTION OF THE INVENTION
The equalizer system is implemented as a complex adaptive filter with 8-taps. The input to the FFE is the complex signal (I and Q channels) from the interpolator block. The FFE taps are also complex values. The equalizer system will operate in symbol-spaced mode. LMS tap update algorithms are employed. Two types of tap update algorithms are implemented. The Constant Modulus Algorithm (CMA) allows initial tap updates in the presence of Garner phase and frequency offset.
The Decision-Directed (DD) tap update mode is implemented to complete the convergence of the equalizer system tap update process. The Garner acquisition mode precedes the equalizer system DD-mode as explained subsequently.
Provisions are also made to bypass/freeze the equalizer system where not needed, such as in satellite communication applications.
Figure 1 shows the equalizer system and its interconnectivity with other blocks.
The equalizer system works in collaboration with carrier recovery system. The equalizer system output is fed to the phase de-rotator. The phase de-rotator de-rotates the received signal constellation to counter the phase and frequency offsets. The Garner recovery block provides the de-rotator with estimates of the angular correction to be applied to the received signal samples.
The phase and frequency corrected samples are fed to the slicer which de-maps the received I and Q samples to generate QAM (or QPSK) symbols. The dicer output feeds the Viterbi decoder via the IQ-generation block.
Upon start-up, the equalizer system taps will be initialized, and the equalizer system will remain idle until sufficient timing phase correction is achieved.
Once, timing recovery is in tracking range, the equalizer system will initiate tap update recursions using the Constant Modulus Algorithm (CMA). CMA is insensitive to carrier offset. The complex phase de-rotator also remains idle until CMA
has converged. When CMA has converged to within acceptable limits as indicated by the equalizer system lock detector, the equalizer system tap updates are frozen and the Garner frequency/phase acquisition process is initiated. After the Garner synchronization loop has compensated for the carrier frequency and phase offsets, the equalizer system will switch to Decision-Directed (DD) tap update mode to achieve satisfactory channel equalization.
The two equalizer system tap update modes, and carrier synchronization loop will operate interactively to reach steady state. This handshake protocol between the equalizer system and carrier recovery will be supervised by the Air Interface Processor (AIP). The synchronization flowchart in Figure 2 shows the synchronization process involving timing recovery, equalization and carrier recovery.
The error for tap adaptation is derived as follows:
CMA-Mode - Y~n)I IYO)I2 -R2 2 for QPSK
R -13.2 for 16 - QAM
y(n) is the complex equalizer system output.
Upon start-up, the equalizer system taps will be initialized, and the equalizer system will remain idle until sufficient timing phase correction is achieved.
Once, timing recovery is in tracking range, the equalizer system will initiate tap update recursions using the Constant Modulus Algorithm (CMA). CMA is insensitive to carrier offset. The complex phase de-rotator also remains idle until CMA
has converged. When CMA has converged to within acceptable limits as indicated by the equalizer system lock detector, the equalizer system tap updates are frozen and the Garner frequency/phase acquisition process is initiated. After the Garner synchronization loop has compensated for the carrier frequency and phase offsets, the equalizer system will switch to Decision-Directed (DD) tap update mode to achieve satisfactory channel equalization.
The two equalizer system tap update modes, and carrier synchronization loop will operate interactively to reach steady state. This handshake protocol between the equalizer system and carrier recovery will be supervised by the Air Interface Processor (AIP). The synchronization flowchart in Figure 2 shows the synchronization process involving timing recovery, equalization and carrier recovery.
The error for tap adaptation is derived as follows:
CMA-Mode - Y~n)I IYO)I2 -R2 2 for QPSK
R -13.2 for 16 - QAM
y(n) is the complex equalizer system output.
DD-Mode - (q(n) - a(n))e'B~n>
where, q(n) : phase de-rotator output, a(n) : slicer output, e'B~"~ : complex conjugate of the phase de-rotator input Figure 3 shows the tap update recursions for both CMA and DD modes.
The effect of hardware pipeline delays on tap updates will now be discussed. The hardware pipeline delay involved in the computation of tap adaptation equations makes real-time tap adaptation unrealizable. Hence, tap adaptations are performed in a non-real-time mode. The equalizer system, as shown in Figure 4 consists of a real-time equalizer sub-block and a non-real-time equalizer sub-block, herein referred to as an off line equalizer sub-block. The off line equalizer sub-block operates in block processing mode and performs tap weight adaptations in non-real-time.
The tap weights are uploaded into the real-time equalizer sub-block at periodic intervals. The real-time equalizer sub-block updates its tap-weights when the AIP indicates to it that a new set of weights are available from the off line equalizer sub-block. After a weight update, the real-time equalizer sub-block operates in its normal operating mode as a fixed-tap FIR filter. Figure 5 shows the operational flow diagram of the real-time equalizer sub-block.
The off line equalizer sub-block will store a block of 1024 samples each from the I and Q channel inputs to the equalizer system. Once the block of 1024 samples are saved, the block mode equalizer will perform tap update recursions. The block mode tap update recursions for the 1024 I and Q samples will take 20 blocks of 1024 samples.
Once a set of tap weights are ready, the air interface processor will indicate to the real-time equalizer sub-block to upload its taps. This process continues until the off line equalizer sub-block lock detector indicates that tap adaptation convergence has reached.
This process is illustrated in the flowchart of Figure 6. In CMA mode, off line equalizer sub-block will only require 1024 samples each from I and Q channels for tap updates.
However, in DD-mode, the tap update recursions require the phase/frequency correction ( e'B~"~ ) that is applied at the phase de-rotator by the carrier recovery system. Therefore, when we store 1024 I and Q samples for off line processing in DD-mode, we have to save the corresponding e'B~"~ samples as well. The dependency of DD-mode (off line) tap updates on e'B~"~ is shown in Figure 3.
Figure 7 shows the structure of the off line equalizer sub-block. Figure 8 shows the structure of the complex FIR filter implementation of the equalizer system.
The error computation blocks in Figures 9 and 10 give the relevant bus-widths for computation of equalizer system error for both CMA and DD modes of operation. The tap adaptation process is illustrated in Figure 11.
The above-described embodiments of the invention are intended to be examples of the present invention. Alterations, modifications and variations may be effected the particular embodiments by those of skill in the art, without departing from the scope of the invention which is defined solely by the claims appended hereto.
where, q(n) : phase de-rotator output, a(n) : slicer output, e'B~"~ : complex conjugate of the phase de-rotator input Figure 3 shows the tap update recursions for both CMA and DD modes.
The effect of hardware pipeline delays on tap updates will now be discussed. The hardware pipeline delay involved in the computation of tap adaptation equations makes real-time tap adaptation unrealizable. Hence, tap adaptations are performed in a non-real-time mode. The equalizer system, as shown in Figure 4 consists of a real-time equalizer sub-block and a non-real-time equalizer sub-block, herein referred to as an off line equalizer sub-block. The off line equalizer sub-block operates in block processing mode and performs tap weight adaptations in non-real-time.
The tap weights are uploaded into the real-time equalizer sub-block at periodic intervals. The real-time equalizer sub-block updates its tap-weights when the AIP indicates to it that a new set of weights are available from the off line equalizer sub-block. After a weight update, the real-time equalizer sub-block operates in its normal operating mode as a fixed-tap FIR filter. Figure 5 shows the operational flow diagram of the real-time equalizer sub-block.
The off line equalizer sub-block will store a block of 1024 samples each from the I and Q channel inputs to the equalizer system. Once the block of 1024 samples are saved, the block mode equalizer will perform tap update recursions. The block mode tap update recursions for the 1024 I and Q samples will take 20 blocks of 1024 samples.
Once a set of tap weights are ready, the air interface processor will indicate to the real-time equalizer sub-block to upload its taps. This process continues until the off line equalizer sub-block lock detector indicates that tap adaptation convergence has reached.
This process is illustrated in the flowchart of Figure 6. In CMA mode, off line equalizer sub-block will only require 1024 samples each from I and Q channels for tap updates.
However, in DD-mode, the tap update recursions require the phase/frequency correction ( e'B~"~ ) that is applied at the phase de-rotator by the carrier recovery system. Therefore, when we store 1024 I and Q samples for off line processing in DD-mode, we have to save the corresponding e'B~"~ samples as well. The dependency of DD-mode (off line) tap updates on e'B~"~ is shown in Figure 3.
Figure 7 shows the structure of the off line equalizer sub-block. Figure 8 shows the structure of the complex FIR filter implementation of the equalizer system.
The error computation blocks in Figures 9 and 10 give the relevant bus-widths for computation of equalizer system error for both CMA and DD modes of operation. The tap adaptation process is illustrated in Figure 11.
The above-described embodiments of the invention are intended to be examples of the present invention. Alterations, modifications and variations may be effected the particular embodiments by those of skill in the art, without departing from the scope of the invention which is defined solely by the claims appended hereto.
Claims
1. An equalizer system comprising:
a non real-time equalizer for performing tap update recursions;
a real-time equalizer for receiving tap updates from the non real-time equalizer.
a non real-time equalizer for performing tap update recursions;
a real-time equalizer for receiving tap updates from the non real-time equalizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2301970 CA2301970A1 (en) | 2000-03-22 | 2000-03-22 | Method and system for high speed equalization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2301970 CA2301970A1 (en) | 2000-03-22 | 2000-03-22 | Method and system for high speed equalization |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2301970A1 true CA2301970A1 (en) | 2001-09-22 |
Family
ID=4165613
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2301970 Abandoned CA2301970A1 (en) | 2000-03-22 | 2000-03-22 | Method and system for high speed equalization |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8111740B2 (en) | 2005-12-29 | 2012-02-07 | Triductor Technology (Suzhou) Inc. | Time-domain equalizer |
-
2000
- 2000-03-22 CA CA 2301970 patent/CA2301970A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8111740B2 (en) | 2005-12-29 | 2012-02-07 | Triductor Technology (Suzhou) Inc. | Time-domain equalizer |
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