CA2301480A1 - Broadband wireless modem - Google Patents

Abstract

A programmable integrated circuit device for wireless modems is disclosed. The integrated circuit has an architecture that allows specific digital blocks to be programmed in order to allow the device to function with different wireless communication standards.

Description

Broadband Wireless Modem FIELD OF THE INVENTION
The present invention relates to a digital ASIC for a broadband wireless modem. In particular, the present invention relates to an architecture for a digital ASIC in a broadband wireless modem .
BACKGROUND OF THE INVENTION
Digital ASICs (Application Specific Integrated Circuits) of the prior art are not programmable and cannot conform to different protocols and handle different data formats when incorporated into telecommunication devices such as broadband wireless modems. The design and fabrication of such ASICs is typically customized for a single product offering from a single client, who requires specific technical features from the ASIC. If future products must incorporate new technical features, or use existing technical features that were chosen not to be implemented due to costs or other considerations, a new ASIC design must be developed and manufactured.
This can be particularly expensive when the new technical feature to be added only requires minimal design changes. In the competitive ASIC market where more advanced products are released each year, the turnaround time for producing the next ASIC design becomes a critical window for success of the product. Although the next device in the same family of ASICs may recycle the standard blocks of the previous device, the engineering man hours, manufacturing and testing costs for the new device become significant.
It is therefore desirable to provide an ASIC device for modems, which can cost-effectively, and quickly be adapted for many existing or future technical features. It is further desirable to provide a programmable ASIC device, customizable for different technical requirements, that does not require re-design or re-manufacturing of the ASIC.

SUMMARY OF THE INVENTION
It is an object of the present invention to provide a programmable ASIC. It is a filrther object of the present invention to provide a broadband wireless modem having an air interface for configuring data for transmission, a modulator for modulating data and a demodulator for demodulating data.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:
Figure 1: Top Level Block Diagram Figure 2: ASIC Clocking Diagram Figure 3: Satcom Terminal Configuration Example Figure 4: Event Handler/Sequencer Interaction Figure 5: Preamble Insert Delayed Time Reference Figure 6: Event Handler Instruction Set Summary Figure 7: Event Handler ALU Opcodes Figure 8: Event Handler Branch Conditions Figure 9: Register Access Instructions Figure 10: Data Scheduling Instructions Figure 11: Burst Descriptor Instruction Figure 12: Modulator Burst Info Field Format Figure 13: Demodulator Burst Info Field Format Figure 14: Processor Wait Instruction Figure 15: Microsequencer Instruction Set Figure 16: Configuration of condition codes and fork Figure 17: Modulator Top Level Block Diagram Figure 18: Scrambler functional diagram Figure 19: Interleaver Block Diagram Figure 20: Convolutional Encoder Block Diagram Figure 21: Rate 2/3 (4/6) default puncturing pattern = OO100010xxxxxxxx Figure 22: Rate 3/4 default puncturing pattern = 001001 xxxxxxxxxx Figure 23: Rate 5/6 default puncturing pattern = OO10011001xxxxxx Figure 24: Rate 7/8 default puncturing pattern = OOl OlO10011001xx Figure 25; Demodulator Top Level Block Diagram Figure 26: Slices Output Encoding Figure 27: Slices Figure 28: IQ Generator Symbol Rotation Figure 29: Reed-Solomon encoder module block diagram Figure 29a: Pulse Width Modulator block diagram Figure 29b: Input Queuing block diagram Figure 29c: Frame Formatter block diagram Figure 29d: Scrambler block diagram Figure 30: CRC Generator block diagram Figure 31: Interleaves block diagram Figure 32: Parallel-to-serial Converter block diagram Figure 33: Convolutional Encoder block diagram Figure 34: Code Puncture block diagram Figure 35: Preamble Insert block diagram Figure 36: Mapper block diagram Figure 37: Differential Encoder block diagram Figure 38: Modulator Root Raised Cosine Filter block diagram Figure 39: Demodulator Root Raised Cosine Filter block diagram Figure 40: Ranging block diagram Figure 41: Differential Decoder block diagram Figure 42: IQ Generator block diagram Figure 43: Convolutional (Viterbi) Decoder block diagram Figure 44: Sync Detect block diagram Figure 45: Serial to Parallel block diagram Figure 46: Deinterleaver block diagram Figure 47: Reed-Solomon Decoder block diagram Figure 48: CRC Verifier block diagram Figure 49: Descrambler block diagram Figure 50: Address Filter block diagram Figure S 1: Output Queuing block diagram Figure 52: Cell delineation state diagram DETAILED DESCRIPTION OF THE INVENTION
The above-described embodiments of the invention are intended to be examples of the present invention. Alterations, modifications and variations may be effected the particular embodiments by those of skill in the art, without departing from the scope of the invention which is defined solely by the claims appended hereto.
The SpaceBridge SB7016 Digital Modem ASIC is part of a three-chip set, consisting of the SB7016, the SB7040, an integrated I-Q up converter, and the SB7041, an integrated I-Q down converter.
The SB7016 is designed to interface with an external PowerPC processor, such as the Motorola MPC860 or MPC8260. Application software, running on the PowerPC, is used to configure the SB7016 to the desired air interface protocol, and to enable all required error control coding functions. Data access with the SB7016 is supported using the on-chip Utopia controllers for ATM traffic, and using the PowerPC interface for all other kinds of data, such as IP.
The SB7016 contains all the functions required to operate in either terminal or base station/hub mode. The SB7016 provides burst modulator and continuous demodulator features applicable to terminal mode operation, with all the required error control coding functions. It also provides burst mode demodulation and continuous mode modulation for base station applications. Since the modulator and demodulator are both programmable, the SB7016 may also be used for variants of these basic configurations. For example, it can be configured for continuous mode operation in both modulation and demodulation paths.
Both the Modulator and Demodulator portions of the SB7016 have special-purpose processors that are designed with the intention of allowing the Modem to meet many air interface standards.
The Air Interface Processor is divided into a transmit-side and receive-side unit. Each processor unit consists of an Event Handler and a Microsequencer.
The Event Handler provides an abstraction of the Burst Frequency Time Plan. The Microsequencer controls how data is formatted by the Modulator/Demodulator circuitry.

For the remainder of the description, the following notation is used for numbers:
Verilog notation (w'Bdddd) used for unsigned numbers:
~ 'w' denotes the width of the number, in bits ~ 'B' denotes the base of the number, and is one of the following:
~ b = binary ~ o = octal ~ d = decimal ~ h = hexadecimal ~ 'd' are the digits representing the number; underscores ('_') are for readability, and have no meaning SPW notation (<w, i, t>) used for fixed-point numbers:
~ 'w' denotes the width of the number, in bits ~ 'i' denotes the number of bits for the integer portion of the number ~ 't' is either "t" for 2's complement, or "u" for unsigned For example, <11,2,t>:

The following notation will be used for registers:
S ~'i, '~ ~ 7 ,PI' R ' ~~~ ~~ ~~ ~I'~ '%' ~y 3 Re Inter Is readable W Re aster is writeable E The register is located in an external VHDL module (le. not the regfle).

This Is meanln less for software a ores.

S Reading or writing this register creates a read or write strobe for use by external VHDL modules.

This is meanin less for software ur ses.

P This fs a "pulse" register. Writing to this register causes the new value to be valid for one clock cycle, after which the re inter returns to its default value.

All register addresses are shown as offsets into a virtual address space. A
top level block diagram of the digital ASIC of the present invention is shown below in Fig. 1.

digital I
digital Q
I sample Q sample data for I sample from external ADC
Q sample from external ADC
analog I
analog Q
PowerPC Bus Utopia TX/RX
Figure 1: Top Level Block Diagram The ASIC clocking diagram is shown in Fig. 2 below.
dds ref dk (rwminal 4'f MHz oscillator) dds_syn clk_aut mod b~ dk_out dpll_m~ ref_dk dpll_de~nod_ref_dk Figure 2: ASIC Clocking Diagram mod_samp_dk_out demad_byte dk_out denod_bit_dk_out demod_samp_dk_out All clocks used internally by the ASIC come from input pins. No clocks are derived and used internally. A number of circuits are present (shown above) which can derive and synthesise clocks; those outputs must be looped out from output pins and back into the appropriate input. Clocks that are looped around are inverted at the input pad in order to gain more timing margin.
In terminal mode, all modulator and demodulator clocks are ultimately derived from dds ref clk. This clock is an oscillator that is running at nominally 4 times the network clock rate. The Network Synchronization Algorithm uses, for example, the PCR count in order to derive a very stable reference clock that matches the reference oscillator used on the satellite/hub/base station.
In base station mode, the Network Synchronization Algorithm is generally not required.

The ASIC provides 4 on-chip PLLs, which can be programmed through the processor interface. The PLLs used are AZ_PLL71FS macrocells from ST
Microelectronics. These have a programmable output frequency from 6.25 MHz to 622 MHz, and a loop bandwidth of 35 kHz.
The parameters and constraints of interest are:
F(clock _ out) _ ~ ~. ~ F(clock _ in) F(clock-in) _< 200MHz 1_<M<_255 1<_N<_255 0<_P<_5 lMHz _< F(cl M -tn) ~ 2MHz Phase comparator limit 200MHz <_ ~ F(clock_in) <_ 622MHz vCO limit Refer to the ST datasheet for more detailed information.
The PLLs are used to generate the sampling and bit clocks on the Modulator and Demodulator. There is a spare PLL (not shown) for debugging purposes.
The range of the PLLs is not sufficient for low-bit-rate application. For this reason, a bank of 2N clock dividers is included; the value of N is programmable from 0 to 9 through the processor interface. Given a 6.25 MHz clock generated by one of the PLLs, this divider allows the clock to be divided down to approximately 6.1 kHz.
The Modulator portion of the chip has two clock domains: mod byte clk and mod samp clk, which are the byte and sampling clocks, respectively.
The Modulator Sampling clock is locked to the system's reference oscillator. Its frequency is directly related to the data rate of the modulator. The Modulator Byte clock is derived from the Sampling clock, using one of the Numerically-Controlled Clock Divider circuits.

The clocking of the Modulator is quite straightforward. Over the duration of a "burst" of data, the samples provided to the DAC must be continuous (at the "sampling rate"). The number of samples per symbol is fixed depending on the modulation type (2 for QPSK, 4 for 16-QAM); the number of samples per byte is therefore fixed, regardless of modulation type:
4 symbols/byte * 2 samples/symbol = 8 samples/byte for QPSK
2 symbols/byte * 4 samples/symbol = 8 samples/byte for 16-QAM
The Convolutional Encoder imposes an additional overhead to the data rate (C:
2 for rate %z, 8/7 for rate 7/8, etc.). The frequency of the Sampling clock is therefore D*C*8, where D is the data rate in bytes per second, after all frame encoding overheads have been factored in.
The frequency of the Byte clock is simply D/8.
~ Modulator Sampling Clock ~ Target frequency for synthesis will be 250 MHz. This gives 155 Mbps at rate=2/3 for 184 data bytes with 20 bytes overhead (RS(204, 188), MPEG2 frame).
~ This clock is locked to the system's reference oscillator.
~ The Modulator Sampling Clock is not necessarily the same as the Demodulator Sampling Clock.
~ Modulator Byte Clock ~ This clock is derived from the Modulator Sampling Clock, which in turn is locked to the system's reference oscillator.
~ The transition points are at the Input Queuing module and Parallel-to-Serial Converter.
~ Target frequency for synthesis will be 33 MHz. This is derived from the following relationship, leaving plenty of margin for frame formatting and encoding overhead.

bit ' rate~RS _ overhead ~ frame _ overhead bits _ per _ byte The Demodulator portion of the chip has three clock domains:
demod samp clk, demod bit clk, and demod byte clk. The clocking structure of the Demodulator is considerably more complicated than that of the Modulator.
On Revision A0, the Demodulator Sampling Clock was always 2 samples per symbol. Starting with Revision A1, this is no longer the case; the number of samples per symbol is now programmable. When running at low data rates, using a higher number of clocks per symbol allows us to avoid the pipeline delay problem.
Following are descriptions of the demodulator clocks.
~ Demodulator Sampling Clock ~ The target frequency for synthesis will be 250 MHz. This allows for two samples per symbol at the highest supported combination of data rate and encoding (155 Mbit/s @ 2/3 encoding).
~ This clock is locked to the system's reference oscillator.
~ Demodulator Bit Clock ~ This is an intermediate clock between the demodulator circuitry and the Viterbi decoder. The target frequency for synthesis will be 200 MHz, which is the maximum user data rate, with 30% margin for frame formatting overhead.
~ This clock is locked to the system's reference oscillator.
~ The transition points are at the Depuncturing module and Serial-to-Parallel Converter.
~ Demodulator Byte Clock ~ Byte clock similar to the one on the Modulator. Target frequency is 33 MHz.
~ The transition points are at the Output Queuing module and Serial-to-Parallel Converter.
Following are descriptions of other clocks.
~ DDS Reference Clock ~ This clock is an oscillator running at 4 times the network clock. For DVB/MPEG systems, it is a 27*4=108 MHz oscillator.
~ Utopia TX clock ~ Utopia RX clock ~ These clocks are driven externally by the ATM-layer function that accesses the Utopia ports on this device. Max frequency is 50 MHz.
~ It is assumed to be totally asynchronous to everything else in the system.
Transition point is at Input FIFO and Output FIFO.
Processorinterface clock The local bus clock for the MPC860/MPC8260 processor, driven by the processor.
~ It is assumed to be totally asynchronous to everything else in the system.
The following example illustrates a typical application of the SB7016 in a satcom terminal product.
In this example, the downstream data rate is 60 Mbit/s with rate %2 convolutional encoding. The upstream data rate is 2 Mbit/s, also with rate I/z convolutional encoding. QPSK modulation is used in both directions. The modulator and demodulator clocks are tied to a 27 MHz reference clock which is derived using the PCR algorithm. The terminal uses a 108 MHz oscillator to derive a stable MHz reference from the data stream (O DDS SYN CLK OUT).
Using this information, we can determine the required frequencies for ~ mod sump clk and demod samp clk:
mod samp_clk = 2 M * 2 = 4 MHz demod samp clk = 60 M * 2 = 120 MHz demod bit clk = 60 MHz The O DDS SYN CLK OUT is the derived 27 MHz reference. It will be used as the input to the PLLs. It is looped back in to the I DPLL MOD REF CLK
and I DPLL DEMOD REF CLK pins.

The 4 MHz required for mod samp clk is too low for the PLL; instead, we will target 16 MHz, which can be attained by choosing M=27, N=128, and P=4.
This 16 MHz clock can then be divided by 2 using one of the divide-by-2N inputs, and then again by 2 using the NCCD to get the target 4 MHz.
To get 120 MHz from the PLL with an input frequency of 27 MHz, we choose M=18, N=80, and P=1. In this case, we will not need to use the divide-by-2 feature of the NCCD to get the sampling clock. We need to account for this when programming the NCCD to get the byte clock.
The 60 MHz demod bit clk 'can be had by choosing M=18, N=80, and P=2.
The NCCD modules generate the byte clocks. For the mod byte clk signal, we use a delta value of 4 (9'b0100 00), which gives a clock with 32 periods of I MOD NCCD_CLK on the O MOD BYTE CLK OUT pin. The O MOD SAMP NCLK OUT pin has a clock with 2 periods of I MOD NCCD CLK. These two are to be used as I MOD BYTE CLK and I MOD S~ CLK, respectively.
For the demod byte clk signal, we use a delta value of 8 (9'b1000 00) to generate a O DEMOD BYTE CLK OUT with 16 periods of I DEMOD NCCD CLK. In this case, we are using I DEMOD NCCD CLK as I MOD SAMP CLK as well.
Fig. 3 below illustrates a typical application of the SB7016 in a satcom terminal product.

MHz LDDS_REF 0_MOD_BVTE_CLILOUT
CLK

O_MOD_SAMP_NCLILOUT

0_DDS_SYN_CLILOUT

I_DPL~MOD_REF_CLK0_DEMOD_BYTE_CLILOUT

I_DP~.~DEMOD_REF_CLICO_DEMDD_SAMP_NCLILOUT

0_DEMOD_BIf_NCLILOUT

O_DEMOD_SAMP_Ctl(.OUT

O_DEMOD_BIf_CLILOUTLMOD_BVTE_ClK _ O_MOD_SAMP_CLILOUTI_MOD_SAMP_CLK SB7O4O

I_MOD_NCCD_Cl!(LDEMOD_BVTE CL1C _ I_DEMOD_NCCD_CLKL DES S1MP_ClJ( SB7O4I~

SB7OZE LDEMOD_8)T_CU( I_DN2NClILO
[Clock Modell I_DN2NCL1(.l I_DN2NCLIL,2 O DN2NCU(OUT

O_DN2NClKOUT_1 O_DN2NCLKOUT_2 O_DN2NG.ICOUT_3 MHz MPC860SAR L xro_cuc LnLCUc I_wc_cuc I PWMCLx Figure 3: Satcom Terminal Configuration Example The following example illustrates a typical application of the SB7016 in a LMDS base station product.
The SB7016 Modulator can operate in either continuous mode or burst mode. Continuous mode is treated as a subset of burst mode.
Rather than developing complex state machines that track frame structures, timeslots, and mini-timeslots, the SB7016 abstracts all frame formats to a single, simple concept: We want to transmit a certain amount of data at a certain time. A
similar concept is used in the Demodulator.
We introduce the notion of an abstract "Super-Frame", which starts at time 0. The start of a Super-Frame is keyed off a "Super-Frame Strobe", which may be derived from the PCR algorithm, or some other system event. The duration of the Super-Frame is N samples (programmable, up to 232). In continuous mode, we program the modulator to process data between time O...N; in burst mode, we program the modulator to process data over any subset of time 0.. .N. We will refer to any data processed as a "burst" of data; continuous mode is simply two seamless "bursts", back-to-back.

At the core of the Modulator is the Modulator Air Interface Processor (AIP), which is responsible for initiating the data processing required for bursts of data. It consists of an Event Handler and a Sequences. The Event Handler schedules bursts of data, under software control. It maps the time of a burst to a burst format.
The Sequences actually build the data stream by sending commands to the Frame Formatter. The sequence of commands sent to the Frame Format determines the burst format.
In burst mode, the Event Handler is continuously modified by software in Burst Mode, depending on the Burst Frequency Plan. In continuous mode, the Event Handler simply repeats the Frame format.
The Sequences is configured by software at startup, and is static. This is because the types and formats of frames in a system and generally fixed.
TS TS BOD
t=107 t=394 t=768 t=0 t=0 Event Handler Sequences Time Sequence SequenceActions t=107 TS TS send header t=394 TS send 1 ATM
cell t=768 BOD add RS encoding BOD send header send 3 ATM
cells add RS encoding Figure 4: Event Handler/Sequencer Interaction The Frame Formatter receives commands from the AIP. These commands instruct the Frame Formatter to insert special constants ("Control Words") in the data stream, or to pull data out of one of the data queues in the Input Queue and insert them in the data stream. The Frame Formatter also tags each byte with a specific attribute, which determines whether or not that byte is to be scrambled, and whether or not and CRC or Reed-Solomon encoding is to be performed.
Data from the Frame Formatter is "streamed", which means that bursts of data are built up on the fly. The data burst is not assembled off line beforehand, and then transmitted.
For accurate burst synchronization, one important issue must be resolved.
Much of the Modulator (including the AIP), runs off a byte clock; however, burst times are typically specified in terms of samples or symbols. A special module called Preamble Insert compensates for this lack of precision.
Apart from actually inserting the preamble, the Preamble Insert module contains a small FIFO. Data is streamed from the Frame Formatter, and arnves at the FIFO slightly before it is due to leave. The burst data is then delayed until the precise transmission time.
The Preamble Insert module uses a time reference that is a delayed version of the one used by the AIP. The amount of time by which the reference is delayed is programmable, and depends on the FEC functions that are enabled in the Modulator chain, and the ratio of the sampling clock to byte clock.
Note that the Preamble Insert module is not required for continuous mode, because burst synchronization is not an issue.

AIP Time Reference Preamble Insert Time Reference 'PD
Modulator Pipeline Delay ~ programmable ~ depends on which blocks are active Figure 5: Preamble Insert Delayed Time Reference The Event Handler is a fairly general-purpose processor that can do much more than simply map times to bursts of data. Its instruction set consists of ALU &
Branch instructions, Data Scheduling instructions, Register Access instructions, and special instructions.
Like the Modulator, the SB7016 Demodulator can also operate in either continuous mode or burst mode. Unlike the Modulator, there are some significant differences between continuous mode and burst mode.
The same Event Handler/Sequencer structure appears in the Demodulator.
On the Demodulator, the Sequences sends commands the Frame Deformatter. The Frame Deformatter performs simple pattern matching (instead of data insertion). Like the Frame Formatter on the Modulator, it also tags each byte with a specific attribute, which determines whether or not that byte is to be descrambled, and whether or not and CRC or Reed-Solomon decoding is to be performed. Furthermore, each byte is tagged with a flag indicating whether or not it should be sent to the Output Queue, and if so, in which queue it should be saved.

The issue of burst synchronization exists on the Demodulator as well. Its solution is a little more complicated than on the Modulator, however. In the Demodulator, there are actually three time references. The Event Handler runs off the master time reference, which is dubbed "AIP Time". The front-end burst demod circuitry runs off a slightly delayed version of that, and is dubbed "Current Time".
Finally, the Sequencer runs on much more delayed version, which is dubbed "Delayed Time".
The Current Time is used to open a window during which the burst demod knows to expect data. The Delayed Time is used to process data once it is ready to go to the Reed-Solomon Decoder and Descrambler. This can be a substantial amount of time relative to the actual burst length. The Demodulator AIP queues up the execution times and sequencer program addresses to avoid losing any bursts of data inside the Demodulator chain.
The SB7016 powers up with Modulator, Demodulator, and clock dividers all in the reset state. The software must program the appropriate RESET N
registers to 1 in order to bring the functions out of reset.
A version register is also provided to distinguish between different revisions of the chip.
0x00000004 Modulator Reset n R/W

default value = 1'b0 access macro = CFG MOD RESET N x 0x00000008 Modulator Clock Divider Reset n R/W

default value = 1'b0 access macro = CFG MOD CLKGEN RESET
N x Ox0000000C Demodulator Reset n ! R/W

default value = 1'b0 access macro = CFG DEMOD RESET N x 0x00000010 Demodulator Clock Divider Reset n R/W

default value = 1'b0 ' access macro = CFG DEMOD CLKGEN RESET
N x 0x00000018 SB7016 Version R/E

default value = 32 bits access macro = CFG VERSION x Both the Modulator and the Demodulator have special-purpose processors that are designed with the intention of allowing the Modem to meet any air interface standard. However, it is impossible to predict whether all forthcoming LMDS
and SatCom systems can be handled. For any systems which cannot be handled directly, there will be a provision to bypass internal FEC generation/correction and process a raw bit stream.
The Air Interface Processor is divided into a transmit-side and receive-side unit. Each Processor Unit consists of an Event Handler and a Microsequencer.
The Event Handler provides an abstraction of the Burst Frequency Time Plan; the Microsequencer controls how data is formatted by the Modulator/Demodulator circuitry.
The configuration of the Microsequencer is intended to be static during the course of operation (though this is not a necessary condition). The Event Handler configuration is static for continuous mode operation, and dynamic for burst mode to accommodate varying Burst-Frequency Time Plans.
The primary purpose of the Event Handler is to schedule the processing of burst data transmission/arrival in the Modem. (Continuous data is treated as a special subset of burst data.) In addition to being able to initiate sending/receiving bursts of data, the Event Handler has the ability to perform various ALU operations, and to perform conditional or unconditional branches. The ALU and branch operations are performed simultaneously, which allows for greater code density than would otherwise be possible.
The instruction set is divided into general purpose and modem control instructions. There are 8 16-bit readlwrite registers, and 8 16-bit read-only registers.
All instructions occupy one 48-bit word in memory. The instruction set summary is shown below.

Type0 Rd operand branchpass fall 1 0 Rn 2 address address ALU
S

o code code T 0 Rhi - 32-bit data a 1 Rlo T 0 Rhi Imm 32-bit data a 1 l0 T 0 Rhi - Rlo - Rd a 1 T 0 R hiImm - Rd a 1 to Type1 0 Microsequencer trigger 6 T time D
Q

address T 1 0 - burst Info a 1 T 1 A1 - mask a - 1 Instruction Type 1: ALU Operations Instruction Type 2: Write register Instruction Type 3: Write register Immediate Instruction Type 4: Read register Instruction Type 5: Read registerimmediate Instruction Type 6: Trigger Instruction Type 7: BURST
Instruction Type 8: WAIT
[A='0' -~ until any of (R12 and mask) bits are set]
[A='1' ~ until all of (R12 and mask) bits are set]
Figure 6: Event Handler Instruction Set Summary The Event Handler memory is a single-port, synchronous, 1K * 48 RAM.
General-purpose instructions (bits 47:46=00) are comprised of an ALU
instruction and a two-way branch instruction. The ALU instructions are reminiscent of the ARM RISC processor, in that the second operand always passes through a programmable barrel shifter before being applied to the ALU.
For each operation, the ALU computes a new result and the flags associated with that result (N=negative, Z=zero, C=carry, V=overflow). The results of the ALU
operation are stored in the destination register only if the 'W' flag is asserted for that instruction. The ALU flags are updated only if the 'S' flag is asserted.
The results of the ALU operation are written to a destination register (Rd).
The destination register may be any of the 8 read/write registers (RO-R7).
Operand 1 (Rn) is always a register, and may be any of the 16 registers. Operand 2 is either an immediate value (I=1) or a register value (I=0), and is passed through a programmable barrel shifter to yield a 16-bit result.

Immediate mode ( 16 bit result) ~'~~ ~~~1~~ s ~~I''1'il~~e' i,,ii ' ':I~
shift by val shift(op2) = LSL ( val, shift_by ) Register mode 0 (16 bit result) I shift_by 0 t~
I 0 i type I I
I

shift(op2) Rm,shift_by) if _ ~sL ( type=0 LSR ( Rm,shift_by) if type=1 ASR ( Rm,shift_by) if type=2 RoR ( Rm,shift_by) if type=3 Register mode 1 ( 16 bit result) I Rs I 0 I Rm type I

I

shift_by 0) = Rs<3 downto shift(op2) shift_by) if = LSL type=0 ( Rm, ASR shift_by) if ( Rm, type=1 ,45R shift_by) if ( Rm, type=2 RoR shift_by) if ( Rm, type=3 In general, each ALU instruction performs the following operation:
result = fn(Rn, shift(op2)) Rd <= result if w else no change {N,z,c,v} <= flags(result) if 5 else no change The following operations are supported:

0000 AND Bitwise vector AND
Rd := Rn AND o 2 0001 XOR Bitwise velar XOR
Rd := Rn XOR o 2 0010 SUB Subtract Rd := Rn - 0 2 0011 RSB Reverse Subtract Rd := 0 2 - Rn 0100 ADD Add Rd:=Rn+o 2 0101 ADC Add w/ Carry Rd:=Rn+o 2+C

0110 SBC Subtract w/ Carry Rd:=Rn-o 2-NOTC

0111 RSC Reverse Subtract w/
Carry Rd:=a 2-Rn-NOTC

1000 OR Bitwise vector OR
Rd:=RnORo 2 1001 BIC Bit Clear Rd := Rn AND NOT o 2 1010 INT Ralse Interru t 1011 reserved 1100 reserved 1101 reserved 11 reserved _ T reserved _ _ dill Figure 7: Event Handler ALU Opcodes The branch component of the instruction allows a conditional branch to happen based on the result of the previous ALU instruction. Each branch instruction has an address offset to jump to in the case the condition passes, and a separate address offset to jump to in the case the condition fails. This mechanism only allows for relative branches.

The following branch codes are supported:

0000 JEQ equal Z

0001 JNE not equal !Z

0010 JCS unsigned higher or same C

0011 JCC unsigned lower ~C

0100 JMI negative N

0101 JPL positive or zero ~N

0110 JVS overflow V

0111 JVC no overflow !V

1000 JHI unsigned higher C & !Z

1001 JLS unsigned lower or same !C Z

1010 JGE greater than or equal N&V !N&!V

1011 JLT less than N&!V !N&V

1100 JGT greater than !Z& N&V+!N&!V

1101 1LE less than or equal Z&N&!V+!N&V

1110 JMP unconditional 1111 ~ ~ reserved Figure 8: Event Handler Branch Conditions Register Access instructions (bits 47:46=O1) are provided to allow reading or writing arbitrary registers within the Modem. The Modulator Air Interface Processor can only control registers within the Modulator, and the Demodulator Air Interface Processor can only control registers within the Demodulator.
This facility is used to enable/disable internal ASIC blocks, and to control external devices that need to be manipulated on a real-time basis, such as RF
frequency select for MF-TDMA systems. It is not intended for static configuration, which is better handled via the processor interface (although it can be performed here as well).
T a 0 Rhi 2 1 Rlo 0 32-bit 0 data T 3 0 Rhl 2-bit ta 1 Imm da 0 l0 T a 0 Rhi Rlo Rd T 5 0 Rhl Rd 1 Imm 1 to Figure 9: Register Access Instructions Rhi provides the top 16 bits of the 24 bit address. Rlo (bit 44=0) or imm_lo (bit 44=1) provides the bottom 8 bits. For a write operation (bit 45=0), the 32 bit data is contained directly in the lower bits of the instruction. For a read operation (bit 45=1), the bottom 3 bits encode the number of the destination register.
The register access occurs over the internal HCPU bus.
Data Scheduling instructions (bit 47=1) are the means by which bursts of data are transmitted or received by the Modem.
Each of these instructions is an entry that maps time indices to actions.
Time indices are specified in clock ticks relative to the start of a super-frame. Time index 0 is determined via the PCR algorithm (PCR offset). Actions are pointers to microcode instruction sequences. With this scheme, it is not necessary to count frames or even timeslots, only superframes.
Figure 10: Data Scheduling Instructions For the execute phase of a data scheduling instruction, the Event Handler will wait until the current time (time index relative to super-frame start) is approximately equal to the trigger time. (It can only wait for the times to be approximately equal because the Event Handler runs off the byte clock, whereas the current time is a counter that runs off the sample clock.) When the trigger time is reached, a start command is sent to the Microsequencer, which will begin running at the address specified in "microsequencer address".
A time offset of 32'hFFFF FFFF is a special code indicating that this event is to be processed immediately. The microsequencer address 0 is a special code indicating that the start command should not be sent.
If the trigger flag is set, the time offset in the current event is passed to the Preamble Insert module in the Modulator, or Direct Sampling module in the Demodulator.

Bursts can be conditional on the availability of data in a certain queue. In this case, the 'D' flag must be set to 1, and 'Q' must be set to the number of the data queue which must contain data (0 -~ DATA1, 1 ~ DATA2, etc).
For burst mode applications, the AIP provides a special BURST instruction which is used to specify special information related to the following burst of data.
i I ~I'~II~~ ,ri I i ~ I ~~ ~ Ipi ~ ~'~ ~i ~ 'i ~~~ I' I~~I~i ~' ~I~,~ III i II II~~~ ~~~~i ~Il~lll~i l~Ilir ~~~ (li ' ~', i I I f i 1 T a 7 1 - 0 1 - burst info Figure 11: Burst Descriptor Instruction The contents of the burst info field are different for the modulator and demodulator.
For the modulator, this field is used to select which preamble is to be used for the following burst (PS). Up to four preambles may be defined. For MF-TDMA
applications, the burst info field contains frequency information that is used to reprogram the DDS or Fractional-N counter.
Figure 12: Modulator Burst Info Field Format For the demodulator, the burst info field is used to select the expected preamble for the incoming burst (PS). Up to four preambles may be defined. It also contains the length of the expected burst. The SB7016 tags all incoming bursts with an arbitrary user ID, which the MAC layer software can use to correlate received bursts with expected bursts in the BFTP. The user ID is specified in the burst info field.
Figure 13: Demodulator Burst Info Field Format Processor wait instructions are shown in Fig. 14.
! f i 9 ~ !~4f~ II
I ilii I~~
T a S 1 - A 1 1 - mask Figure 14: Processor Wait Instruction The Microsequencer is responsible for sending commands to the Frame Formatter. On the Modulator, this builds up a frame of data on a byte-by-byte basis.
The core of the Microsequencer design is based on a modified version of the AMD2910 micro-program sequencer. The original 2910 is a 12 bit sequencer with a 32 word stack, and is capable of conditional branching, subroutine calls, and looping. The microsequencer in the Air Interface Processor is a 10 bit sequencer, but adds some powerful instructions to perform mufti-way conditional branching, among other things.
The number of microcode sequences is limited only by the available Sequence RAM
(SeqRAM) available. The SeqRAM is a single-port synchronous 1K * 32 RAM.
The Microcode Sequencer has a program counter (PC), which is initially set by the Event Handler. When it is instructed to start by the Event Handler, it shall begin executing the instructions in SeqRAM at the specified address, until such time as a JZ (jump-to-zero) instruction is found.

00000 JZ Jum to Zero 00001 GJS Conditional Jum to Subroutine 00010 JMAP Jum Ma 00011 CJP Condttional Jum PI
Ilne 00100 PUSH Push Conditional Load Counter 00101 JSRP Conditional Jum to Subroutine 00110 CJV Conditional Jum Vector 00111 JRP Conditional Jum 01000 RFCT Re at Loo Counter Not E ual to Zero 01001 RPCT Re at Pi Iine Counter Not E ual to Zero 01010 CRTN Cond~lonal Return 01011 GJPP Conditional Jum PI
line and Po 01100 LDGT Load Counter and Continue 01101 LOOP Test End of Loo 01110 CONT Continue 01111 TWB Three Wa Branch 10000 FORK Multlwa Branch others reserved Figure 15: Microsequencer Instruction Set The memory format for the modulator microsequencer is defined as follows:
OPCODE I EMIT I CCSEL ICPI FFCMD ISBI OC
The format of OPCODE is defined in Figure 21. The EMIT field is used as an argument to the OPCODE field, and is used for branch addresses or to load the internal counter. The format of the CCSEL (condition code select) and CP
(condition code polarity) is shown in Figure 22. The SR field (Scrambler reset) can be used to reset the Scrambler at any time. Refer to the Scrambler section for more information.
Counter (r) CMP
Threshold M ~ ~, I
o ~i ~t roa 8 erf of msnf0l & r tt & r ea & n0 ~ ~ m B anE of m5p(1) &~It & r i~&
r1 .A~
o O
.. ..
M I M
y ~(yiv&eMNmm(j)ArR&ryq&YL ~ ~-G~almmf3l&r~taren6r3 Figure 16: Configuration of condition codes and fork The configuration of condition codes and fork is shown in Fig. 16.

The FORK instruction, which is an addition to basic 2910 instruction set, uses the value formed by the fork cc(3:0) vector as the basis for a 16-way branch.
For example, if the value of fork cc is 12, the microsequencer will advance its program counter by 12.
The fork cc value is updated every clock cycle based on the configuration circuitry shown in Figure 16. Each bit in fork cc is derived from a programmable look-up table. A 5-bit value is used as the index to this look-up table.

FORK LUT insert~cr end of counter counter r0 0 message < ==
In threshold threshold ueue 1 FORK LUT insert~cr end of counter counter rl 1 message < ==
In threshold threshold ueue 2 FORK LUT insert~cr end of counter counter r2 2 message < ==
In threshold threshold ueue 3 FORK LUT insert_pcrend of counter counter r3 3 message < ==
in threshold threshold queue 4 Table I: FORK LUT Indices Programming the FORK instruction is a rather convoluted process, as it involves three layers of indirection. The FORK instruction is essentially a "case"
statement. The idea is to generate a 4-bit value (fork cc) to create an offset of 0 to 15.
Each bit of fork cc is derived from the corresponding FORK LUT. Each FORK LUT
is indexed by the 5-bit number formed by the concatenation of the conditions shown in Table 1. The conditions r0, rl, r2, and r3 are bits from the R7 register in the Event Handler. The R7 Bit Select register can be used to select among the lower 8 bits of the R7 register. Refer to Figure 16 for more details.
For example, suppose we wanted fork cc(0) to evaluate as true whenever insert~cr and counter=threshold are both true. This condition can be expressed as lxxlx, which means that bits 4 and 1 must be 1, and the other bits are don't cares. In this case, we would program the bits in the LUT that match lxxlx with 1, and the others with 0. The value generated is 32'hCCCC_0000.
o I o I o I o 0 0 0 0 ~ o 0 0 o s o 0 0 o i o 0 0 0 o i 0 0 o i i o a 0 0 i i 1 0 i 1 1 0 0 0 C

The condition codes (CCSEL) for conditional branches (for example, CJV) in the Microsequencer are hard-coded as follows:
j,, ~,~ ': ,1'i~ , 0 alwa s false 1 counter= 0 2 counter == threshold 3 counter < threshold 4 counter <= threshold insert r == 1 6 end of messy a In ueue 1 7 end of messy a In ueue 2 8 end of messy a In ueue 3 9 end of messy a in ueue 4 insert cr ==i AND ueue 1 end of messy a In 11 Insert r ==1 AND ueue 2 end of messy a in 12 insert r ==1 AND ueue 3 end of messy a in 13 insert r ==1 AND ueue 4 end of messy a in 14 value of R7 bit value of R7 bit Register R7 in the Modulator Event Handler can be used to control the Microsequencer to some degree. Bits 8 and 9 of the R7 register are used to generate condition codes 14 and 15. Bits 0 to 7 of the R7 register, in conjunction with the static R7 Bit Select register, can be used as inputs to the FORK LUT.

The read-only Event Handler registers for the Modulator contain the following values:
I ~~ I~ I ,~ ~ ~, ~ I, iii, IV~~ 'i'i ~ f rI~ i~iPl~~.
R8 B es remaininueue 1 in messy a R9 es remainin ueue 2 in messy a R10 B s remainin ueue 3 in messy a Rll s remainln ueue 4 in messy a R12 Condition Code Re aster R13 Event Handler Pr ram Counter R14 32'h0000 0000 R15 32'hFFFF FFFF

The definition of FFCMD (Frame Formatter command) is shown in Table 2. This instruction set is used to generate frames to be fed into the modulator Frame Formatter. As data or control words are inserted, they can be flagged with an attribute indicating whether or not they should be scrambled, and which outer code is to be used (ie. Reed-Solomon, CRC, or neither). If the SB bit is asserted in the Microsequencer instruction, the Scrambler is bypassed. The value in the OC
field is used to select which outer coding scheme is to be used (0-3).
The Frame Formatter is also able to insert register values from the Event Handler into the data stream. This mechanism allows the generated data stream to be more dynamic than would otherwise be possible. When the Event Handler issues a start command to the Microsequencer, the contents of RO to R7 are passed through a programmable barrel shifter and stored as inputs to the Frame Formatter.
III n~~i~~I~~~, I~~~li'~qi~j 0 no NOP

1-16 Insert Control Word 1-16 CW1- CWi6 ~

17 - 24 Insert Shifted Re aster 0 RO - R7 25 Insert Ori anal PCR PCRO

26 Insert Current PCR PCR

27 Insert Data from ueue 1 DATAl 28 Insert Data from ueue 2 DATA2 29 Insert Data from ueue 3 DATA3 30 Insert Data from ueue 4 DATA4 31 Flush FLUSH

Table 2: Modulator Command Set for Frame Formatter The most common use of the barrel shifter is to align an 8-bit value in one of the registers to the upper 8 bits of the 16-bit register value (inputs to the Frame Formatter must be MSB-aligned). The barrel shifter is configured as follows:
Each Rx shift field is defined as follows:
2'b00 = LSL (Rn, shift_by) shlft_by 2'b01 = LSR (Rn, shift_by) 2b10 = ASR (Rn, shift_by) 2'bll = ROL (Rn. shift bv) A simple microcode sequence to generate an MPEG frame for a base station could be programmed in the following manner. This sequence indicates that all bytes except for the initial sync should be scrambled (".S") MPEG_FRAME:
CONT Cwl.oC1 # 1 byte, typically 47h CoNT CW2.S.OC1 # 1 byte CONT CW3.S.OC1 # 1 byte CONT CW4.5.OC1 # 1 byte LDCT 182 DaTA2.s.oc1 # send data from queue 2, load counter loop: RPCT loop DATA2.S.OC1 # continue pulling data from queue 2 # until counter reaches zero; total =

7z FLUSH # indicates end of burst; soft reset The device can act as a simple ATM segmentation engine by setting the control word to a 5-byte ATM header. Up to 16 simultaneous ATM connections can be handled in this manner (one per Control Word).
CONT CW1.5.OC1 # cWl = 5-bytes = { vPZ/vc==(a,b) }
LDCT 2 NoP # 4 NoPS because Cwl is 5 bytes lOOpl: RPCT lOOpl NOP
LDCT 46 DATA1.S.OC1 # send 48 bytes from queue 1 lOOp2: RPCT lOOp2 DATA1.S.OC1 )Z FLUSH

i o" ~ ~~ 'i, ~ ~ ~ w ~~, , ~ ~
Ox000E0004 Event Handler Registers R/W/E
- ~

Ox000E0020 default value = 16 bits access macro = MOD_AIP_RW_REG_x number of a%ments = 8 Ox000E0024 Event Handler Read-Only Registers R/E
-Ox000E0040 default value = 16 bits access macro = MOD AIP_RO REG x 1 number of a%ments = 8 E

Ox000E0044 Event Handler Flags R/W/E

default value = 4 bits ' access macro = MOD AIP EV FLAGS x Ox000E0048 Event Handler PC R/W/E

default value = 10 bits access macro = MOD AIP EV PC x Ox000E004C uSequencer Next Address R/E

default value = 10 bits access macro = MOD AIP USE NA x Ox000E0050 Fork LUT R/W
-Ox000E005C default value = 32'h0 access macro = MOD AIP_FORK_LUT_x number of elements = 4 Ox000E0060 R7 bit select R/W

default value = 12'h0 access macro = MOD AIP R7 BIT SEL x Ox000E0064 Counter Threshold R/W

default value = 10'h0 access macro = MOD AIP THRESHOLD x Ox000E0068 u5equencer Counter Autodecrement R/W

default value = 1'b0 access macro = MODAIP USEQ,~AUTODECR x Ox000E006C uSequencer Busy R/E
' default value = 1 bits access macro = MOD AIP USE BUSY x Ox000E0070 Barrel Shifter to FF R/W

default value = 48'h0 access macro = MOD AIP SHIFT CNTL x Ox000E0078 Register Access Acknowledge Timeout R/W

default value = 10'b0001000000 access macro = MOD AIP REG TIMEOUT x 0x00800000 Mod Event Handler Memory R/W
-Ox00800FFC access macro = MOD EV_x number of elements = 1024 0x00840000 Mod Sequencer Memory R/W
-Ox00840FFC access macro = MOD_SE~x number of elements = 1024 Optionally, a 2910 can be added to the Receive-Side Microsequencer in future revisions of the chip.
The Microsequencer is responsible for sending commands to the Frame Formatter/Frame Deformatter. On the Modulator, this builds up a frame of data on a byte-by-byte basis. On the Demodulator, it performs byte-by-byte pattern matching to direct different portions of the received burst to different output queues.
The Demodulator Microsequencer is much simpler than its modulator counterpart. The Microsequencer instructs the Frame Deformatter to perform rudimentary pattern matching on the demodulated data stream.
Received bytes are matched to an expected frame or timeslot format, and flagged with attributes that are passed to the remaining downstream hardware for processing before being written in the Output Queues.
The memory format for the demodulator Microsequencer is defined as follows:
The Microsequencer starts running at the address specified by the Event Handler. Every instruction in FDFCMD is sent to the Frame Deformatter a number of times, depending on the value in.the COUNT field. When finished with the current instruction, the Microsequencer program counter advances to the next instruction. If the BR flag is set, the Microsequencer performs an unconditional branch to the address specified in the ADDR field.
The attributes that can be tagged are ~ whether or not the byte should be descrambled (S) ~ the type of outer code decoding to be applied to each byte (OCn) ~ whether or not the byte should be copied to the output FIFO (KEEP) ~ if the byte is to be copied to the output FIFO, the number of the QUEUE in to which it should go In addition to these basic attributes, the Frame Deformatter allows the user to control the operation of three downstream blocks, to a limited degree. The start-of frame for Reed-Solomon decoding can be indicated using the RS attribute. The Scrambler can be reseeded using the SR attribute. The start-of frame for Address Filtering can be indicated using the SYNC (SY) attribute.
<, ~~ FT~~I ~;., ~ ~ ~ ;~., 0 0 0 0 0 0 y 0 0 0 0 1 DATA ueue Table 3: Frame Deformatter table The NOP command is the command that the Frame Deformatter receives when the Demodulator is not running, or when there is no incoming data.
A DISCARD command matches any incoming data. The KEEP attribute is not set. The data will still be passed through the Reed-Solomon decoder, Descrambler, and Address Filter. It will not, however, be stored in the Output FIFO.
A DATA command matches any incoming data. The KEEP attribute is set. The QUEUE attribute will be set to the value specified in Q.
A CW command compares the control word number N with the incoming data. If a match is found, the Microsequencer will perform a conditional branch to the address specified in the ADDR field. If a match is not found, the Microsequencer will continue with the next address. In either case, the KEEP attribute is not set.
A CDATA command performs the same function as the CW command.
However, the KEEP attribute will be set, and the QUEUE attribute will be set to the value specified in Q.

The SYNC, FRSYNC, and SFRSYNC commands indicate that the Frame Deformatter should discard all incoming data until a Sync is found. In the case of the SYNC command, either a Frame Sync or a Super Frame Sync will cause a match;
FRSYNC and SFRSYNC cause the Frame Deformatter to wait for a specific Frame or Super Frame Sync, respectively. The data is discarded if the K bit in the command is not set; if it is set, then QUEUE attribute will be set to the value specified in Q.
Note that the various SYNC commands are different from the SYNC
attribute. The SYNC command causes the Frame Deformatter to wait for a Sync.
Depending on the frame format in use, it may be desirable to reposition this Sync, to allow better filtering of incoming data using the Address Filter.
i ' ' i i i ~ I I, q ! ~ I f ~~, i, i p Ox002A0004 II ~I I i!!
- Event Handler Registers R/W/E

Ox002A0020 default value = 16 bits access macro = DEMOD_AIP_RW_REG_x number of elements = 8 Ox002A0024 Event Handler Read-Only Registers R/E
-Ox002A0040 default value = 16 bits access macro = DEMOD_AIP_RO_REG_x number of a%ments = 8 Ox002A0044 Event Handler Flags R/W/E

default value = 4 bits access macro = DEMOD AIP EV FLAGS x Ox002A0048 Event Handler PC R/W/E

default value = 10 bits access macro = DEMOD AIP EV PC x Ox002A004C uSequencer Next Address R/E

default value = 10 bits access macro = DEMOD AIP USE NA x Ox002A0050 Fork LUT R/W
-Ox002A005C default value = 32'h0 access macro = DEMOD_AIP_FORK_LUT_x number of a%ments = 4 Ox002A0060 R7 bit select R/W

default value = 12'h0 access macro = DEMOD AIP R7 BTT SEL x Ox002A0064 Counter Threshold R/W

default value = 10'h0 access macro = DEMOD AIP THRESHOLD x Ox002A0068 uSequencer Counter Autodecrement R/W

default value = 1'b0 access macro = DEMOD AIP USE AUTODECR
x Ox002A006C uSequencer Busy R/E

default value = 1 bits access macro = DEMOD AIP USE BUSY x Ox002A0070 Register Access Acknowledge Timeout R/W

default value = 10'b0001000000 access macro = DEMOD AIP REG TIMEOUT
x 0x00820000 Demod Event Handler Memory R/W
-Ox00820FFC ' access macro = DEMOD_EV_x number of a%ments = 1024 0x00860000 Demod Sequencer Memory R/W
-Ox00860FFC access macro = DEMOD_SE~x number of elements = 1024 There are 4 phase-locked loops on the SB7016.
Table 4: PLL Control Register Format The "SETUP" field is a special PLL configuration parameter. It is a function of M, N, P, and input frequency, and must be requested from ST
Microelectronics.
F(clock-out) _ ~~. ~ F(clock-in) F(clock-in) <_ 200MHz 1<_M<_255 15N<_255 OSPSS
F(clock in) IMHz <_ M - S 2MHz Phase comparator limit 200MHz <_ ~ F(clock-in) <_ 622MHz vCO limit Each PLL has a "lock" signal that can be read by software to ensure that the PLL has locked.
r i ~ICII 1 t In I i V
i I
I I ~~'' i~~ ~'~ii~
0x00000020 mod_samp clk default value = 29'h 10101 access macro = CFG MOD SAMP x 0x00000024 mod_samp_clk lock R/E

default value = 1 bits access macro = CFG MOD SAMP LOCK x 0x00000028 demod_samp clk R/W

default value = 29'h10101 access macro = CFG DEMOD SAMP x Ox0000002C demod_samp_cik lock R/E

default value = 1 bits access macro = CFG DEMOD SAMP LOCK
x 0x00000030 demod_bit clk R/W

default value = 29'h10101 access macro = CFG DEMOD BIT x 0x00000034 demod_bit clk lock R/E

default value = 1 bits access macro = CFG DEMOD BIT LOCK
x 0x00000038 ' modem_e cik R/W

r default value = 29'h10101 access macro = CFG MODEM E x Ox0000003C modem_e_clk lock R/E

default value = 1 bits access macro = CFG MODEM E LOCK x Table 5: PLL Control Register Map The Numerically-Controlled Clock Dividers (NCCDs) consists of a divide-by-2 circuit, and a divide-by-N. They are provided to divide the reference clock generated by the PLL to the sampling clock (from the divide-by-2) and the byte clock (from the divide-by-N). The duty cycle of the generated divide-by-N clock is not guaranteed to be 50%. As such, the clock should not be used for timing-sensitive applications, such as driving ADCs or DACs. It is intended only to drive the internal byte clocks.

The clock divider must be programmed with a 9-bit number ("delta"); the top 7 bits comprise the integer portion, and the bottom 2 bits comprise a fractional portion, which is in thirds. The period of the generated clock is 128/delta periods of the reference clock.
Table 6 shows the delta values to be used if the sampling clock is derived from the NCCD divide-by-2. If it is not, the delta value should be doubled.
Ref clk periods refers to the number of periods of ref clk in one period of the generated clock.
Samp clk periods refers to the number of periods of samp clk in one period of the generated clock. There are always two periods of ref clk in one period of sump clk.
~~ ~' I1T' ';';;;~~ ~ as.>~;
1 2 4 ~ 32 8*2=16 9'b0100 2 3 5 9'b0101 24 8*3 2=12 1 Ol 3 4 6 9'b0110 21 1 8*4 3=10 2 3 6 6 9b0110 19 1 8*6 5=9 3 5 7 8 7 9'b0111 18 2 S*8 7=9 1 7 b ass 8 9'b1000 16 8 Table 6: NCCD Control Register Format A bank of 4 clock dividers is provided for very low bit-rate applications that are outside the range of the PLL. Each clock input is divided by 2d'"-° by the Divide-by-2N Counters diva div2 divl div0 Table 8: Divide-by-2N Register Format Table 7: NCCD Clock Dividers Register Map 0x00400044 Divide-by-2~N counters R/W
default value = 16'h0 access macro = FLUFF DIV2N x Table 9: Divide-by-2N Register Map There are 3 on-chip DACs: I, Q, spare.
~ Triple DAC with 8 bit resolution, optional 10-bit resolution for gamma-correction and specialist applications.
~ Comparators on outputs for monitor sensing ~ 250MHz operation at 2.SV +/- 0.25V
~ 1.235 V input reference voltage, with optional internal bandgap reference ~ Advanced power-down modes kid C1 I,'R~, d 47 F i'I
ca acitor CZ-C3 100 nF surface mount ca adtor C4 10 nF surtace mount ca acftor Rl iK S2 5/a resistor R2 147 S1 1% resistor R3-R5 75 fI 1% resistor Dl LM385BZ-1.2volts a reference D2-D7 1N4148 diode Li 1 mH inductor iF~~',Y'i Eylr; :'~i~f~' ~l"~ ''~i I_DAC VREF r I ,a'" ;
External VRef pin to allow the Internal reference voltage to be overridden. If used in external mode the volts a reference should be decou led to local round out-side the chi with a lOnF chi -ca acitor.

I_DAC_RSETV A precision resistor placed between this pin and GND sets the full-scale DAC current.

O_DAC_RSETI The required resistor value can be calculated from:

RSet (ohms) _ (Z.1 x Vref) / Iout where VRef is the external or Internal reference volts a and Iout is the r ulred DAC full scale current.

IO_DAC_COMP External compensation pin, which should be externally coupled to analog VDD using a lOnF chip ca acitor.

VDD ANAO Analo ower su I .

O_DAC_I_DATA The DAC outputs. These are designed to drive a doubly terminated (37.5 ohm) load, but can drive up to O_DAC_Q_DATA 75 ohms with a suitably chosen RSet resistor value.

O DAC ANA E

O_DAC_COMPOUT_IThese signals are outputs which detect the DAC
output level relative to an internally generated level of O_DAC_COMPOUT_Qapproximately 0.35V. The output is driven high when the relevant DAC output is below this reference O DAC COMPOUT level.
E

I_DAC_COMPIN_ICurrent return path for the DAC outputs, tied to the PCB ground plane I_DAC_COMPIN_Q

I DAC COMPIN
E

notBlank ~ notBlank ~ notBlank ~ Black ~ Black ~ Black Power Down Sleep Table 10: DAC Control Register Format The spare DAC can be controlled using the FLUFF DAC_TEST register.
Table 11: DAC Register Map There are two on-chip ADCs, one each for the I and Q channels. The ADCs have a resolution of 8 bits. The internal ADCs may be disabled, allowing the use of external ADCs, mounted on the system PCB.
The flash ADCs are able to quantize the input signal at up to 250 Ms/s in 63 levels (-31 to +31).
Ox003C003C ADC Control R/W
default value = 12'b0 access macro = DEMOD ADC CONTROL x The Modulator and Demodulator each have 8 general-purpose digital output pins. They are intended primarily as control signals for the SB7040 and SB7041.

Table 12: Feature Pins Register Map The Pulse Width Modulator block is shown in Fig. 29a.
pwm out clk duty_cycle(9:0) Figure 29a: Pulse Width Modulator block diagram There are 8 internal pulse width modulator (PWM) devices that can be used for miscellaneous external control functions.
The period and duty-cycles of the PWMs are programmable via "On Time"
and "Off Time" registers.
I PWMCLK
PWM ON TIME = 6r PWM OFF TIME = 11 ! PWM ON TIME
~--w O PWM OUT n ! ~ ii r i, i ~ I14~ ~ ~ ! illl ~Ir'R, nl I y ~~
~ rr r ,,.
0x00400004 ' I ~ I i ' i iiill~ ' i ', i - i i PWM On Times R/W

0x00400020 default value = 32'd0 access macro = FLUFF_ON_TIME_x number of a%ments = 8 0x00400024 PWM Off Times R/W
-0x00400040 default value = 32'd0 access macro = FLUFF_OFF_TIME_x number of elements = 8 Table 13:
PWM Register Map The Frequency Hopper is used for MF-TDMA applications. It has two modes of operation: DDS mode and Fractional-N mode.
~=j'IFi ~, ~ ~El~n, ~, ~.. ~~y,, 0 0 r~i.
0 DDS Mode AIP controlled 0 1 0 DDS Mode Software driven 1 0 x Fractional-N mode AIP controlled 1 1 X Fractional-N mode software driven In DDS mode, the supported Frequency Synthesizer chip is the National Semiconductor LMX2315/LMX2320/LMX2325 PLLatinum. In this mode, the 32-bit data, from either the AIP or the Overnde register, is interpreted as follows:
The DDS is programmed with a serial bit stream. The bits are transmitted in the order S, R, 1, B, A, 0. The S value is obtained from the Prescaler Select register. Refer to the data sheet for this part for more information.
In Fractional-N mode, the SB7016 is assumed to be a portion of the feedback loop of a PLL. In this mode, the clock driven on the I MOD FRACTN CLK pin is divided by a factor of 128/N. This allows fine-tuning of the IF up-converter. The 32-bit data, from either the AIP or the Override register is interpreted as follows:

The SB7016 has a single modulator circuit incorporating both burst-mode and continuous-mode modulator operation. It can be configured in software to operate in the desired mode. The modulator supports both QPSK and 16-QAM modulation schemes.
The following features are programmable:
~ Burst or continuous mode transmission ~ Programmable frame format; optional preamble ~ QPSK or 16-QAM modulation; programmable constellations ~ Burst-by-burst frequency hopping for MF-TDMA applications ~ Scrambler polynomial and seed; bypass ~ Reed-Solomon encoding; bypass ~ Convolutional Interleaving depth and delay; bypass Table 14: Frequency Hopping Register Map Input Butfu RAM (S12 X 80) dW~-pat .Y... ",...
input data Ipp~ F~~ Scrambler RS Encoder Interleaver Paralfel~tq Queuing Formatter serial:
(tea- r CRC Irrterkaver RAM (512 x 8) Generator ~ ,,",,_""., ' Power digital Amp I

"... ~Contrdler RC I
data to DAC

Corn.

Preamble Diff.
Encoder Puncturing Mapper T

iwierr,~"w Insert Encoder ~ ~ ~ a a ~ s RC Q
Q data ~~ to ~ DAC

1 dt !a QPSX.

1 dls lar QAM

digital Q

~1M
k ssnpla/symbol Lp$X
h sampla/symDOl raw I&Q
data Figure 17: Modulator Top Level Block Diagram The modulator section consists of the following major functional blocks:
~ Input Queuing ~ Frame Formatter ~ Scrambler ~ RS Encoder ~ CRC Generator ~ Interleaver ~ Parallel-to-Serial Converter ~ Convolutional Encoder ~ Preamble Insert ~ Power Amp Controller ~ Differential Encoder ~ Modulation Mapper ~ Root Raised Cosine Filter Depending on the applications, the following functional blocks can be bypassed:
~ Scrambler ~ RS Encoder ~ CRC Generator ~ Interleaver ~ Convolutional Encoder At power-up, the modulator is held in a reset state. The software must write a 1 to the reset register to bring the modulator out of reset, at which point it is possible to configure any of the programmable options on the modulator side of the SB7016.
After configuration, the modulator must be specifically enabled by asserting the Enable Register.
The following table shows the configuration of the modulator Bypass register. At power-up, all functional blocks are bypassed. The user must specifically enable the desired blocks by setting the relevant bits to zero.
0 Scrambler Bypass 1 Interleaver Bypass 2 Convolutional Encoder Bypass 3 Differential Encoder Bypass 4 Differential Encoder2 Bypass Scrambler2 Bypass 6 Address Filter Bypass 7 Reed-Solomon Decoder Bvoas The modulation format can be selected using the Modulation Select register.
2'b00 ~ QPSK (2 samples per symbol) 2'b01 16-OAM l4 samples per svmb For applications requiring the transmission of a PCR count, the following register must be configured to indicate the relationship between mod byte clk and the generated dds_syn_clk signal.
2b00 mod_byte_dk Is approximately the same as dds_syn_clk 2'b01 ~ mod byte_dk Is slower than dds_syn_dk 2'b10 mod buts dk is faster than dds sun dk The dbg mux sel register can be used to send the output of various internal modulator components to the O DBG MOD2 * pins. These pins can be used for debugging purposes, or to send a partially formatted and encoded data stream to an external device for further processing.
6'b001_lll Frame Formatter output 6'b010_i11 Scrambler output 6'b011_lil Outer Code output 6'b100_lll Scrambler2 output The External Processing Register can be used to pipe raw data into the modulator, allowing the use of an external device for data processing or encoding. By using this register and the dbg_mux sel register previously described, an external FPGA can be used to implement error control codes that are not supported directly by the SB7016.
2'b00 No external processing (default) 2'b01 Accept byte-level data from I_DCf_MOD_BYTES input pins 2'b10 ~ Accept symbol-level data from I EXT MOD SYMS input oir i ~ f~,~,~~~ ~ , i ~ ~~ i default value = 1'b0 access macro = MOD BURST MODE x Ox001A0040 mod byte_clk to dds_syn clk relationship R/W

default value = 2'b00 access macro = MOD BYTE CLK SPEED x Ox001A0044 External ProcessingR/W

default value = 2'b00 access macro = MOD USE EXTERNAL x Ox001A004C Debug mux sel R/W

default value = 6'bi 11 001 access macro = MOD MUX SEL x The start of a Super-Frame is keyed off a "Super-Frame Strobe", which may be derived from the PCR algorithm, or some other system event. This is an issue of system design. The SB7016 looks for the I MOD SF STRB IN pin to be asserted high.
The duration of the Super-Frame is N samples (programmable using the Frame Count Limit register, up to 232). In continuous mode, we program the modulator to process data between time O...N; in burst mode, we program the modulator to process data over any subset of time 0. ..N. We will refer to any data processed as a "burst" of data; continuous mode is simply two seamless "bursts", back-to-back. For debugging purposes, the value of the Event Counter can be read.
For accurate burst synchronization, one important issue must be resolved.
Much of the Modulator (including the AIP), runs off a byte clock; however, burst times are typically specified in terms of samples or symbols. A special module called Preamble Insert compensates for this lack of precision.
Apart from actually inserting the preamble, the Preamble Insert module contains a small FIFO. Data is streamed from the Frame Formatter, and arnves at the FIFO slightly before it is due to leave. The burst data is then delayed until the precise transmission time.

The Preamble Insert module uses a time reference that is a delayed version of the one used by the AIP. The amount of time by which the reference is delayed is programmable. The Pipeline Delay register is used to control this time offset.
The difference in time references depends on the FEC functions that are enabled in the Modulator chain, and the ratio of the sampling clock to byte clock. Table 15 shows the processing delays for the various functional blocks.
a ~ 4 '; jr ~ ~! P~,~-Pr,~ ;~T;I~qij iy";na, enera l ~i~P~' y.
overhead ,;,, mod b a clk TBD

eneral overhead TB D mod sam clk Scrambler TBD TBD mod b a clk CRC Generator TBD TBD mod b a clk RS Encoder TBD TBD mad b a dk Scrambler 2 TBD TBD mod b a dk Interleaver TBD TBD mod b a clk Convolutlonal TBD TBD mod sam dk Encoder Pundurin TBD TBD mod sam dk Table 15: Processing Delays for Modulator Funcrional Blocks P ~r f' I ~ I i'ir~i~ ii i 1, i I ~ t Ox001A0010 i Frame Count Limit R/W

default value = 32'h0 access macro = MOD COUNT LIMIT x Ox001A0018 Pipeline Delay R/W

default value = 16'd256 access macro = MOD PIPELINE DELAY
x Ox001A001C Event Counter Readback R/E

default value = 32 bits access macro = MOD EVENT COUNTER
x Ox001A003C Ranging Offset R/W

default value = 10'd512 access macro = MOD RANGING OFFSET
x Ox001A0050 DDS Hop Delay R/W

default value = 16'd256 access macro = MOD DDS HOP DELAY
x The Input Queuing block is shown in Fig. 29b.

cpu_iq_add(11:0) cpu_iq_data(63:0) hec_insert iq_cpu data out(63:0) urx_parity_cheGc_en cpu iq_data rdy processor type cpu_iq_r wn start~ointer(7:0)(8:0) iq_cpu_error end~pointer(7:0)(8:0) min_queue size(7:0)(8:0) tx_data(7:0 ) tx_enb_n tx_soc iq_ff data(3:0)(7:0) ~_p,ly ff fifo_rd(3:0) tx_Gav iq_ff cell_available(7:0) tx_Gk e iq_ff om(3 downto 0) iq_low q interrupt x60_clk iq_overflow mod_byte Gk iq_urx~arity_error Figure 29b: Input Queuing block diagram The Input Queuing block has two data sources:
~ Utopia RX block ~ Data from processor There are four input classes supported, with a FIFO for each. Utopia data is always queued in FIFO 0, ATM idle cell (with the right HEC) must be configured in queue 4. Processor data can be queued in FIFOs 0-3, depending on the register address used to perform the write. Each data queue 0-3 is paired with an idle queue 4-7. Idle data for queue 0 must be placed in queue 4, idle data for queue 1 must be placed in queue 5 and so on. The MAC layer software will set different address to determine into which FIFO incoming data is to be queued. FIFO design supports data transfer from utopia to queue 0 at the same time as processor data transfer to queue 1 to 7.
The FIFOs are implemented using a dual-port synchronous, S 12 * 80 bit RAM. The FIFO depths shall be configured by software, as required for the particular system. This allows the entire memory to be used as one FIFO for systems that require only one data class.
Each data class may define an associated Idle Cell, which is used whenever there is a request for data, but no data is available in the FIFO. An Idle Cell is stored in memory, and copied out verbatim. The size of the Idle Cell can be anywhere from 0 to 1024 bytes.

Generally, a modem should not care about packets or cells - it transfers raw data. However, to properly support Idle Cells and many of the proposed air interface standards, the modem must, at a minimum, keep track of where packets end. The number of bytes remaining in the message is available with the output data, and passed to the Frame Formatter.
An enable signal from the Frame Formatter is used to feed data into the modulator with sufficient gaps in between to accommodate any FEC or frame format overhead.
The "ff fifoN rd" signal shall cause the FIFO read pointer to be incremented, which in turn shall cause a new data byte to appear on "fifoN ff data"
two clock cycles later.
The Air Interface Processor (via the Frame Formatter) will select which data queue is to be serviced.
The input queuing memory is 80 bits wide. The first 64 bits are used for buffering data; the other 16 bits are used to identify end of message and gives information about the number of bytes left in the message. Maximum message length is 262 143 bytes (bytes left is 16 bits only so it will saturate at a maximum value of 65535). ATM messages, Idle and Data, are always and exactly 53 bytes in length.
The input queue memory can be accessed in two different ways. By using address (11:9), 0 to 2, any location of the input queuing memory can be read from or written to. These addresses should be used for debugging purposes only.
Current queue size values are available for software fine-tuning of data transfer rate to the modulator buffers. An interrupt is generated for data queues when queue level is smaller the specified minimum queue size.
Whenever the data queue level is below the minimum queue size, the input queuing will select data from the idle queue if reaching an end of message.
For normal data transfer to queues the software should follow this procedure:

1. Configure memory partitioning for one or multiple queues based on system requirements. Idle queue size as to be set exactly to the length of the idle message.
~ message length between 1 to 8 bytes =>
queue start~ointer = queue end~ointer.
~ message length between 9 to 16 bytes =>
queue end~ointer - queue start_pointer = 1 2. Write idle message length to register => address ( 11: 9)=" 100"
3. Write Complete Idle message to Idle queue (4-7) _> address (11: 9)--'"011"
Repeat:
4. Write Data message length to register 5. Write Data message to Data queue (can alternate between data queues without end of message but must complete a 64-bit write access before changing queue) I I ~ 'I ~ II I,il I.
I
0x00020004 Queue End Pointer R/W
-0x00020020 default value = 9'h0 access macro = IQ_ENt7_POINTER x number of elements = 8 0x00020024 Minimum Queue Size R/W
-0x00020030 default value = 9'h0 access macro = IQ_MIN_QUEUE SIZE_x number of elements = 4 0x00020034 Queue Start Pointer wW
-0x00020050 default value = 9'h0 access macro = IQ_START_POINTER
x number of a%ments = 8 0x00020054 ATM HEC Insert R/W

default value = 1'b1 Table 16: Input Queuing Memory Map The Frame Formatter block is shown in Fig. 29c.
fifo_ff data(3:0)(7:0) ff scr data(7a)) ff fifo_rd(3:0) ff scr_rdy ff scr flush aip_ff cmd(4:0) pcr ff count(41:0) pcr ff offset(41:0) mod_byte_clk Figure 29c: Frame Formatter block diagram The Frame Formatter is a large MUX that outputs data from various sources into the Modulator. Based on control signals from the Air Interface Processor, this block will output either user data (the input stream), or control data, which can consist of PCR information, control words, management information, sync words, preamble, or unique words.
The Frame Formatter contains 16 control words, which are special characters that may be inserted into the data stream at any time. These control words are a maximum of 64 bits each, and must be set up by software beforehand.

Table 6: Input Queuing Register Map If~,4 V~t'~! 4E~, p ~'9 iI~~!,;" fi i ; ~r~"
;,, 0 no NOP

1 - 16 Insert Control Word 1- 16 CW1 - CW16 17 - 24 Insert Shifted R inter 0 RO - R7 25 Insert Ori final PCR p~0 26 Insert Current PCR PCR

27 Insert Data from ueue 1 DATAl 28 Insert Data from ueue 2 DATA2 29 Insert Data from ueue 3 DATA3 30 Insert Data from ueue 4 DATA4 31 Flush FLUSH

Table 17: Frame Formatter Command Codes Note that it is possible to insert markers that are not multiples of 8 bits.
The fifo ff data signal will always contain valid data when the Frame Formatter receives a command from the AIP. It is the responsibility of the AIP
to ensure that the Frame Formatter only receives commands when there is valid data in the FIFO. The Frame Formatter controls the reading end of the FIFO by strobing the ff fifo rd signal. New input data arrives on the following clock cycle.
A "flush" command indicates that there are no more data words to be sent in this frame. The Frame Formatter shall assert ff scr flush coincident with the last output byte, and return to its idle state.
,~4ti~
Input to FF W DZ 3 4 I d Dd ~--_.._ Da °d n ~ nusn nop R_sa_data 47h cMl7 ahf2 rnd3 ~~ ~ D D
ff_sa_Ny tf sa >tush Saamder bypass overtida sa_rs~ dale 47h ~ (~I 3 (D) (D} ~_-_-__ {D} N) Sa_rsenc_by sv rsenc dash 18 drtles rsenc_int data ~ 47h (adl aN ~ (p) {D) \ -~___ ..-__ (p) {D) ~ ---__ {R) ~~
Benc_Int_rc!y rsenc Int nusn ~i ~, ~ i '~I 0~ ~ !' ~ ' ii I ~ I I I ~ ~
0x00040004 wW
- Control Word I i 0x00040040 default value = 64'h0 access macro = FF_CW_x number of elements = 16 0x00040084 Control Word Size R/W
-Ox000400C0 default value = Td0 access macro = FF_CW_SIZE_x number of elements = 16 Ox000400C4 AIP Register Size R/W
-Ox000400E0 default value = 5'd8 access macro = FF_AIP_REG_SIZE_x number of a%ments = 8 Ox000400E4 PCR Offset Size R/W

default value = Td42 access macro = FF PCR OFF SIZE
x Ox000400E8 PCR Count Size R/W

' default value = Td42 ' access macro = FF PCR CNT SIZE
x Table 18:
Frame Formatter Register Map The Scrambler is shown in Fig. 29d.
ff scr data(7:0) scr rsenc_data(7:0) ft_scr rdy scr_rsenc rdy ff scr flush scr rsenc flush aip scr bypass mod_byte Gk scr seed(15:0) scr~olynomial(15:0) Figure 29d: Scrambler block diagram The scrambler depth is up to 16. The generator polynomial G(x) is programmable. The scrambler seed is programmable.
Input data is valid on the rising edge of the clock when ff scr rdy is high.
If ff scr flush is high, then the input data is the last octet in the stream.
The pipeline delay in active and bypass modes is identical.
The Scrambler Control register controls when the pseudo-random binary sequence is advanced, and when it is reset. There is one of these registers for each of the 2 scrambler circuits.
0.
The Scrambler polynomial and seed registers have the following format:

Table 19: Scrambler Control Register Format There is a Scrambler Mode register, which must always be programmed to Figure 18: Scrambler functional diagram !
0x00060004 i~ ~ ~I R/W/S
Scrambler Seed default value = 16'b1111111111111111 access macro = SCRAMBLER SEED x 0x00060008 Scrambler Polynomial R/W

default value = 16'b0000111000000011 access macro = SCRAMBLER POLYNOMIAL
x Ox0006000C Scrambler Mode R/W

default value = 1'b0 access macro = SCRAMBLER MODE x 0x00060010 Scrambler 1 Control R/W

default value = Tb1111 100 access macro = SCRAMBLER SCR1 CONTROL
x 0x00060014 Scrambler 2 Control R/W

default value = Tb1111_100 access macro = SCRAMBLER SCR2 CONTROL
x Table 20: Register Scrambler Map The Modulator Outer Code module contains the CRC Generator and the Reed-Solomon Encoder, in that order. It is a simple block that enables the appropriate encoder depending on the "aip outer code sel" signal. This scheme allows up to four encoding schemes to be in use during normal system operation without requiring any software intervention.
The mapping between "aip outer code sel" and encoding scheme is fully programmable. There is a register for each combination of "aip_outer code sel", with the following format:

DATA IN DATA OUT

There are limitations on the value of the shortening parameter. Refer to the Reed-Solomon Encoder section for more details.
It is possible to have both the CRC Generator and the RS Encoder active for any given burst.
By default, the Outer Code table entries are mapped as follows:
r, ~ , ~~R ,a 0 ~'~ ~i~, uncoded 2pq 188 i i 0x00080004 Outer Code 0 R/W

default value = 18'b11 00000 000 00000000 access macro = MOD OUTER CODE OUTER CODESEL
0 x 0x00080008 Outer Code 1 R/W

default value = 18'b10 00000 100 00110011 access macro = MOD OUTER CODE OUTER CODESEL
1 x Ox0008000C Outer Code 2 R/W

default value = 18'b10_00000_010_10111011 access macro = MOD OUTER CODE OUTER CODESEL
2 x 0x00080010 Outer Code 3 R/W

default value = 18'b10_00000_100_11000000 access macro = MOD OUTER CODE OUTER CODESEL
3 x Table 22: Outer Code Select Register Map Modulator Table 21: Modulator Outer Code Select Register Format A block diagram of a Reed-Solomon encoder module is shown in Fig. 29.
oc_rsenc_data(7:o) rsenc_data(7:0) oc_rsenc_rdy rsenc rdy oc rsenc flush rsenc flush oc rsenc_bypass mod_byte_clk oc_rsenc code_sel(3:0) oc rsenc_shortening(7:0) Figure 29: Reed-Solomon encoder module block diagram The Reed-Solomon Encoder module consists of the following Reed-Solomon codes.
RS(255, 239, t=8), including RS(204, 188) RS(255, 247, t=4), including RS(68, 60) RS(255, 245, t=5), including RS(63, 53) The output of this module must be continuous over the duration of a burst in order for the rest of the downstream circuitry to work properly.
Since the Reed-Solomon encoder adds extra bytes to the data stream, it must reposition the rsenc int flush signal to coincide with the final byte.
The Reed-Solomon Encoder has no directly accessible registers. All configuration is done through the Outer Code wrapper module.
More flexible Reed-Solomon encoders incorporating variable generator polynomials and more flexible shortening can be used in alternate embodiments.

A block diagram of a CRC Generator is shown in Fig. 30.
oc rsenc data(7:°) crcg data(7:0) oc rsenc rdy crcg rdy oc rsenc flush crcg flush oc crcg bypass mod byte cik Figure 30: CRC Generator block diagram Some systems use CRC to encode the transmitted data instead of the Reed-Solomon code. This is a programmable option.
The output of this module must be continuous over the duration of a burst in order for the rest of the downstream circuitry to work properly.
Since the CRC Generator adds extra bytes to the data stream, it must reposition the crcg_flush signal to coincide with the final byte.
The generator polynomial shall be programmable, supporting terms up to x sz. The CRC value can be programmed to be 8, 16, 24, or 32 bits in length. Any length of input data is supported.
Following is a list of some commonly used CRC polynomials. The CRC
Generator shall be verified against these polynomials ~ CRC-16 x 16+ x 15+ x 2+1 ~ CRC-CCITT x 16+ x 12+ x 5+1 ~ CRC-32 x32+x26+x23+x22+x16+x12+x11+xl°+xg+x'+xs+x4+x2+x +1 Both CRC-16 and CCRC-CCITT are used for 8 bit transmission streams and both result in 16 bit FCS. The last two are widely used in the USA and Europe respectively and give adequate protection for most applications. Applications that need extra protection can make use of the CRC-32, which generates 32 bit FCS.
The CRC-32 is used by the local network standards committee (IEEE-802) and in some DOD applications.
When calculating CRC 8-bits at a time, the general structure of the computation is always as follows (regardless of the polynomial):
for i in 0 to 31:
CRC(i) <= reduce_xor( subset of current data bits ) xor reduce_xor( subset of CrtC bits ) The CRC Generator uses a set of mask registers to extract the subset that is required to generate the CRC for the polynomial in question. It is up to the software to generate these masks.
Ox000A0004 Data Mask R/W
-Ox000A0080 default value = 8'h0 access macro = CRCGEN DATA_MASK_x number of a%ments = 32 Ox000A0084 CRC Mask R/W
-Ox000A0100 default value = 32'h0 access macro = CRCGEN_CRC_MASK_x number of elements = 32 Ox000A0104 CRC Byte Count R/W

default value = 3'h4 access macro = CRCGEN CRC BYTE COUNT
x Ox000A0108 Data Byte Count ~ R/W

default value = T h8 ' access macro = CRCGEN DATA BYTE COUNT
x Table 23:
CRC Generator Register Map A block diagram of an Interleaver is shown in Fig. 31.
oc_int data(7:0) int diffenc data(7:0) oc int rdy int diffenc rdy oc_int flush int diffenc flush aip_int bypass mod_byte_clk depth sel(3:0) Figure 31: Interleaver block diagram Performs convolutional interleaving as per EN 300 421.
The product of depth and delay must be less than or equal 256. The interleaving period (and thus frame size) is therefore limited to 256.
This block contains a 512 x 8 dual-port synchronous RAM.

M

M M
from g encoder . M !~; M ~, channel M M M M M
Figure 19: Interleaver Block Diagram The parallel to serial converter of Fig. 32 is the transition point between the byte clock and sampling clock domains. The Modulator requires a continuous output stream to be provided to the DACs. In this design, the way this is achieved is to ensure that there is a continuous stream of bytes to the Parallel-to-Serial Converter.
diffenc~s data(7:0) ps_convenc data diffenc~s rdy ps convenc rdy diffenc~s flush ps_convenc flush aip_convenc_bypass mod_byte clk mod same clk aip_convenc rate sel(2:0) Figure 32: Parallel-to-serial Converter block diagram The Parallel-to-Serial Converter performs the rate adaptation across time domains, and feeds bitwise data to the convolutional encoder. Data may be shifted out either MSB-first or LSB-first, depending on the value of the PS Invert Bits register (0=MSB-first, 1=LSB-first).
This block consists of a FIFO for rate adaptation, and a state machine to feed data into the convolutional encoder in a specific pattern, depending on the selected rate.

Table 24: Interleaver Register Map The output side of the FIFO is significantly faster than the input side. The output clock is anywhere between 8 to 16 times faster, depending on the convolutional encoding rate.
The Air Interface Processor should control the data flow into the modulator, so that the data flow into the Parallel-to-Serial Converter is continuous over a given burst.
The Parallel-to-Serial Converter receives the int-ps_flush signal on the last data byte. The ps_convenc flush signal must be positioned to coincide with the final bit.
The following timing diagrams illustrate the expected output of the Parallel-to-Serial Converter ("Input Data") for supported convolutional encoding rates.
Bypass Sampling dock Inputdefa X3 X' '~5~8 ~7~8 ( 1 X2 \

Bypus ou~ut 1.2 3.' 5.A 7.B

R abe 1 /

sampkno dock Input data RHataoufput I,~, I,G, Rate 2/ 3 ( = 4/ 6) Sampllnp dock Input dah 2 3 1 1 2 9 I

Rate t/2 I,O,I,O,i,~,I,a,I,O, I,p, i,0, I,a, ou~ul Punaured i~p~ 0,1,C,O, I,~, ~,lo boa.
ou~ut, rate 2l3 Rate a/ o Senrylinp dock _ 2 3 1 2 3 Rats 12 auglulI,U,I,GiI,~, I,O, I,p, I,G, PUnd7lred I Qp I O
Q G I

~ , ou~ut, rste v n Rate 5/ 8 SampNnp dock Input t 2 3 1 5 1 2 3 ~ 5 data Rete ~ ~,a, ~ ~,a, 4p, ~~~~~,aI,p,I,p, ~.p. ~,pr 12 ou~ut~ ~,a, ~ I,O, ~
~

Punduradi p p~, p,l. I,p,O,I, p ' ' 4 output. .
rNe SIB

Babe 7/ s Semplinp dodo Input 1 2 3 1 5 6 7 1 2 3 I 5 8 date Rete 4p, ~xpx 4po asps 4pv I~p~ ~xpn 4pa Lp.
12 output 4p. I,p, 4pe Punctured~ ~ p p p ~ p I p p I
' I

output, nte A block diagram of a convolutional encoder is shown in Fig. 33.
ps convenc_data convenc~unc_i data ps convent rdy convenc~unc_q data ps_convenc_flush convenc~unc rdy convenc_punc_flush aip_convent bypass mod samp_clk Figure 33: Convolutional Encoder block diagram This is a rate %i convolutional encoder with constraint length=7. Input is a serial bit-stream, output is rate %z encoded (two bits). Puncturing is not performed here.
In bypass mode, the first bit received is mapped to the I channel, and the second bit is mapped to the Q channel.
Table 25: Parallel-to-Serial Register Map There is a differential encoder here, which can be bypassed.
The default generator polynomials are Gl=133ocT and G2=171ocT. The generator polynomials are programmable.
DATA IN
Figure 20: Convolutional Encoder Block Diagram The code puncture block is shown in Fig. 34.

Table 26: Convolutional Encoder Register Map convenc~unc_i data punc_preable_i data convenc~unc_c~data punc_preamble_c~data convenc~unc_rdy punc~reamble_niy convenc~unc_flush punc~reamble_flush aip_convenc_bypass mod_samp Gk rate_sel(2:0) Figure 34: Code Puncture block diagram This block takes the rate %z output from the convolutional encoder and punctures the code to get rate 2/3, 3/4, 5/6, 7/8.
This block ensures that there is one 2-bit symbol on every other clock pulse of the sampling clock.
The puncturing patterns is programmable. A 16-bit register is provided for each puncturing rate. The register is arranged as a list of I & Q pairs. A 0 in the register means that the bit should be transmitted. A 1 means that the bit should be "punctured", or dropped from the transmission sequence.
Rate 2l3 1.1 ~~ 1.3 Output of Conv. Encoder Q.1 Q.2 Q.3 Q.4 1.1 ~ Q.2 Q.3 Output of Puncture Module Q Q.1 1.3 Q.4 Figure 21: Rate 2/3 (4/6) default puncturing pattern = OO100010xxxxxxxx Rate 314 1.1 ~--~~ 1.3 Punctured Data Q.1 Q.2 1.1 4.2 Output of Puncture Module Q Q.1 1.3 Figure 22: Rate 3/4 default puncturing pattern = OO1001xxxxxxxxxx Rate 5/6 1.1 ~/-~~ 1.3 ~ 1.5 Punctured Data Q.1 Q.2 I ~ Q.4 I 1.1 Q.2 D.4 Output of Puncture Module Q 4.1 ' ~ 1.3 1.5 Figure 23: Rate 5/6 default puncturing pattern = 0010011001 xxxxxx Rate 718 Punctured 1.1 ~~ ~ 1.5 ~ ~ CL7 I
Data Q.1 ~Q.2 Q.3 4.4 ~ ! Q.6 Output of I 1.1 G1.~ D.4 Q.s Puncture Module Q.1 Q.3 1.5 1.7 Figure 24: Rate 7/8 default puncturing pattern = 00101010011001 xx rate = 1 (bypass) rate = 1/2 rate = 2/3 rate = 3/4 rate = 5/6 0x00120004 Puncturing Rate Select R/W

default value = 3'b000 access macro = PUNC RATE SEL x 0x00120008 Rate 2/3 Puncture Pattern R/W

default value = 16'b0010001000000000 access macro = PUNC R23 x Ox0012000C Rate 3/4 Puncture Pattern R/W

default value = 16'b0010010000000000 access macro = PUNC R34 x 0x00120010 Rate 5/6 Puncture Pattern R/W

default value = 16'b0010011001000000 access macro = PUNC R56 x 0x00120014 Rate 7/8 Puncture Pattern R/W

default value = 16'b0010101001100100 access macro = PUNC R78 x Table 27: Puncturing Module Register Map The Preamble Insert block is shown in Fig. 35.
punc~reamble i data i preamble map data punc~reamble_~data preamble map_~data punt preamble rdy r preamble map dy punc~reamble flush preamble map flush mod same clk aip_current time(31:0) aip trigger time(31:0) ignore trigger preamble data(31:0) preamble length(5:0) flush data(31:0) flush length(5:0) pipeline delay(7:0) Figure 35: Preamble Insert block diagram The Preamble Insert block serves two functions. It provides fine-grain synchronisation to the sample clock for the output data. It also allows an uncoded bit sequence to be transmitted at the beginning and end of the output data.
The preamble is programmable from 0 to 128 bits in 2-bit increments. The flush word is programmable from 0 to 128 bits in 2-bit increments. Both have 6-bit repetition counts to allow for very long (but repeatable) preamble or flush sequences.
This block contains a FIFO that is 128 symbols deep, to account for clock fitter that can occur while crossing time-domains.
The current time is a 32-bit counter generated by the Air Interface Processor. Time 0 is defined as the start of the superframe. The trigger time is a 32-bit value which is set by the Air Interface Processor. The trigger time can be ignored via a programmable register; this is the typical configuration for a continuous modulator. The pipeline delay is a programmable register to provide a fixed time offset for the output data.

Up to four different preambles are supported at a time. The BURST
instruction in the AIP can be used to select the preamble for a given burst.
use_trigger:
if current_time = trigger_time:
if preamble_word defined:
shift out preamble_word shift out data if flush_word defined:
else:
data th shift out flush_word i ~ ~ ~ ~
0x00140004 ~ Preamble Data R/W
-0x00140010 default value = 128'h0 access macro = PREAMBLE_INSERT_PREAMBLE_DATA_x number of a%ments = 4 0x00140044 Preamble Length R/W
-0x00140050 default value = 8'h0 access macro = PREAMBLE_INSERT_PREAMBLE_LENGTH_x number of a%ments = 4 0x00140054 Flush Data R/W

default value = 128'h0 access macro = PREAMBLE INSERT FLUSH DATA
x 0x00140064 Flush Length R/W

default value = 8'h0 access macro = PREAMBLE INSERT FLUSH LENGTH
x 0x00140068 Ignore Trigger R/W

default value = 1'bi access macro = PREAMBLE INSERT IGNORE
TRIGGER x Ox0014006C Preamble Repeat R/W

default value = 6'h0 access macro = PREAMBLE INSERT PREAMBLE
REPEAT x 0x00140070 Flush Repeat R/W

default value = 6'h0 access macro = PREAMBLE INSERT FLUSH REPEAT
x Table 28:
Preamble Insert Register Map The Mapper block diagram is shown in Fig. 36.
preamble_map_i_data map_rc_i data(1:0) preamble_map_q_data map_rc_q_data(1:0) preamble map rdy map rc rdy preamble_map_flush map_rc_flush mod_samp clk aip_modulation sel(1:0) aip_qam l6~attem Figure 36: Mapper block diagram This block generates 1-bit I & Q values every other clock cycle for QPSK, and 2-bit I & Q values every four clock cycles for 16 QAM.
Input is a 2-bit symbol from the Puncturing module. For QPSK, the input is separated into I & Q channels. For 16 QAM, two successive inputs are required to generate 2-bit values for I & Q.
The following timing diagram shows the expected Mapper output ("Mapper I" & "Mapper Q"). Note that the Mapper pattern for 16 QAM is programmable (see register map below).
This module exists mainly for historical reasons, and is generally not used.
It was considered safer to leave it in the design rather than to take it out.

ii) ipu b lAapper Outpu from Purtcture AbdWe ~ d pn ij m S QAt.t. ! samples per symbol _ _ _ _. _ Mapper I ,c p Mapper O na fi OuputtoDAC vt v2 v7 v! vt m vs va two of tttesel PSK. 2 samples per symbol _ _ MaDDerl c p Mapper O ti d r n OulputWDAC vt v7 vt v2 vt v2 ~ v2 (two of fhese~
Ox001A0030 QAM-16 Pattern R/W
default value = 1'b1 access macro = MOD AM16 PATTERN x Table 29: Mapper Register Map The Differential Encoder block diagram is shown in Fig. 37.
in data(3:0) out data(3:0) in rdy out rdy in flush out flush aip_diffenc_bypass mod_byte_clk Figure 37: Differential Encoder block diagram The modulator Root Raised Cosine Filter block diagram is shown in Fig. 38.

map rc data rc dac data(7:0) map rc rdy map rc flush mod samp clk aip modulation sel(1:0) rc lut addr(9:0) re lut data(31:0) Figure 38: Modulator Root Raised Cosine Filter block diagram This is a 21-tap symmetric FIR filter with programmable taps. The taps must be programmed at system start-up, since they do not have initial values.
The taps are fixed-point numbers, with format <12, 0, t>.
The actual mapping from I & Q symbols to numbers in Cartesian co-ordinates occurs in this block. These constellations are fully programmable for QPSK
and 16-QAM. They too must be programmed by software at system start-up.
The constellation is programmed by assigning an (I,Q) pair to each possible QPSK or 16-QAM symbol. The (I,Q) pair is programmed as follows:
I value (3 bit signedQ value (3 bit signed number) number) 3'b101 = -3 3'b101 = -3 3'blll = -1 3'blll = -1 3'b000 = 0 3'b000 = 0 3'b001 = 1 3'b001 = 1 3b011=3 3'b011=3 There is a programmable option here to provide either 2's complement or unsigned values as the output samples. Most DACs operate on unsigned values.
Software must take care to select the right setting to ensure proper system operation.
0x00180004 - QPSK Pattern R/W
0x00180010 default value = 6'b000 000 access macro = MOD IQMAP_QPSK PATTERN x number of elements = 4 I I i III I,II I
0x00180014 16-QAM Pattern R/W
-0x00180050 default value = 6'b000 000 access macro = MOD IQMAP_QAM PATTERN x number of a%ments = 16 0x00180054 tap coefficients R/W
-Ox0018007C default value = 12'h0 access macro = MOD IQMAP_COEF x number of elements = 11 0x00180080 DAC Values Unsigned R/W

default value = 1'b0 access macro = MOD IOMAP DAC UNSIGNED x Table 30: Modulator RC Filter Register Map There is a power amp controller which is used in burst mode. This controller generates a pulse which turns on 0-7 samples before the burst of data, and turns off 0-31 samples after the burst of data.
The Power Amp Off register needs to be biased with an offset of +21 to account for propagation delays through the RC Filter.
~ aartp_ak modwalo~ axa idf_aip_match Table 31: Power Amp Register Map The SB7016 supports both burst-mode and continuous-mode demodulator operation. It can be configured in software to operate in the desired mode.
The demodulator supports both QPSK and 16-QAM modulation schemes.
The following features are programmable:
~ Burst or continuous mode transmission ~ Programmable frame format; optional preamble ~ QPSK or 16-QAM modulation; programmable constellations ~ Viterbi decoder polynomial and encoding rate ~ Convolutional Deinterleaving depth and delay; bypass ~ Reed-Solomon decoder; bypass ~ Descrambler polynomial and seed; bypass I

I data from ADC
Q data ~ ~ I I I I
from ADC RC Equalizer - u~
-.~
_, , Deinterleaver Frame CRC Verifier Descrambler Address Output; output Deformatter Filter Queuing data a a s12x8 RAM
dm-~ RS Decoder o~uc a~mer RAM (s12 x 64) ~v~
8 banks of 256x14 RAM ~ CIOCIC
Recovery Figure 25: Demodulator Top Level Block Diagram ~in The Demodulator section consists of the following major functional blocks:
~ Root Raised Cosine Filter ~ Continuous Demodulator ~ Burst Demodulator ~ Differential Decoder ~ IQ Generator ~ Convolutional (Viterbi) Decoder ~ Sync Detect ~ Serial-to-Parallel Converter ~ Deinterleaver ~ Frame Deformatter ~ Reed-Solomon Decoder ~ CRC Verifier ~ Descrambler ~ Address Filtering ~ Output Queuing ~ Clock Recovery Depending on the applications, the following functional blocks can be bypassed by software:
~ Differential Decoder ~ IQ Generator ~ Viterbi Decoder ~ Deinterleaver ~ CRC Verifier ~ Reed-Solomon Decoder ~ Descrambler At power-up, the Demodulator is held in a reset state. The software must write a '1' to the reset register to bring the Demodulator out of reset, at which point it is possible to configure any of the programmable options on the Demodulator side of the SB7016. After configuration, the Demodulator must be specifically enabled by asserting the Enable Register.
The following table shows the configuration of the Demodulator Bypass register. At power-up, all fixnctional blocks are bypassed. The user must specifically enable the desired blocks by setting the relevant bits to zero.
0 Descrambier Bypass 1 Oeinterleaver Bypass 2 Viterbl Decoder Bypass 3 Differential Decoder Bypass 4 Sync Detect Bypass RC Filter Bypass 6 Address Filter Bypass 7 Reed-Solomon Decoder Bypass 8 CRC Verify Bypass 9 Descrambler2 Bypass Frame Deformatter Bypass 11 Differential Decoder2 Bypass 12 Equalizer Bypass 13 Reserved i4 Reserved Reserved The Algorithm Select and Data Source registers are used to select whether the SB7016 is to operate in continuous or burst mode. Various loopback modes are also available, for debugging purposes.
Ol ~ burst mode 10 continuous 9'b??7 on-chip ADC

9'b??? external ADC

9'b000 modulator parallel-to-serial 000100 output (loapback) 9'b000_001000modulator puncturing output (loopback) 9'ti000_100000modulator samples (loopbadc) 9'b001_~?????burst mode 9'b010_?????7continuous mode, from carrier recovery The modulation format of the incoming data stream can be selected using the Demodulation Select register.
The ext mux_sel register can be used to send the output of various internal demodulator components to the O DBG DEMOD2 * pins. These pins can be used for debugging purposes, or to send a partially formatted and decoded data stream to an external device for further processing.
3'b001 Serial-to-Parallel 3'b010 Deinterleaver 3'b011 Frame Deformatter 3'b100 Descrambler2 3'b101 Outer Code 3'b110 Descrambler The External Processing Register can be used to force the SB7016 to ignore its demodulation circuitry, and to instead inject data from the I EXT DEMOD SYMS, I EXT DEMOD BITS, or I EXT DEMOD BYTES
inputs. This is intended as a debugging feature. Details are TBD.
There is a read-only RSSI register, which returns the Received Signal Strength Indicator value, as presented to the SB7016 by the analog circuitry.
Ox003C0004 Demodulator Enable R/W

default value = 1'b0 access macro = DEMOD ENABLE x Ox003C0008 Bypass Register R/W

default value = 16'hFFFF

access macro = DEMOD BYPASS x Ox003C000C Demodulation Selection R/W

default value = 2'b00 access macro = DEMOD DEMODULATION SEL
x Ox003C0010 Algorithm Select R/W

default value = 2'b10 access macro = DEMOD ALG SEL x Ox003C0014 Data Source W

I
default value = 9'b111 00000~~1 access macro = DEMOD DATA SOURCE x Ox003C0020 External ProcessingR/W

default value = T b0 access macro = DEMOD USE EXTERNAL x Ox003C0024 RSSI R/E

default value = 8 bits access macro = DEMOD RSSI x Ox003C0028 Debug mux_sel R/W

default value = 3'b000 access macro = DEMOD MUX SEL x Ox003C0018 Event Counter Readback R/E

default value = 32 bits access macro = DEMOD EVENT COUNTER x Ox003C002C Frame Count Limit R/W

default value = 32'h0 access macro = DEMOD COUNT LIMIT x Ox003C0030 Pipeline Delay R/W

default value = 16'd256 access macro = DEMOD PIPELINE DELAY x Ox003C0034 AIP Processor Delay R/W

default value = 16'd32 access macro = DEMOD AIP PROC DELAY x Ox003C0038 Ranging Offset R/W

default value = 10'd1 access macro = DEMOD RANGING OFFSET x The demodulator DSP block contains the RC Filter, Carner Recovery, Timing Recovery, Interpolator, Equalizer, and Burst Demodulator.
The continuous mode demodulator runs on a minimum of 2 samples per symbol. At low data rates, the demodulator oversamples the incoming analog signal.
This helps minimize the effect of pipeline delays in the multipliers, by giving more clock cycles in which to compute a mathematical result.
The continuous mode demodulator runs on a minimum of 2 samples per symbol. The burst demodulator runs on a minimum of 4 samples per symbol.

At low data rates, the demodulator over samples the incoming analog signal. The Clock Multiplication register must be programmed with the over sampling factorin use.
Ox001C0034 clock_multiplication R/W
default value = 6'b1 I access macro = RC CLOCK MUL x The demodulator Root Raised Cosine Filter block diagram is shown in Fig. 39.
adc rc data(5:0) rc sync data(11:1)) aip_rc-bypass demod samp clk Figure 39: Demodulator Root Raised Cosine Filter block diagram The Raised Cosine Filter block receives I & Q samples from the ADC (6 bits each). It must be instantiated twice, one for filtering I samples, and one for filtering Q samples.
This block can be bypassed so that the filtering can be performed with analog circuitry.
This is a symmetric 21-tap FIR filter with programmable taps. Note that the taps are the same for both instances of the filter, so the registers can be shared.
The taps must be programmed at system start-up, since they do not have initial values.
The taps are fixed-point numbers, with format <12,1,t>.
There is a programmable option here to interpret the incoming samples as either 2's complement or unsigned values. Most ADCs operate on unsigned values.
Software must take care to select the right setting to ensure proper system operation.

i Ox001C0004 tap coefficients< 12,O,t> R/W

default value = 12'b111111111111 access macro = RC COEF 0 x Ox001C0008 tap coefficients<12,O,t> R/W

default value = 12'b000000001010 access macro = RC COEF 1 x Ox001C000C tap coefficients<i2,0,t> R/W

default value = 12'b111111101011 access macro = RC COEF 2 x Ox001C0010 tap coefficients< 12,O,t> R/W

default value = 12'b000000010110 access macro = RC COEF 3 x Ox001C0014 tap coefficients< 12,O,t> R/W

default value = 12'b000000000110 access macro = RC COEF 4 x Ox001C0018 tap coefficients<i2,0,t> R/W

default value = 12'b111111100001 access macro = RC COEF 5 x Ox001C001C tap coefficients< 12,O,t> R/W

default value = 12' b000001010111 access macro = RC COEF 6 x Ox001C0020 tap coefficients<12,O,t> R/W

default value = 12'b111101100110 amess macro = RC COEF 7 x Ox001C0024 tap coefficients<12,O,t> R/W

default value = 12'b111100100111 access macro = RC COEF 8 x Ox001C0028 tap coefficients<12,O,t> R/W

default value = 12'b010010100001 access macro = RC COEF 9 x Ox001C002C tap coefficients<12,O,t> R/W

default value = 12'b011111111111 access macro = RC COEF 10 x Ox001C0030 ADC Values Unsigned R/W

default value = 1'b0 access macro = RC ADC UNSIGNED x Table 32: Demodulator RC Filter Register Map The timing recovery scheme used in the terminal demodulator is an all-digital implementation. Timing synchronization is achieved by means of a feedback loop that adjusts the phase and frequency of a locally generated clock to match the transmitted symbol clock. A locally generated clock at the AID converter samples the received baseband signal. It is assumed that the I and Q signal samples out of the A/D
converter are unsynchronized in phase and frequency to the transmitted symbol clock.
The I and Q signal samples are supplied to the received root raised cosine filters.
Following the root raised cosine filters, the signal samples are interpolated in such a manner as to produce the correct symbol strobes that are synchronized with the transmitted symbol clock.
Timing recovery loop provides the interpolator with tap-adaptation information. The interpolator is implemented as a series of cascaded look-up tables.
The look-up tables are programmable. Timing recovery precedes both equalization and carrier recovery, and therefore, operates on received signal samples that contain, in addition to sampling clock offsets, multipath distortion and carrier frequency and phase errors.
There is one Interpolator for each I and Q input stream. Control signals ("mu") are generated by the Timing Recovery circuit. The function of the Interpolator is to produce samples that are synchronised with the transmitting clock.
The Interpolator is implemented as a series of cascaded look-up tables. The look-up tables are programmable.
il Ox003E0004 Interpolator Taps R/W
-Ox003E0010 default value = 128'h0 access macro = INTERPOLATOR_LUT_VALS_x number of a%ments = 4 Ox003E0044 ai R/W

default value = 8'b00001100 access macro = INTERPOLATOR A1 x Ox003E0048 a3= a1+a2 R/W

default value = 8'b00011001 access macro = INTERPOLATOR A3 x Ox003E004C Loop Gain R/W

default value = 4'b0010 access macro = INTERPOLATOR LOOP GAIN
x Ox003E0050 Lock Count R/W

default value = 16'b0000000111110100 access macro = INTERPOLATOR LOCK COUNT
x Ox003E0054 block size R/W

default value = 16'b0000010000000000 access macro = INTERPOLATOR BLOCK SIZE
x Ox003E0058 mean scale R/W

default value = 10'b0001001100 access macro = INTERPOLATOR MEAN SCALE
x Ox003E005C beta R/W

default value = 8'b01111110 access macro = INTERPOLATOR BETA x Ox003E0060 beta comp R/W

default value = 8'b00000010 access macro = INTERPOLATOR BETA COMP~,x Ox003E0064 loop filter value R/E

default value = 12 bits access macro = INTERPOLATOR LOOP F OUT
x Ox003E0068 Lock Flag R/E

default value = 1 bits access macro = INTERPOLATOR LOCK FLAG x Ox003E006C Plag Count R/E

default value = 16 bits access macro = INTERPOLATOR FLAG COUNT
x Ox003E0070 Clear Accumulator R/W

default value = 1'b0 access macro = INTERPOLATOR CLEAR ACC x Table 33: Interpolator Register Map An Equalizer is employed to compensate for the Inter Symbol Interference (ISI) present in the received signal. The main sources of ISI are the multipath effects introduced by the channel, and the non-linearities in the amplifiers at both the transmitter and the receiver. The choice of the equalizer structure depends on the nature of the channel impairments. The proposed design of the equalizer is a structure that assumes the presence of both pre and post-cursor ISI in the equivalent complex baseband channel impulse response.
8s The Equalizer is implemented as a complex adaptive filter with 8-taps. The input to the FFE is the complex signal (I and Q channels) from the interpolator block.
LMS tap update algorithms are employed. Two types of tap update algorithms are implemented. The Constant Modulus Algorithm (CMA) allows initial tap updates in the presence of Garner phase and frequency offset. The Decision-Directed (DD) tap update mode is implemented to complete the convergence of the equalizer tap update process.
Provisions are also made to bypass/freeze the equalizer where not needed (satellite communication applications). Equalizer works in collaboration with Garner recovery system. The equalizer output is fed to the phase derotator.
0x00220004 Load Configuration R/W

default value = 1'b0 access macro = E LOAD x 0x00220008 FFE weights (I) R/W
-0x00220024 default value = 12'h0 access macro = E~CI x number of a%ments = 8 0x00220028 FFE weights (Q) R/W
-0x00220044 default value = 12'h0 access macro = E~C~x number of a%ments = 8 0x00220048 Mu R/W

default value = 12'b000000000001 access macro = E MU x ~a Ox0022004C R2 R/W

default value = 12'b000010000000 access macro = E R2 x ...~.~....~.

0x00220050 Current FFE weights Readback (I) R/E
-Ox0022006C default value = 12 bits access macro = E~CI CURRENT_x number of elements = 8 0x00220070 Current FFE weights Readback (Q) R/E
-Ox0022008C default value = 12 bits access macro = E~C~CURRENT x l number of a%ments = 8 0x00220090 lock det beta R/W

default value = 10'b0111111110 access macro = E BETA x 0x00220094 lock det 1-beta R/W

default value = 10'b0000000010 access macro = E BETA COMP x 0x00220098 Lock Count R/W

default value = 16'b0000000111110100 access macro = E LOCK COUNT x Ox0022009C block size R/W

default value = 16'b0000010000000000 access macro = E BLOCK SIZE x Ox002200A0 treshold_i R/W

default value = 12'b0000000100 access macro = E MEAN COMP VALUE x Ox002200A4 Lock Flag R/E

default value = 1 bits access macro = E LOCK FLAG x Ox002200A8 Flag Count R/E

default value = 16 bits access macro = E FLAG COUNT x Ox002200AC Clear lock average R/W

default value = 1'b0 access macro = E CLEAR ACC x Ox002200B0 select dd mode R/W

default value = 1'b0 access macro = E DD MODE x Ox002200B4 tap update enable R/W

default value = 1'b0 access macro-- EQ",UPDATE ENABLE x Ox002200B8 scale_cma R/W

default value = 12'b000001000000 access macro = E SCALE CMA x Ox002200BC scale_dd R/W

default value = 12'b000100000000 access macro = E SCALE DD x The carrier recovery loop compensates for the phase and frequency offsets that are present in the recovered baseband signal due to offsets between the transmit and receive local oscillators. The Garner recovery scheme implemented in the demodulator is an all digital implementation. The Garner recovery subsystem consists of the following blocks: the phase derotator, phase error detector, loop filter, acquisition control; phase accumulator and Sine and Cosine Look-Up Table (LUT).

CR block will stay 'inactive' upon power-up, until the Air Interface Processor (AIP) gives the Carner synchronization enable signal. Carrier loop operates in two modes: the initial frequency acquisition mode, and the tracking mode.
AIP
activates the Garner acquisition mode after the Equalizer CMA mode has converged.
Once, carrier acquisition has been achieved and the Garner loop is in tracking mode, AIP will initiate the equalizer decision-directed tap update mode. It is assumed that the frequency offset encountered by the CR loop is in the order of ~5% of the symbol rate. Carrier loop operates at a rate of one sample per symbol or at a reduced rate as determined by the specific application.
I~ I
Ox001E0004 Loop A1 R/W

default value = 8'b01001100 access macro = CR LOOP A1 x Ox001E0008 Loop A3=a1+a2 R/W

default value = 8'b00000110 access macro = CR LOOP A3 x Ox001E000C Loop Gain R/W

default value = 4'b0000 access macro = CR LOOP GAIN x Ox001E0010 Reset R/W

default value = 1'b1 access macro = CR RESET x Ox001E0014 down sampling(symbol) rate 1 2 3 or 4 R/W

default value = 2'b0 access macro = CR DOWN SYMBOL FACTOR x Ox001E0018 max transition for phase interpolator R/W

default value = 16'b0001100100000000 access macro = CR PHASE MAX TRANSITION
x Ox001E001C Lock Count value for in lock R/W

default value = 16'b0000001010111100 access macro = CR LOCK COUNT x Ox001E0020 mean scale R/W

default value = 10'b0001100110 access macro = CR M EAN SCALE x Ox001E0024 Step Size R/W

default value = 12'b000000100000 access macro = CR STEP SIZE x Ox001E0028 lock det block size R/W

default value = 16'b0000010000000000 access macro = CR BLOCK SIZE x Ox001E002C Swee Max Value W

i default value = 12'bi 1111111111 access macro = CR SWEEP MAX VALUE x Ox001E0030 Sweep Min Value R/W

default value = 12'b000000000000 access macro = CR SWEEP MIN VALUE x Ox001E0034 Symbol Max Value R/W

default value = 16'b001000000000000 access macro = CR SYMBOL MAX VALUE x Ox001E0038 lock det beta R/W

default value = 8'b01111110 access macro = CR BETA x Ox001E003C lock det beta R/W

default value = 8'b00000010 access macro = CR BETA COMP x Ox001E0040 Flag Count R/E
' default value = 16 bits access macro = CR FLAG COUNT x Ox001E0044 Carrier Lock R/E

default value = 1 bits access macro = CR LOCK x Ox001E0048 loopf_out R/E

default value = 12 bits access macro = CR LOOPF OUT x Ox001E004C sweep_value R/E

default value = 12 bits access macro = CR SWEEP VALUE x Table 34: Carrier Recovery Register Map The Ranging block diagram is shown in Fig. 40.

in_i data time offset(9:0) in_q_data out match in rdy out failed reset n demod samp_clk pn sequence(63a)) pn_length(5:0) aip_burst enable Figure 40: Ranging block diagram The ranging block performs the following functions:
~ contains a bit correlator that attempts to match the incoming I/Q data with the stored preamble sequence ~ measures the amount of time elapsed between start of aip burst enable asserted and when the PN sequence is detected ~ when aip burst enable goes low, either out match or out failed is asserted for one clock cycle, and time offset is loaded with the measured time elapsed if a match was found ~ correlator design is almost identical to the one in demod sync detect ~ pn sequence is stored as [I1, Q 1, I2, Q2, . . . ]
~ pn length is between 0 and 63, which indicates a PN length of 1 to 64 The Slicer performs a hard decision on the input sample (yn) in the following manner:
- 3 yn < -2 yn _ _ yn qn = + 11 Yn < +2 16 QAM qn + 1 I otherwo a I'SK
+ 3 otherwise The output of the Slicer is a hard decision of the processed sample. It can have one of 4 values (~1, ~3). These values are passed to the Carner Recovery, Timing Recovery, and IQ Generator modules. They are encoded in the following manner:

Ol -3 +1 11 +3 Figure 26: Slicer Output Encoding These codes are also used by the IQ Generator to get the actual bit value of the symbol represented by this dot.

om oom iom mn olio ooia ioio iiio , oioo 000o iooo moo oioi oooi iooi iioi I

QPSK Slicer 16-QAM Slicer Figure 27: Slicer A block diagram of the demodulator Differential Decoder is shown in Fig. 41.
in data(3:l)) d out ata(3:0) in rdy out rdy in frsync out frsync in sfrsync out sfrsync aip_diffdec_bypass demod_byte_clk Figure 41: Differential Decoder block diagram The IQ Generator block diagram is shown in Fig. 42.
sync iqgen_i data(1:0) iqgen_vitdec i data sync iqgen_q data(1:0) iqgen vitdec_q_data sync iqgen rdy iqgen_vitdec_ rdy demod same clk aip_iqgen~h amb(3:0) Figure 42: IQ Generator block diagram The IQ Generation module performs two functions. It compensates for phase ambiguity by performing the reverse rotation operation. It also performs the reverse operation of the Mapper on the modulator; QPSK samples are passed through, QAM samples are split up and fed into the Viterbi decoder.
This module presents 1-bit I and Q samples to the Viterbi Decoder for decoding.
The constellations are fully programmable. They must be programmed by software at system start-up, since they do not have initial values.
The IQ Generator can rotate all incoming symbols if so instructed by the phase ambiguity register. The value in the phase ambiguity register determines the number of times the symbol is rotated counter-clockwise by 90°. The arrows in the diagram of Fig. 28 show the effect of rotation on the symbol.
Figure 28: IQ Generator Symbol Rotation om oom iom mn ____ _ _ ______-aiio ooio ioio iiio U
oioo 000o iooo moo oioi , oooi iooi , W

0x00240054 Phase Ambiguity R/W
default value = 2'b00 I access macro = DEMOD IOGEN PH AMB x Table 35: IQ Generator Register Map The Convolutional (Viterbi) Decoder is shown in Fig. 43.
i data_in data out cLdata in rdy_out rdy_in aip vitd_bypass demod_samp Gk vitd aip numbits(15:0) vitd aip numerrs(15:1)) Figure 43: Convolutional (Viterbi) Decoder block diagram The Convolutional (Viterbi) Decoder is a Rate %z Viterbi Decoder with a constraint length of K=7 and traceback length of K*7=49. The decoder is a hard-decision decoder. A soft-decision decoder may be used in a future revision of this chip.
The generator polynomials are programmable. The decoder shall be optimised to ignore depunctured input bits. The decoder has a built-in differential decoder, which may be bypassed via the bypass register.
To support different convolutional encoding rates, there is a depuncturing unit in front of the Viterbi Decoder. It is programmable, similar to the Puncturing module on the Modulator.

It takes rate 2/3, 3/4, 5/6, or 7/8 data and converts it to rate 1/2 format by inserting ("depuncturing") extra symbols into the data stream. The value of the extra bit is not important, since depunctured bits are flagged by asserting the "ignore bits"
signal. This allows the Viterbi decoder to ignore these bits during metric computation.
This block performs rate adaptation between demod samp clk and demod bit clk domains.
0x00260004 Viterbi Decoder Generator PolynomialR/W

default value = To133 access macro = VITDEC POLY G1 x 0x00260008 Viterbi Decoder Generator PolynomialR/W

default value = 7'0171 access macro = VITDEC POLY G2 x Ox0026000C flush bits R/W

default value = 3'h0 access macro = VITDEC FLUSH BITS
x 0x00260010 Puncturing Rate Select R/W

default value = 3'b000 access macro = VITDEC RATE SEL x 0x00260014 Rate 2/3 Puncture Pattern R/W

default value = 16'b0010001000000000 access macro = VITDEC R23 x 0x00260018 Rate 3/4 Puncture Pattern R/W

default value = 16'b0010010000000000 access macro = VITDEC R34 x Ox0026001C Rate 5/6 Puncture Pattern R/W

default value = 16'b0010011001000000 access macro = VTTDEC R56 x 0x00260020 Rate 7/8 Puncture Pattern R/W

default value = 16'b0010101001100100 access macro = VITDEC R78 x 0x00260024 Puncture Pattern Skip W/p default value = 1'b0 access macro = VITDEC PATTERN SIQP
x 0x00260028 Symbols Processed R/E/S

default value = 32 bits access macro = VITDEC SYMS PROCESSED
x The Sync Detect block is shown in Fig. 44.
sd data in sd data out sd_rdy_in sd_rdy_out sd_sfrsync sd frsync sd_aip lock aip_sd_bypass demod bit clk sync_pattern(31:0) sync~attern_length(4:0) frame size(15:0) num match(7:0) missed_sync_limit(7:0) frame_marker(63:0) frame marker length(6:0) superframe_marker(63:0) superframe_marker length(6:0) Figure 44: Sync Detect block diagram The Sync Detect block attempts to detect patterns of Sync Words in the data stream. The number of Sync Words is programmable between 0 and 2. One of these Sync Words is the Superframe marker, the other is the Frame marker. The length of each Sync Word is programmable, as is the Sync Word itself. The maximum Sync Word length is 64 bits. The Sync Word length need not be a multiple of 8 bits. The Sync Word length should be set to 0 to disable that particular Sync Word. The Sync Words must be programmed MSB-aligned.
The Sync Pattern defines a pattern of Superframe and Frame Sync Words, each separated by "frame size" bits. The Sync Pattern is programmable up to 16 markers in length. The pattern is specified MSB-aligned, using the following encoding scheme:

~'ii!G
00 end-of- attern O1 ex ect Frame Word ect Su ertrame Word 11 undefined Table 37: Sync Pattern Encoding Scheme The Sync Detect module has 2 states of operation, "acquisition" and "tracking". In Acquisition mode, a number of counters are used to attempt to detect the pattern of Sync Words in the bit stream. When the Sync Words have been detected "num match" consecutive times, the Sync Detect module switches to Tracking mode.
Output data is qualified with the "sd sp rdy" signal only when the Sync Detector is in Tracking mode.
The Sync Pattern is composed of sixteen 2-bit fields. Each field must be programmed with the Sync Word expected in that pattern. The code 2'b01 is used to represent an expected Frame Sync, and the code 2'b 10 to represent an expected Super Frame Sync.
The Watermark register is available to monitor the progress of the acquisition process. Details are TBD.
For MPEG, the Sync Words are 47h (Frame) and B8h (Superframe). The Sync Pattern is BBh, 47h, 47h, 47h, 47h, 47h, 47h, 47h. This pattern is represented by programming the Sync Pattern Length register with 8, and setting the Sync Pattern to a value of 32'h9555000. The Num Match register should be set to 4, and the Missed Sync register should be set to 3. These must be programmed by software at system start-up, since there are no initial values.
This module is not needed for the burst demodulator (base station) because it is already synced to the start of a transmission. In burst mode, the Sync Detect module must be programmed to bypass mode.

I i default value = 64'h0 access macro = SD FRAME MARKER MASK x 0x00280014 Superframe Marker R/W

default value = 64'h0 access macro = SD SUPERFRAME MARKER x Ox0028001C Supertrame Marker Mask R/W

default value = 64'h0 access macro = SD SUPERFRAME MARKER MASK
x 0x00280024 Missed Sync Limit R/W

default value = 8'h0 access macro = SD MISSED SYNC LIMIT x 0x00280028 Num Match R/W

default value = 8'h0 access macro = SD NUM MATCH x Ox0028002C Frame Size R/W

default value = 16'h0 access macro = SD FRAME SIZE x 0x00280030 Sync Pattern R/W

default value = 32'h0 access macro = SD SYNC PATTERN x 0x00280034 Sync Pattern Length R/W

default value = 5'h0 access macro = SD SYNC PATTERN LENGTH x 0x00280038 Sync Lock R/E

default value = 1 bits access macro = SD SYNC LOCK x Ox0028003C Sync Lost R/E/S

default value = 1 bits access macro = SD SYNC LOST x 0x00280040 Number of Syncs Detected R/E/S

default value = 32 bits access macro = SD NUM SYNCS x 0x00280044 Watermark R/E/S

default value = 32 bits access macro = SD WATERMARK x Table 38: Sync Detect Register Map The Serial to Parallel converter block diagram is shown in Fig. 45.
sd sp_data sp diffdec data(7:0) sd_sp_rdy sp_diffdec rdy sd_sp frsync sp diffdec frsync sd_sp sfrsync s p diffdec sfrsync demod samp_clk demod_byte_clk Figure 45: Serial to Parallel block diagram The Serial to Parallel converter block is the transition point between the sampling clock and byte clock domains. The Serial-to-Parallel Converter performs the rate adaptation across time domains. This block simply takes in data and stuffs it into 8-bit symbols.
The serial bit stream is sent in either MSB first or LSB first order (programmable). Data is sent LSB first if the SP Invert Bits register is programmed to 1.
Incoming data need not be continuous. The Frame Sync and Superframe Sync strobes, which are asserted on the first bit of the sync data, must be carned over to the byte clock domain and asserted on the first byte of the sync data.
Ox003C001C SP Invert Bits R/W
default value = f b0 access macro = DEMOD SP INVERT BITS x Table 39: Serial-to-Parallel Register Map The Deinterleaver block is shown in Fig. 46.
diffdec deint data(7:0) deint oc data(7:0) diffdec deint_niy deint oc niy diffdec deint sfrsync deint oc sfrsync diffdec deint_frsync deint oc frsync aip_deint bypass demod sym clock depth sel(3:0) Figure 46: Deinterleaver block diagram The Deinterleaver performs inverse operation of Interleaver. The Deinterleaver performs convolutional interleaving as per EN 300 421.
The depth and delay parameters are programmable. The product of depth and delay must be less than or equal 256. The deinterleaving period (and thus frame size) is therefore limited to 256.

Table 40: Deinterleaver Register Map The Frame Deformatter performs rudimentary pattern matching on the demodulated data stream, under the command of the Air Interface Processor.
Received bytes are matched to an expected frame or timeslot format, and flagged with attributes that are passed to the remaining downstream hardware for processing before being written in the Output Queues.
The attributes that are tagged are similar to those tagged on the Modulator side:
~ whether or not the byte should be descrambled ("fdf descr bypass") ~ the type of outer code decoding to be applied to each byte ("fdf outer code sel") ~ whether or not the byte should be copied to the output FIFO ("fdf oc keep") The Frame Deformatter, like the Frame Formatter, contains 16 control words, which are special characters up to 8 bits in length. Unlike the Frame Formatter, the control words in the Frame Deformatter are qualified by mask bits.
The control words must be set up by software beforehand.
The commands the Frame Deformatter must respond to are shown in Table 41.
'i 0 0 0 0 1 DATA ueue Table 41: Frame Deformatter Command Codes The NOP command is the command that the Frame Deformatter receives when the Demodulator is not running, or when there is no incoming data.
A DISCARD command matches any incoming data. The KEEP attribute is not set. The data will still be passed through the Reed-Solomon decoder, Descrambler, and Address Filter. It will not, however, be stored in the Output FIFO.
l02 A DATA command matches any incoming data. The KEEP attribute is set.
The QUEUE attribute will be set to the value specified in Q.
A CW command compares the control word number N with the incoming data. If a match is found, the Microsequencer will perform a conditional branch to the address specified in the ADDR field. If a match is not found, the Microsequencer will continue with the next address. In either case, the KEEP attribute is not set.
The match is successful if the following logical condition holds:
(incoming data AND cw mask) = cw data A CDATA command performs the same function as the CW command.
However, the KEEP attribute will be set, and the QUEUE attribute will be set to the value specified in Q.
The SYNC, FRSYNC, and SFRSYNC commands indicate that the Frame Deformatter should discard all incoming data until a Sync is found. In the case of the SYNC command, either a Frame Sync or a Super Frame Sync will cause a match;
FRSYNC and SFRSYNC cause the Frame Deformatter to wait for a specific Frame or Super Frame Sync, respectively. The data is discarded if the K bit in the command is not set; if it is set, then QUEUE attribute will be set to the value specified in Q.
Note that the various SYNC commands are different from the SYNC
attribute. The SYNC command causes the Frame Deformatter to wait for a Sync.
Depending on the frame format in use, it may be desirable to reposition this Sync, to allow better filtering of incoming data using the Address Filter.
Byte dock ksync 16! dense dah R R ~ 47h md1 cnd2 .cndi ~~ _~ 0 D R R
eip_idf_cmd -SYNC --- ~ DISCARD.S.OCn ~ pATAS.OCn DISCARD
---_-tdf_aip rm~ch 1df_oc-rdy idf_oe_deta R R ~ 47h md1 arU2 md3 D R R R
tdt oc_keep ~ desa_bypaee ~ oubr_oode_sel DCn ----------------_----I
0x00340004 Control Word R/W
-0x00340040 default value = 8'b00000000 access macro = DEMOD_FDF_CW_DATA_x number of a%ments = 16 0x00340044 Control Word Mask R/W
-0x00340080 default value = 8'b00000000 access macro = DEMOD_FDF_CW_MASK_x number of a%ments = 16 Table 42: Frame Deformatter Register Map The Demodulator Outer Code Decoder module contains the CRC Verifier and the Reed-Solomon Decoder, in that order. This block enables the appropriate decoder depending on the "aip outer code sel" signal. This scheme allows up to four decoding schemes to be in use during normal system operation without requiring any software intervention.
The mapping between "aip outer code sel" and decoding scheme is fully programmable. There is a register for each combination of "aip_outer code sel", with the following format:
Table 43: Demodulator Outer Code Select Register Format It is possible to have both the CRC Verifier and the RS Decoder active for any given burst.
This block contains some statistics counters: total number of bytes processed, number of CRC errors detected, number of RS errors detected, and number of incorngible RS frames detected. All counters are self clearing: they return to zero when read by the software.

The implementation of this block actually contains two Reed-Solomon decoders. Incoming frames are sent to alternate decoders, and the results of each decoder are then recombined at the output. This is to compensate for some limitations in the Hammercores decoder, which requires a number of clock cycles between successive frames.
a ~ ~~ ~ ~ ~ ~ ~ ~ ~ ~ ;-Ox002E0004 Outer Code 0 R/W

default value = 18'h3_00_00 access macro = DEMOD OUTER CODE OUTER CODESEL
0 x Ox002E0008 Outer Code 1 R/W

default value = 18'h2_cc_10 access macro = DEMOD OUTER CODE OUTER CODESEL
1 x Ox002E000C Outer Code 2 R/W

default value = 18'h2 44 08 access macro = DEMOD OUTER CODE OUTER CODESEL
2 x Ox002E0010 Outer Code 3 R/W

default value = 18'h2 3f 0a access macro = DEMOD OUTER CODE OUTER CODESEL
3 x Ox002E0014 Bytes Processed R/E/S

default value = 32 bits access macro = DEMOD OUTER CODE BYTE COUNT_x Ox002E0018 CRC Errors R/E/S

default value = 32 bits access macro = DEMOD OUTER CODE CRC ERR
COUNT x Ox002E001C RS Decoder Errors R/E/S

default value = 32 bits access macro = DEMOD OUTER CODE RSDEC ERR
COUNT x Ox002E0020 RS Decoder Invalid Frames R/E/S

default value = 16 bits access macro =

DEMOD OUTER CODE RSDEC INVALID FRAMES x Ox002E0024 RS Decoder Burst Hack R/W

default value = 1'b0 access macro = DEMOD OUTER CODE RSDEC BURST
HACK x Table 44: Outer Code Decoder Register Map The Reed-Solomon Decoder is shown in Fig. 47.
deint oc data(7:0) rsdec des data(7:0) deint oc rdy rsdec des rdy deint oc sfrsync rsdec des sfrsync deint oc frsync rsdec des frsync oc rsdec bypass demod_byte clk rsdec code sel(3:0) rsdec_aip numerr(4:0) rsdec aip_decerr Figure 47: Reed-Solomon Decoder block diagram The Reed-Solomon Decoder module operates on the DVB polynomial, and can be shortened to RS(x, y) for any value of x and y up to RS(255,235, t=20).
Specifically, the following Reed-Solomon codes are supported.
RS(204, 188, t=8) RS(68, 60, t=4) RS(63, 53, t=5) This module performs whatever correction it can. The number of errors corrected or detected is reported to the Processor Interface. The redundant bytes are not discarded (they must be tagged for discard using the Frame Deforrnatter).
The RS Decoder implementation used is a COTS decoder core by Hammercores.

The CRC Verifier block is shown in Fig. 48.
deint oc data(7:0) crcv oc data(7:0) deint oc rdy crcv oc rdy deint oc sfrsync deint oc frsync oc crcv_bypass demod byte clk Figure 48: CRC Verifier block diagram Some systems use CRC to verify the received data instead of the Reed-Solomon code.
" ~, I I ' I , I" ,I~~ , !, v 0x00300004 i~ I i i, - Data Mask R/W

0x00300080 default value = 8'h0 access macro = CRCV DATA_MASK_x number of a%ments = 32 0x00300084 CRC Mask R/W
-0x00300100 default value = 32'h0 access macro = CRCV CRC_MASK_x number of a%menLs = 32 0x00300104 CRC Byte Count R/W

default value = 3' h4 access macro = CRCV CRC BYTE COUNT
x 0x00300108 Data Byte Count R/W

default value = T h8 access macro = CRCV DATA BYTE COUNT
x Table 45: CRC Verifier Register Map The Descrambler block is shown in Fig. 49.
oc_ _ _des data(7:0) des fd_data(7:0) oc des_rdy des fd_rdy oc_ _des_sfrsync des fd_sfrsync oc_ _des frsync des fd_frsync aip_des_bypass demod byte clk des seed(15:0) polynomial(15:0) Figure 49: Descrambler block diagram The Descrambler performs the reverse operation of the scrambler. The Descrambler Control register controls when the pseudo-random binary sequence is advanced, and when it is reset. There is one of these registers for each of the 2 Descrambler circuits.
The Descrambler polynomial and seed registers have the following format:
There is a Mode register, which must always be programmed to 0.

Table 46: Decrambler Control Register Format The Burst Data Header does the following:
~ attaches 10 byte prefix to every burst of data (only in burst mode) ~ data format is:
struct 3;
unsigned char header_length; // 10 for Ss7016-al unsigned char header_flags;
unsigned short burst id; // from aiP "BURST" instruction unsigned short timing_offset; // from ranging module (10 bits) unsigned short frequency_offset;
unsigned short received_power;
The "header flags" field is defined as follows:
The "timing offset" field is the number measured by the Ranging block, and is in units of samples.

Table 47: Descrambler Register Map Ox004C0004 Header Flags R/W
default value = 5'b00000 access macro = BDMUX HEADER FLAGS_x The Address Filter block is shown in Fig. 50.
in data(7:0) out data(7:0) in rdy out rdy in frsync out sync in sfrsync in_queue(1:0) out_queue(1:0) in keep out keep aip_adrfilt bypass demod_byte_clk filter defined(7:0) pass_if match(7:0) address_data(7:0)(31:0) address_mask(7:0)(31:0) Figure 50: Address Filter block diagram The address filter can be used to filter data packets that either match or do not match a specific bit sequence. For MPEG applications, the address filter can be programmed to do PID filtering. For ATM applications, the address filter could be used to filter out unwanted VPI/VCI combinations, or cells based on the PTI/CLP
flags (although this would depend very much on the frame structure used).
Pattern matching is performed on the first four bytes of the packet. The start of a packet is defined as the first byte for which either "in frsync" or "in sfrsync" is asserted. The end of a packet is defined as the last byte for which neither "in frsync" nor "in sfrsync" is asserted.
Up to 32 patterns can be defined. A pattern is defined if the "filter defined" bit is set. Patterns not defined shall be ignored. Each pattern has a data and mask value. The pattern is matched if the following logical condition holds:
(incoming data AND address mask) = address data If one of t he defined patterns is matched and the corresponding "pass if match" bit is set, the entire packet is sent as output. Alternately, if one of the defined patterns is not matched and the corresponding "pass if match" bit is not set, the entire packet is also sent as output.

The behaviour of this module is undefined for the case where one pattern match indicates that the data should be sent, and another indicates that the data should not be sent. The software must ensure that the module is configured in such a way that this does not happen.
In bypass mode, the input data is sent directly to the output data.
i i~ ~ ~~~i~ ~i ~~~~ i 0x00380004 j i il~ ~'I ' ~''Ij~ ~, R/W
- Address Data ~
~I

0x00380080 default value = 32'h0 access macro = ADRFILT ADDR_x number of elements = 32 0x00380084 Address Mask R/W
-0x00380100 default value = 32'h0 access macro = ADRFILT_MASK_x number of elements = 32 0x00380104 Filter Defined R/W

default value =

32'b0000 0000 0000_0000_0000_0000_0000_0001 access macro = ADRFILT FILTER DEFINED
x 0x00380108 Pass If Match R/W

default value =

32'b0000 0000 0000_0000_0000 0000 0000_0001 access macro = ADRFILT PASS IF MATCH
x Table 48: Address Filter Register Map The Output Queuing block is shown Fig. 51.
atm_mode cpu_iq_add(11:0) cell_discard_n(3:0) cpu_iq_data(63:0) lineation_en 8~ hec_check_en ~

iq_cpu data out(63:0) start_pointer(7:0)(8:0) cpu_iq_data rdy end_pointer(7:0)(8:0) cpu_iq_r wn max_queue_size(7:0)(8:0) iq cpu_error alpha(3:0) oq_high_q_interrupt(3:0)d elta(3:0) rx_data(7:0) den'10d Oq header(3:0)(39:0) --rx oq_keep enb_n utopia oe - -end of burst nc_soc oq_rdy rx~rty oq data(7:0) nc_clav processor type nc clk _ atm fifo overflow x60 clk _ x60 fifo_overflow demod_byte clk hec_error~ulse Figure 51: Output Queuing block diagram The Input Queuing block has two data destinations:
~ Utopia TX block (ATM mode) ~ Data to processor The Output Queue supports two classes of data, with a FIFO for each. The FIFOs are implemented using a dual-port synchronous 512 * 64 bit RAM for the 4 data queues and 512*8 bit RAM for the ATM queue. The data queue FIFO depths shall be configurable by software, as required for a particular system.
The data at oq_data shall be stored in the queue given by ocLqueue or in the ATM queue if in ATM mode if both oq_rdy and oq_keep are high., When in burst mode the AIP should strobe end of burst with the rdy of the last byte of the burst.
The input queuing will then flush the remaining data from the serial parallel converter (8 bits input to 64 bits memory).
The module shall keep track of the number of bytes in each FIFO at all times. When this count exceeds a programmable threshold (max_queue size), an interrupt shall be generated on the processor bus.
For Utopia, the queuing module must perform ATM cell delineation using the HEC. As programmable options, the Utopia queuing portion of the module shall perform the following functions:
ATM cell delineation using HEC
ATM cell discard for invalid HEC
~ 4 programmable ATM cell discard (Ex: idle, F1, F3) I ~'~~
Out i''~~, I ~
put~
ueuin D 0 0 0 Data LSB R debu 31:0 Memory Address (8:0) 0 0 1 0 Data MSB R debu 63:32 0 1 1 - ueue 0 Data from R
ueue 2b01 1 0 1 - ueue 0 Data ueue R debu size 1 1 0 0 - ueue 0 Read PointerW debu 1 1 0 1 - ueue 0 Write PointerW debu 1 1 1 - 0 Software W debu Reset Table 49: Output Queuing Memory Map i 0x00360004 Queue End Pointer R/W
-0x00360010 default value = 9'h0 access macro = OQ_END_POINTER x number of a%ments = 4 0x00360014 Maximum Queue Size R/W
-0x00360020 default value = 9'h0 access macro = OQ_MAX_QUEUE_SIZE_x number of elements = 4 0x00360024 Queue Start Pointer R/W
-0x00360030 default value = 9'h0 access macro = OQ_START POINTER_x number of a%ments = 4 0x00360034 ATM alpha R/W

default value = 4'h0 access macro = 0 ALPHA x 0x00360038 ATM delta R/W

default value = 4'h0 access macro = 0 DELTA x Ox0036003C ATM cell discard_n R/W

default value = 4'bi l11 access macro = O CELL DISCARD N x 0x00360040 ATM HEC check enable R/W

default value = 1'b0 access macro = O HEC CHECK EN x 0x00360044 ATM cell delineation enable R/W

default value = 1'b0 access macro = O CELL DELINEATION EN x 0x00360048 ATM HEC error count R/E/S

default value = 8 bits access macro = 0 HEC ERROR COUNT x Ox0036004C ATM Queue Enable R/W

default value = 1'b1 access macro = O ATM UEUE EN x 0x00360050 ATM Discard Header R/W
-Ox0036005C default value = 40'h0 access macro = OQ_HEADER_x number of a%ments = 4 0x00360070 OQ ATM Master mode enable R/W

default value = 1'b0 access macro = 0 MASTER MODE EN x Table 50: Output Queuing Register Map Cell delineation (from ITU-T L432) is performed by using the correlation between the header bits to be protected (32 bits) and the relevant control bits (8 bits) introduced in the header by the HEC (header error control) using a shortened cyclic code with generating polynomial xg + x2 + x + 1.
Figure 52 shows the state diagram of the HEC cell delineation method.
NOTE - The "correct HEC" means the header has no bit error (syndrome is zero) and has not been corrected.
The details of the state diagram are described below:
1) In the HUNT state, the delineation process is performed by checking bit by bit for the correct HEC (i.e. syndrome equals zero) for the assumed header field. For the cell based Physical Layer, prior to scrambler synchronization, only the last six bits of the HEC are to be used for cell delineation checking. For the SDH-based interface, all 8 bits are used for acquiring cell delineation. Once such an agreement is found, it is assumed that one header has been found, and the method enters the PRESYNCH
state. When octet boundaries are available within the receiving Physical Layer prior to cell delineation as with the SDH-based interface, the cell delineation process may be performed octet by octet.
2) In the PRESYNCH state, the delineation process is performed by checking cell by cell for the correct HEC. The process repeats until the correct HEC
has been confirmed DELTA times consecutively. If an incorrect HEC is found, the process returns to the HUNT state.
3) In the SYNCH state the cell delineation will be assumed to be lost if an incorrect HEC is obtained ALPHA times consecutively.
Bit by bit ALPHA Cell consecutive by incorrect HEC cell Cell by cell Cell delineation state diagram Figure 52: Cell delineation state diagram The parameters ALPHA and DELTA are to be chosen to make the cell delineation process as robust and secure as possible while satisfying the performance specified in 4.5.2.
Robustness against false misalignments due to bit errors depends on ALPHA.
Robustness against false delineation in the resynchronization process depends on the value of DELTA.
For the SDH-based physical layer, values of ALPHA = 7 and DELTA = 6 are suggested.
For the cell-based physical layer, values of ALPHA = 7 and DELTA = 8 are suggested.
The Clock Recovery module is a generalised implementation of the MPEG
PCR synchronisation algorithm.
This circuit provides the following features:
~ User programmability for timestamp extraction algorithms ~ Protocol based timestamp generation for base stations.
~ Protocol based timestamp extraction for terminal stations.
~ Clock recovery for terminal stations.
~ Super Frame generation and detection.
~ DDS clock with a resolution of .lHz, averaged over 10 seconds The Clock Recovery circuit consists of 2 major blocks: the Timestamp Extractor and the Clock Controller.
The block has 2 modes of operation: base station and terminal. In the base station mode, the circuit generates a local reference clock (I DDS REF CLK) and a timestamp for the terminals. In the terminal mode, the circuit recovers the timestamp from the data stream, which it uses to synthesise a local DDS clock (O DDS SYN CLK OUT).

The Timestamp Extractor block is activated only in terminal mode. Its main function is to recover the protocol dependent timestamp from the downstream data.
The Timestamp Extractor circuit is enabled by asserting the Timestamp Extraction Control register.
The Timestamp Extractor circuit parses the incoming data stream and extracts the embedded timestamp. The circuit is based on a programmable byte processor. The user must program the circuit with byte manipulation instructions that extract the timestamp depending on the data stream protocol.
The timestamp extractor is sequenced by byte arrival times. All instructions run in 1 clock cycle. The timestamp extractor performs all branch, store and CRC
operations in parallel. The defined instruction word is 64 bits wide; the instructions are stored in a small 64x64 RAM, which provides space for 64 instructions. The SES-Astra program requires 11 instructions; the DOCSIS program requires 20.
The circuit is activated by the SYNC attribute. The circuit then runs until the end of its instruction sequence, where it halts until the next SYNC is received. The timestamp extracted can be up to 6 bytes long.
To accommodate DOCSIS, a CRC-CCITT 16 circuit is incorporated into the Timestamp Extractor block.
Once a timestamp is recovered from the incoming data stream, a flag is set and the timestamp is presented to the Clock Control block.
0 ~ timestamp ready 1 HCRC error 2 MCS CRC error default value = 3 bits access macro = CPU TS XTRCTR TS STATUS
x 0x00440010 timestamp data Isb R/E

default value = 32 bits access macro = CPU TS XTRCTR TS REG 4 1 x 0x00440014 timestamp data msb R/E

default value = 16 bits access macro = CPU TS XTRCTR TS REG 6 5 x 0x00440018 general purpose registers R/E

default value = 32 bits access macro = CPU TS XTRCTR GEN BYTE 4 1 x 0x00880000 Timestamp Extractor Memory R/W
-Ox008800FC access macro = TSX_MEM_x number of elements = 64 The clock controller operates in two modes: base station or terminal. In the base station mode it is programmed to generate a reference clock and from the same clock, a timestamp. In the terminal mode, the circuit is programmed to synchronise a local DDS clock to the base station reference clock. The synchronisation method is based on comparing the local timestamp with the one sent by the base station.
Refer to the System Synchronisation section for more details.
The clock control block also generates the super frame pulse.
This is the main control engine. This block performs the following functions:
~ Implement a protocol dependent timing recovery algorithm in the terminal station mode ~ Provide an accurate time base for base station mode ~ Lock on and track an upstream clock reference ~ Control the frequency selection of the DDS
~ Control the resetting of the DDS TS counter ~ Filter out erroneous timestamps ~ Monitor the timestamp arrival times ~ Synchronise the timestamp values, which are generated from 2 asynchronous clocks Ox003A0004 cpu access ID reg R/E

default value = 16 bits access macro = CPU TS CLK CNTL BLKID x Ox003A0008 clock recovery and generation control R/W

default value = 11'h0 access macro = CPU TS CLK CNTL CONTROL
x Ox003A000C clock recovery and generation status R/E

default value = 8 bits access macro = CPU TS CLK CNTL STATUS x Ox003A0010 timestamp loss threshold R/W

default value = 8'h0 access macro = CPU TS CLK CNTL TS LOSS
THRSHLD x Ox003A0014 timestamp delta max R/W

default value = 32'h0 access macro = CPU TS CLK CNTL TS DELTA
MAX x Ox003A0018 window timebase terminal count R/W

default value = 32'h0 access macro = CPU TS CLK CNTL WTB TC x Ox003A001C timestamp load Isb R/W

default value = 32'h0 access macro = CPU TS CLK CNTL SWTS FIELD
LSB x Ox003A0020 timestamp load msb R/W

default value = 10'h0 access macro = CPU TS CLK CNTL SWTS FIELD
MSB x Ox003A0024 timestamp inc load Isb R/W

default value = 8'h0 access macro = CPU TS CLK CNTL SWTS INC
FIELD x Ox003A0028 SES timestamp spacer field R/W

default value = 6'h0 access macro = CPU TS CLK CNTL SWTS SES
FIELD x Ox003A002C superframe timestamp Isb R/W

default value = 32'h0 access macro = CPU TS CLK CNTL SF TS LSB
x Ox003A0030 superframe timestamp msb R/W

default value = 10'h0 access macro = CPU TS CLK CNTL SF TS MSB
x Ox003A0034 supertrame generator terminal count R/W

default value = 32'h0 access macro = CPU TS CLK CNTL SF TC CNT
x Ox003A0038 superframe strobe length value R/W

default value = 8'h0 access macro = CPU TS CLK_CNTL SF STRB
LEN x Ox003A003C timestamp data Isb WE

default value = 32 bits access macro = CPU TS CLK CNTL TSD FIELD
LSB x Ox003A0040 timestamp data msb R/E

default value = 10 bits access macro = CPU TS CLK CNTL TSD FIELD
MSB x Ox003A0044 timestamp count Isb R/E

default value = 32 bits access macro = CPU TS CLK CNTL TSC FIELD
LSB x Ox003A0048 timestamp count msb R/E

default value = 10 bits access macro = CPU TS CLK CNTL TSC FIELD
MSB x Ox003A004C Freq parameter NP number per loop slow R/W
-Ox003A0088 default value = 2Th0 access macro = CPU TS_CLK CNTL FP_LNP S
x number of a%ments = 16 Ox003A008C Freq parameter loop number, loop type and R/W
- NP number Ox003A00C8 for end sequence slow default value = 25'h0 access macro = CPU_TS_CLK_CNTL_FP LTE_S_x number of elements = 16 Ox003A00CC Freq parameter NP number per loop nominal R/W

default value = 2Th0 access macro = CPU TS CLK CNTL FP LNP N
x Ox003A00D0 Freq parameter loop number, loop type and R/W
NP number for end sequence nominal default value = 25'h0 access macro = CPU TS CLK CNTL FP LTE N
x Ox003A00D4 Freq parameter NP number per loop fast R/W
-Ox003A010C default value = 2Th0 access macro = CPU_TS_CLK_CNTL FP LNP_F
x number of a%ments = 15 Ox003A0110 Freq parameter loop number, loop type and R/W
- NP number Ox003A0148 for end sequence fast default value = 25'h0 access macro = CPU TS CLK_CNTL_FP_LTE_F_x number of elements = 15 A Direct Digital Synthesiser (DDS) circuit, running off I DDS REF CLK, is used to generate the recovered clock. The recovered clock is available on the O DDS SYN CLK OUT pin, and would normally be used to drive the I DPLL MOD REF CLK and I DPLL DEMOD_REF CLK inputs.
By combining a sequence of nominal with either a short or long waveform, the DDS can generate any frequency that varies in steps.

The types of possible waveforms are:
I_DDS_REF_CLK
0_DOS ~ CLK_OUT
nominal pulx (NP) 0_DDS SYN_CLK OUT
short pulx (SP) O_DDS_SYN_CLK_OUT
long pulx (LP) For example, a sequence of 269999982 NP (nominal period) interspersed with 24 SP (short period) gives an average frequency of 2700000.6 Hz over a duration of 10 seconds.
The resulting waveform sequence looks like the following:
NP NP NP SP NP NP SP
The DDS block is implemented with a look up table for the programmable frequency values and a state machine to run the sequence based on a frequency error input value.
The lookup table entry for 1 frequency setting is as follows:
Number of repeatable Number of NP End of loop type End number of NP
sub loops in a sub loop NP, SP, or LP to complete 10 sec NP NP NP $P NP NP 5P NP
Sub loop 1 1 . $ub bop N ~, End r NP

In order to be useful, the ASIC must be controlled by a processor. The processors chosen are the Motorola 860 and Motorola 8260.
The SB7016 is able to act as either an ATM-layer or PHY-layer Utopia device, for applications that require an ATM data path.
The Internal Configuration bus (HCPU) is an internal configuration bus with which all internal registers can be programmed. It consists of two 8-bit buses (master-to-slaves, slaves-to-master) with some control signals. It multiplexes address and data to provide a 24-bit address space and 32-bit data length. The control signals from the master are AS (address strobe), DS (data strobe), and R WN
(read/write).
The control signal to the master is ACK.
The HCPU master resides within the Processor Interface. The HCPU slave is replicated a number of times throughout the ASIC. The number of instances shall be adjusted to achieve a trade-off between gate count and fanout of the HCPU
bus signals.
The HCPU slave shall consist of a common front end that runs of the processor clock (x60 clk), and a customised back end that safely crosses time domains and interfaces to the functional module. The back end shall be generated using a Perl script in every instance where it is required.
Note that any number of x60 clk cycles may occur between the address and data phases of a register access operation.
The command to the back end module shall be a 56-bit packet (24 address + 32 data) accompanied by read and write strobes. The back end module must resynchronise to the local clock domain and send back a 'done' signal to acknowledge the address and data values. The command from the back end module (only used for reads) shall be a 32-bit packet, accompanied by a 1-bit enable. This shall be synchronised to the x60 clk domain.
The output data from the slaves to the master may be merged into a single bus. To avoid having muxes at each merge point, the output data shall always be zero when 'ack' is low. This allows for a simple OR-ing of all input buses.
Similarly, the outputs of the customised back ends can be OR-d together to communicate with a single HCPU slave module.

In the event of an error (such as timeout), the HCPU master may terminate a register access by asserting AS and DS simultaneously.
The SB7016 interfaces with the Motorola 860 and 8260 processor local bus. The ASIC requires two chip select signals from the MPC860, one for register accesses, and one for data accesses.
The register address space is accessed with asynchronous hand shaking.
The data address space is accessed in zero wait-state mode.
For registers, the SB7016 presents a 24-bit wide {16 Mbyte) address space to the processor. All registers and memories are mapped within this address space.
Only 32-bit accesses are allowed (no 8- or 16-bit accesses). The SB7016 supports 64-bit accesses, but only to memory spaces in the data access space.
For data access, the device presents a 15-bit wide address space to the processor. High-speed data transfers are supported in the memory space.
For both the MPC860 and MPC8260, only 32-bit bus transactions are allowed to internal registers. The result of using Byte and Word transactions is undefined. For the MPC8260, a special 64-bit mode is supported to read or write data to the Input and Output Queuing modules.
By default, bus errors generated by reads or writes are masked. In the case of reads to invalid addresses, a zero value is returned. The device can be programmed to generate bus faults (TEA) by programming the TEA Enable register.
The MPC860 requires an external device to assert DREQ_N in order to perform DMA operations. The device provides two DREQ_N signals, which can be programmed as required. Note that DREQ_0 can not be used if UTOPIA access is required since the pin used for DREQ_0 is the same as that used for RxCAV.
The SB7016 occupies 24 bits of the PowerPC bus address space. The top 8 bits of the PowerPC bus (0:7) can be used to generate a chip select for this device.
Because all accesses are 32-bit aligned, bits 30:31 of the PowerPC bus are always zero.

The HCPU bus strips off the two LSBs and zero-pads the resulting 22-bit number to 24 bits. This is the address format used throughout the ASIC in the register decode logic.
In order to insert the modem into an appropriate location in the memory map of the processor, the Base (BRx) and Option (ORx) registers corresponding to the associated modem chip selects must be programmed as follows. Zero wait states (programmed using the ORx register) may be used with the GPCM given a maximum CLKOUT rate.
For the Register address space, 16 MB of 32-bit address space, burst inhibited, memory using the GPCM and TA generation must be mapped in. This can be accomplished with the following assembly code snippet (taken from the VxWorks RomInit.s file). Note that, in this example, CSS is used for the register access and is mapped in starting at address 0x5000000.
ne MODE1~LREGISTER_BASE.J1DDRE55 0x5000000 /* Chip select 5 has 16 MB of memory mapped in. */
lis r5, HI:ADJ( Oxff000000 I OR_BI I OR_SETA ) addi r5, r5, Lo(Oxff000000 I oR_BI I OR_SETA ) stw r5, oR5(0)(r4) lis r5. HIADJ((MODENLREGISTER_BASEJ~DDRESS & BR_BAJ~ISK) ~ BR_V) addi r5, r5, LO((hlODEHLREGISTER_BASEJaDDRE55 & BR_BAJdSK) I BR'V) stw r5, BR5(0)(r4) For the data address space, 32MB (the minimum allowable with the MPC860) of 32-bit address burst enabled memory, using one of the UPMs must be mapped in. Address multiplex is not required. This can be accomplished with the following assembly code snippet (taken from the VxWorks RomInit.s file). Note that, in this example, CS4 / UPMB is used for the for the data memory access and is mapped in starting at address 0x4000000.

ne /* Chip select 4 has 32K of memory mapped in. */
lis r5, HIAD7( Oxffff8000) addi r5, r5, Lo(Oxffff8000) stw r5, OR4(0)(r4) lis r5, HIA07( (MODEM_IO_QUEUE_BASE.J~DDRE55 & BR_Ba'MSK) ~ BRJ~IS_UPMB ~
BR_V) addi r5, r5, LO((MODEM_IO_QUEUE_BASEJ~DDRESS & BI~BI~MSK) ~ BR_MS_UPMB ~ BR_V) stw r5, BR4(0)(r4) Given that a UPM is used for data access, the MxMR register and the UPM
RAM array must be programmed appropriately.
No periodic refresh of the memory or address multiplexing is required, meaning that the MxMR register can be programmed with 0. A waveform must be programmed into the UPM array.
When inserting these memory blocks into the operating system memory map, ensure that they are marked as non-cacheable to prevent cache coherency problems from occurring.
All internal configuration registers reside in the address space activated by the I X60 CS REG N chip select pin. This address space is further subdivided into internal register space and internal memory space. The bits number is the table refer to the address bits on the MPC860 address bus. Since all accesses are 32-bit aligned, bits 30 and 31 are always zero.
The memories for the Input and Output Queuing, and the interrupt configuration registers, reside in the address space activated by the I X60 CS MEM N chip select pin. All accesses to this address space are 64-bit aligned. Therefore, bits 29 to 31 are always zero.

The operating system software must map each chip select into a virtual address space. This determines the most significant bits of the address used to access these registers.
The register addresses shown throughout the document are offsets into these virtual address spaces.
Table 51: Processor Interface Configuration Registers r p II nternal registers I

p general modem ______________________________________________ Input queuing configuration 2 ______________________________________________ frameformatter ________________________________________________ gambler -.

4 ______________________________________________ Modulatoroutercode ______________________________________________ CRC generator 6 ______________________________________________ interieaver 7 ______________________________________________ Modulator AIP

g convolutlonal encoder ________________________________________________ 9 pund:uring ______________________________________________ preambleinsert ________________________________________________ 11 mapper 12 ______________________________________________ RC fllter(mod) 3 ______________________________________________ miscellaneous mod 14 ______________________________________________ RC fliter(demod) refer carrier recovery to individual register maps 16 ______________________________________________ timing recovery 17 ______________________________________________ equalizer ______________________________________________ IQ generator ________________________________________________ 1g viterbi ________________________________________________ 2p sync detect:

21 ______________________________________________ pemodulator AIP

22 ______________________________________________ deinterleaver 23 ______________________________________________ pemodulatoroutercode 24 ______________________________________________ CRC verffler ______________________________________________ de~rambler 26 ______________________________________________ frame deformatter 27 output queuing configuration 28 ______________________________________________ addressfilter 2g dock recovery and generation ______________________________________________ miscellaneous demod 31 ______________________________________________ interpolator ________________________________________________ 32 fluff 33 ______________________________________________ dock dividers 34 ______________________________________________ pCR extractor ________________________________________________ Burst Demod 36 ______________________________________________ Modulator Frequency Hopper 37 ______________________________________________ modulator Frequency Hopper 38 ______________________________________________ guy mod Data Mux ________________________________________________ 1 Memory p Internal memory 0 address event map memory (11 (mod) bits) 1 address event map memory (11 (demod) bits) 2 address (10 bits) sequencer memory (mod) 3 address (10 bits) sequencer memory (demod) 1 External memory 0 address per-user configuration (16 bits) memory Table 52: Register Address Space Partitioning The modem ASIC occupies 24 bits of the PowerPC bus address space. The top 8 bits of the PowerPC bus (0:7) can be used to generate a chip select for this device. Because all accesses are 32-bit aligned, bits 30:31 of the PowerPC bus are always zero.

The HCPU bus strips off the two LSBs and zero-pads the resulting 22 bit number to 24 bits. This is the address format used throughout the ASIC in the register decode logic.
A special 64-bit access space will also be provided for the MPC8260 to do DMA.
In ut ueuin 0 0 0 0 Data LSB debu 31:0 0 0 1 0 Data MSB debu 63:32 Memory Address (8:0) 0 1 0 0 End Of Messagewyy debug 79:64 0 1 1 - ueue 0 Data to W
2:0 ueue 2'b00 1 0 0 - Queue 0 Length of (2:0) message, In b es 17:0 1 0 1 - 0 0 0 ueue size R debu 1 0 1 - 0 1 Queue 0 Read ointerR debu (2:0) 1 0 1 - 1 0 0 Wrlte olnterR debu 1 1 1 - 0 Reset ointersW debu Out ueuin gut 0 0 0 0 Data LSB R debu 31:0 Memory Address (8:0) 0 0 1 0 Data MSB R debu 63:32 0 1 1 - ueue 0 Data from R
ueue 2'b01 1 0 1 - ueue 0 Data ueue R debu size 1 1 0 0 - ueue 0 Read Pointerdebu 1 1 0 1 - ueue 0 Write Pointerdebu 1 1 1 - 0 Software W debu Reset Interru - 0 0 0 ID R aster R debu - 3'h0 0 Status LSB R

Interrupt 3'hl 0 Status MSb R
' 2 Number b10 3'h2 0 Mask LSB W

_ 2'b01 3'h3 0 Mask MSB W
or - 2'b10 3'h4 0 Condition R
LSB

- 3'h5 0 Condition R
MSB

Table 53: Data Address Space Partitioning The SB7016 occupies up to 2 PowerPC interrupt lines, depending on the desired system configuration. There are 64 error conditions that are trapped internally by the device. Any of these error conditions can be routed to either interrupt line, or masked off (ignored).
The two interrupt lines are nominally labelled "high" and "low". It is, however, a matter of system and software design that ultimately determines the interrupt priority.

The interrupt lines themselves are level sensitive, active-low, as per the MPC860SAR local-bus specification. The ID register returns a constant value of 32'hAA.AA AAAA.
The Status registers allow the instantaneous status of the 64 error conditions to be read by software. These can be used for polling.
The Mask registers allow the interrupt lines to operate on a particular error condition. By default, these registers have a value of zero, meaning no interrupts will be generated. One possible mode of configuration is to map all data-related conditions to the "low" interrupt, and everything else to the "high"
interrupt. This would be done by setting the corresponding bits in the appropriate Mask register.
When an interrupt occurs, the software Interrupt Service Routine (ISR) should read the appropriate Condition register to determine which events occurred to trigger the interrupt. The act of reading the Condition register will cause the interrupt condition to be cleared.
~,,~~!;i~~, 1q1~~~,~~~;~I~~
~ ~,~u~a ~'~ ~ ~"~~~ii~4 ~,;,a Modulator 57 AIP R Inter Access Timeout 56 Event Handler Pro rammable Interru t 55 Insert PCR Strobe Detected 54 Burst Data has left the chi 53 Burst Mode Timin Error FIFO Full 52 Burst Mode Timin Error FIFO Em 51 Parallel-to-Serial FIFO Overflow Demodulator 31 to 50 reserved 30 PCR Timestam Read 29 AIP R aster Access Tlmeout 28 Burst Demod Header FIFO Overtiow 27 DDS Timebase Fla 26 New f uen arameters re wired 25 Too man timestam s lost 24 Recovered timestam out of ran a 23 FIFO Overflow in Vfterbi Decoder Loo back RS Decoder or Serial-to-Parallel 22 Event Handler Pro rammable Interru t 21 Su erframe Strobe Generated b PCR

20 S nc Detect S nc lost 19 E Lock Lost 18 TR Lock Lost 17 CR Lock Lost CPU Interface 16 Frame Formatter caused FIFO Underflow 15 INT Invalid Address 14 I rea for new data burst 13 HCPU Bus Write Error 12 I Invalid Address ~,, 11 Out ~i i~ ~i I ~ ; I ~ i 1, ut ueue CPU Re nc FIFO Overflow Ou ueue ATM Re nc FIFO Overflow ut 9 Ou ueue 4 HI h Threshold Hit ut 8 Out ueue 3 Hi h Threshold Hit ut 7 Out ueue 2 HI h Threshold Hit ut 6 Out ueue 1 HI h Threshold Hit ut Cell Parl Error Detected 4 In ueue R nc FIFO Overflow ut 3 In ueue 4 Low Threshold Hit ut 2 In ueue 3 Low Threshold Hit ut 1 In ueue 2 Low Threshold Hit ut 0 In ueue 1 Low Threshold Hit ut Table 54: Interrupt Status Register Beginning with Rev A1, the SB7016 is able to act as either an ATM-layer or PHY-layer Utopia device. The receive and transmit ports are completely independent, and it is possible to have one as ATM-layer and the other as PHY-layer.
Rev AO was exclusively a PHY-layer device.
The device conforms to the Utopia Level I interface. [Refer to ATM
Forum AF-PHY-0017]. As an extension, the interface clock can operate as high as 50 MHz instead of 25 MHz.
With the use of a mode pin, the device can operate as MPC860SAR-compatible bi-directional pseudo-Utopia port. This feature is not supported when programmed for ATM-layer operation, since the MPC860SAR assumes the ATM-layer function.
As a PHY-layer device, the Utopia RX and TX clocks are provided to the digital ASIC by the ATM-layer. The ASIC must be able to accommodate any Utopia clock rate up to 50 MHz.

Table 55: Interrupt Registers As an ATM-layer device, an external source must provide the Utopia RX
and TX to both the digital ASIC and the PHY-layer device.
To facilitate debugging and self test, the device provides a number of loopback features.
The output of the Modulator can be fed directly to the input of the Demodulator. Functionality of both halves of the design can be verified by comparing the resulting output data with the input data. This test mode exercises the entire device.
The output of the Modulator Serial-to-Parallel block can be fed to the input of the Demodulator Sync Detect block. The output of the Modulator Puncturing block can be fed to the input of the Demodulator Depuncturing block. The resulting output data is passed to the Output Queue. This test mode can be used to ensure that all frame removal and FEC decoding is being performed correctly.
The byte-level output of the Modulator can be captured directly and passed to the Output Queue of the Demodulator. This test mode can be used to verify that all frame and FEC generation is being performed correctly.
External interfaces include Modulator Inputs & Outputs I EXT MOD BYTES
I EXT MOD SYMS
O MOD_~DATA
O MOD I DATA
O MOD DATA RDY
And Demodulator Inputs & Outputs I EXT DEMOD SYMS
I EXT DEMOD BYTES
I EXT DEMOD BITS

For testability, the device shall provide support for ATPG vectors. The device uses 8 scan chains. For scan test mode, assert I BIST_TM=0 and I JTAG _ _TMS=1. Use I JTAG TCK for the scan clock, and I JTAG_TRST for reset. Scan output comes out on O DBG DEMOD2(7:0) for the 8 scan chains.
RAMS are tested using BIST controllers. For BIST mode, assert I BIST TM=1 and I JTAG _TMS=0. In this case, I JTAG_TCK is the clock and I X60 RESET N is the reset. The BIST start command is issued by driving I EXT MOD BYTES(5)=1.
To see the results of the BIST, drive I EXT MOD BYTES(4:0) with the RAM
number (0--19); this will provide bist done on O DBG MOD2(1) and bist_gonogo on O DBG MOD2(0) for the RAM chosen. The tester must cycle through all 22 RAMS to verify bist-gognogo for all RAMS.
Three pins are provided for basic I/O testing purposes. The I IOTEST_TM
pin puts the device into I/O test mode when asserted high. In this mode, the I IOTEST TEN pin acts as a global tri-state control (1=tri-state). When I IOTEST TEN is set to 0, all outputs will drive whatever value is present on the I IOTEST TA input pin.

APPENDIX A
Physical And Mechanical Characteristics 1.1 PHYSICAL DESCRIPTION & PINOUT
Foundry is ST Microelectronics; process is HCMOS 7 (0.25 micron). Synthesised to WCIND (worst-case industrial) margins.
The SB7016 package is a 40 mm x 40 mm 432-pin SuperBGA, with 1.27 mm ball pitch.
PWR=IIO Power 3.3V
vdd=core power 2.5V
vdd_ana0=dac power vdd anal,2=adc power E4 0 DAC I_DATA R3 I_DEMOD_RSSI VAL_1 D2 0_DAC_COMPOUT_Q T1 I_DEMOD RSSI_VAL_0 Dl 0_DAC_COMPOUT_I T2 0 POWER_AMP_ON

E3 0_DAC_COMPOUT_E T3 0_PWMOUT_7 F4 I_DAC_COMPIN_Q T4 O PWMOUT_6 E2 I_DAC_COMPIN_I U1 O_PWMOUT 5 El I_DAC_COMPIN_E U2 O PWMOUT_4 F3 O DAC_ANA_E U3 O_PWMOUT_3 F2 0_TX_DAC_Q_DATA_7 V2 O PWMOUT_2 F1 O TX_DAC_Q_DATA_6 U4 O PWMOUT_1 G3 vdd V3 O PWMOUT_0 _ H4 O_TX_DAC_Q_DATA_5 W1 I_PWMCLK

G2 0_TX_DAC_Q_DATA_4 W2 0_BURST FREQUENCY_10 G1 O-TX DAC_Q_DATA W3 O BURST_FREQUENCY_9 H3 0_TX_DAC_Q_DATA_2 Y1 O BURST_FREQUENCY_8 J4 0_TX_DAC_Q_DATA_1 Y2 O BURST_FREQUENCY_2 H2 O_TX_DAC_Q_DATA W4 O BURST_FREQUENCY_1 H1 O MOD_SAMP CLK_OUT Y3 O BURST_FREQUENCY_0 J3 VDD ANAO AA1 vdd J2 VDD_ANA1 AA2 I_ADC_RC_Q_DATA_7 J1 VDD_ANA2 Y4 I_ADC_RC_Q_DATA_6 K3 I_PLLVDD AA3 I_ADC_RC_Q_DATA_5 L4 vdd AB1 I_ADC_RC_Q_DATA_4 K2 0_TX_DAC_I DATA_7 AB2 I_ADC_RC_Q_DATA_3 K1 0_TX_DAC_I DATA AA4 I_ADC_RC_Q_DATA_2 L3 0_TX_DAC_I DATA_5 AB3 I_ADC_RC_Q_DATA_1 M4 0_TX_DAC_I DATA_4 AC1 I_ADC_RC_Q_DATA_0 L2 0_TX_DAC_I DATA AC2 O DEMOD_SAMP CLK_OUT

L1 0_TX_DAC_I DATA_2 AC3 I ADC_RC_I_DATA_7 M3 O_TX_DAC_I_DATA AD1 I_ADC_RC_I_DATA

N4 O_TX_DAC_I DATA_0 AD2 I ADC_RC_I_DATA_5 M2 I_MOD_SAMP_CLK AC4 I_ADC_RC_I_DATA_4 Ml I_DEMOD_RSSI_VAL_7 AD3 I ADC_RC_I_DATA_3 N3 I_DEMOD_RSSI VAL_6 AEi I_ADC_RC_I_DATA_2 N2 vdd AE2 I ADC_RC_I_DATA

N1 I_DEMOD_RSSI_VAL_S AD4 I_ADC_RC_I_DATA_0 P3 I_DEMOD_RSSI_VAL_4 AE3 I DEMOD_SAMP_CLK

P2 I_DEMOD_RSSI_VAL_3 AFl I_ADC_Q_REF2 R4 I DEMOD_RSSI VAL_2 AF2 I_ADC_Q_REF1 AF3 I_ADC_Q_IREF AK20 0_DBG MOD2 2 AG1 I_ADC_Q_DATA_NEG AH19 O_DBG_MOD2 1 AG2 I_ADC_Q_DATA AJ20 O_DBG_MOD2_0 AF4 I_ADC_I_REF2 AL21 O_DBG_MOD_ENABLE

AG3 I ADC I REF1 AK21 O_DBG_DEMOD2_13 AH1 I_ADC_I_IREF AH20 0_DBG DEMOD2_12 AH2 I_ADC_I_DATA_NEG AJ21 O_DBG_DEMOD2_11 AG4 I ADC_I_DATA AL22 0_DBG DEMOD2_10 _ AH5 I_EXT_MOD_SYMS_3 AK22 O DBG DEMOD2 9 AK4 I_EXT_MOD_SYMS_2 AH21 O DBG_DEMOD2_8 AL4 I_EXT_MOD_SYMS_i AJ22 O DBG_DEMOD2_7 AJ5 I_EXT_MOD SYMS_0 AL23 O_DBG DEMOD2_6 AH6 vdd AK23 vdd AK5 I_EXT MOD_BYTES_9 AI23 O DBG DEMOD2 5 AL5 I_EXT_MOD_BYTES AL24 O DBG DEMOD2 4 8 _ AJ6 I_EXT_MOD_BYTES_7 AK24 O DBG DEMOD2 3 AK6 I_EXT_MOD BYTES_6 AH23 O DBG DEMOD2 2 AL6 I_EXT MOD_BYTES_5 AJ24 O DBG DEMOD2 1 AI7 I_EXT_MOD_BYTES_4 AL25 O DBG DEMOD2 0 AH8 I_EXT MOD_BYTES_3 AK25 O DBG DEMOD ENABLE

AK7 I_EXT_MOD_BYTES_2 AH24 I_X60_TS N

AL7 I_EXT_MOD_BYTES_1 AJ25 0 X60_TEA_N

AJ8 I_EXT MOD_BYTES_0 AL26 B_X60_TA_N

AH9 O EXT_FEATURE OUT_15 AK26 I_X60 RESET_N

AK8 O EXT_FEATURE OUT_14 AJ26 0 X60_INTB_N

AL8 O EXT_FEATURE_OUT_13 AL27 0_X60 INTA_N

AJ9 O EXT_FEATURE_OUT AK27 I_X60_CS_REG_N

AK9 O EXT_FEATURE OUT_11 AH26 I_X60_CS_MEM_N

AL9 O EXT_FEATURE OUT_10 AJ27 I_X60 BURST_N

AJ100 EXT FEATURE_OUT AL28 I_M860_BDIP_N

AH110_EXT_FEATURE_OUT_8 AK28 I_M8260_TT 4 AK100_EXT_FEATURE_OUT_7 AH27 I_M8260_TT_3 AL100_EXT_FEATURE_OUT_6 AG28 I_M8260_TT 2 AJ110_EXT_FEATURE_OUT_5 AH30 I_M8260_TT 1 AH120_EXT_FEATURE OUT_4 AH31 I_M8260_TT_0 AK110_EXT_FEATURE_OUT_3 AG29 I_M8260 PSDVAL_N

AL110_EXT_FEATURE OUT_2 AF28 vdd AJ120 EXT_FEATURE_OUT AG30 I_X60_CLK

AH130_EXT_FEATURE_OUT_0 AG31 I M860_R WN

AK12I_EXT_DEMOD_SYMS_3 AF29 0_M8260_GTA_N

AL12I_EXT DEMOD_SYMS_2 AF30 O DREQ1N

AJ13I_EXT_DEMOD_SYMS_1 AF31 O DREQON

AK13I_EXT_DEMOD_SYMS AE29 B_X60_DATA_63 AL13I_EXT_DEMOD_BYTES_9 AD28 B_X60_DATA_62 AJ14I_EXT_DEMOD_BYTES AE30 B_X60_DATA_61 AK14I_EXT DEMOD_BYTES_7 AE31 B X60_DATA_60 AH15I_EXT DEMOD_BYTES_6 AD29 B_X60_DATA_59 AJ15I_EXT_DEMOD_BYTES AC28 B_X60_DATA_58 AL16I_EXT_DEMOD_BYTES AD30 B_X60_DATA_57 AK16I_EXT_DEMOD_BYTES_3 AD31 B_X60 DATA_56 AJ16I_EXT DEMOD BYTES_2 AC29 vdd AH16I_EXT_DEMOD_BYTES AC30 B_X60_DATA_55 AL17I_EXT_DEMOD_BYTES AC31 B_X60_DATA_54 AK17I_EXT_DEMOD BITS_1 AB29 B_X60_DATA_53 A117I_EXT_DEMOD_BITS AA28 B_X60_DATA_52 AK18O DBG MOD2_9 AB30 B_X60_DATA_51 AH17O DBG MOD2_8 AB31 B_X60_DATA_50 A718O DBG MOD2 7 AA29 B_X60_DATA_49 AL19O DBG MOD2 6 Y28 B_X60_DATA_48 AKi9O DBG MOD2 5 AA30 B_X60_DATA_47 AJ19O DBG MOD2 4 AA31 B_X60_DATA_46 AL200 DBG MOD2 3 Y29 B_X60 DATA_45 W28 B_X60_DATA_44 A27 I_X60_ADD_13 Y30 B X60_DATA 43 C26 I_X60_ADD_12 Y31 B_X60_DATA_42 B26 I X60_ADD_11 _ W29 B_X60_DATA 41 A26 I_X60_ADD 10 W30 B_X60_DATA 40 C25 I_X60_ADD 9 W31 B_X60_DATA_39 D24 I_X60_ADD 8 V29 B_X60_DATA_38 B25 vdd V30 B_X60_DATA_37 A25 I_PROCESSOR TYPE
_ U28 B_X60_DATA_36 C24 I_TX_SOC

U29 B_X60_DATA_35 D23 I_TX_PRTY

T31 B_X60_DATA_34 B24 I_TX_ENB_N

T30 B X60_DATA_33 A24 I_TX_DATA 7 _ T29 B_X60 DATA_32 C23 I_TX_DATA_6 T28 vdd B23 I_TX_DATA 5 R31 B_X60_DATA_31 A23 I_TX DATA 4 _ R30 B X60_DATA 30 C22 I TX_DATA 3 _ R29 B_X60_DATA_29 D21 I_TX_DATA_2 P30 B X60_DATA 28 B22 I TX_DATA 1 _ _ R28 B X60_DATA 27 A22 I TX_DATA_0 P29 B X60_DATA_26 C21 0_TX CLAV

N31 B_X60_DATA_25 D20 I_TX_CLK

N30 B_X60_DATA 24 B21 O RX_SOC

N29 B X60_DATA_23 A21 0 RX_PRTY

M31 B_X60_DATA_22 C20 I_RX_ENB_N

M30 B_X60_DATA 21 D19 O RX_DATA_7 N28 B X60_DATA_20 B20 O RX_DATA_6 _ M29 B_X60_DATA_19 A20 O RX_DATA 5 _ L31 B_X60_DATA_18 C19 O RX_DATA_4 L30 B_X60_DATA_17 B19 O RX_DATA_3 M28 B_X60_DATA_16 A19 O RX_DATA_2 L29 B_X60_DATA_15 C18 O RX_DATA 1 _ K31 B X60_DATA_14 B18 O RX_DATA 0 _ K30 B_X60_DATA_13 D17 O RX_CLAV

L28 B_X60_DATA_12 C17 I_RX CLK

K29 B X60_DATA 11 A16 vdd J31 B_X60_DATA_10 B16 O DIV2NCLKOUT_3 J30 B_X60_DATA_9 C16 O DIV2NCLKOUT_2 _ J29 B_X60_DATA_8 016 O DIV2NCLKOUT_1 H31 B_X60_DATA_7 A15 O DIV2NCLKOUT_0 H30 B_X60_DATA_6 B15 I_DIV2NCLK_3 J28 B X60_DATA_5 C15 I_DIV2NCLK_2 H29 B X60_DATA_4 B14 I_DIV2NCLK_1 G31 B_X60_DATA 3 D15 I_DIV2NCLK_0 G30 B_X60_DATA_2 C14 I MOD_NCCD CLK

H28 B_X60_DATA_1 A13 0_MODEM E_CLK OUT

G29 B X60_DATA_0 B13 0_MOD SAMP NCLK_OUT

F31 I_X60_ADD_29 C13 O_MOD_BYTE_CLK OUT

F30 I X60_ADD_28 A12 O DEMOD_SAMP_NCLK_OUT

F29 I_X60_ADD_27 B12 O DEMOD_BYTE CLK_OUT

E31 I X60_ADD_26 D13 O DEMOD_BIT_NCLK_OUT

E30 I_X60_ADD_25 C12 O DEMOD BIT_CLK_OUT

F28 I X60_ADD_24 All O DDS_SYN CLK_OUT

E29 I_X60_ADD_23 Bll I_MOD_BYTE CLK

D31 I_X60_ADD_22 D12 I_DPLL_MOD_REF_CLK

D30 I_X60_ADD_21 Cil I_DPLL_DEMOD_REF
CLK

E28 I X60_ADD_20 A10 I_DEMOD_NCCD_CLK

D27 I_X60_ADD_19 B10 I_DEMOD_BYTE_CLK

B28 I X60_ADD_18 D11 I_DEMOD BIT_CLK

A28 I X60 ADD_17 C10 vdd C27 I_X60_ADD_16 A9 I_DDS_REF_CLK

D26 I X60_ADD_15 B9 O_MOD_~DATA 1 B27 I_X60_ADD 14 C9 0 MOD_~DATA_0 A8 0 MOD_I_DATA_1 AL15 GND

B8 0_MOD_I DATA_0 AL18 GND

D9 0_MOD_DATA_RDY AL29 GND

C8 I_BIST_TM AL30 GND

A7 I_JTAG_TRST A1 PWR

B7 I_JTAG_TMS A31 PWR

D8 I_JTAG TCK B2 PWR

C7 I_IOTEST_TM B30 PWR

A6 I_IOTEST TEN C3 PWR

86 I_IOTEST_TA C29 PWR

C6 I_INSERT_PCR D4 PWR

A5 O_DEMOD_SF_STRB_OUT D7 PWR

B5 I_MOD_SF STRB_IN D10 PWR

D6 IO_DAC_COMP D14 PWR

C5 I_DAC_VREF D18 PWR

A4 I_DAC_RSEIII D22 PWR

B4 O DAC_RSETI D25 PWR

D5 O_DAC_~DATA D28 PWR

Bl GND V28 PWR

Rl GND AK2 PWR

U30 GND ALl PWR

All GND

Al2 GND

Al4 GND

AKl GND

~

1.2 POWER CONSUMPTION
TBD
1.3 ON-CHIP MEMORY
The SB7016 contains the following on-chip SRAMs.
Note: SPS RAMS are synchronous single-port. DPR RAMS are synchronous dual-port.
1.4 ANALOG COMPONENTS
The following analog components are used:
~ PLL
~ DAC
~ ADC

APPENDIX B
Electrical Characteristics 1.5 DC CHARACTERISTICS
Ta",b = 25 °C
;; ~, ~~, '~~ ~, i~~li '!~ I ~I l9il i i~'i'' i ' TBD
VDD,~ LOW level core volts 0 ',~I, V
a ~

VDDt" HIGH level core volts TBD 2.5 V
a PWR,~ LOW level I 0 volts 0 TBD V
a PWR", HIGH level I O volts TBD 3.3 V
a I PLLVDD PLL su I volts a V

VDD ANAO DAC su I volts a V

VDD ANAL I ADC su I volts a V

VDD ANA2 ADC su volts a V

I uiescent su I current - TBD

I o ratin current for - TBD mA
I 0 ds I o ratin current for - TBD mA
core 1.6 AC CHARACTERISTICS
i j, ,~ ' ~ i ~~ '''I ~ ~
~ i~~ 'III,II ns I MOD SAMP CLK Modulator Sam i ~ i ~
lin dock ~ ~li. ili -I MOD BYTE CLK Modulator B 30 - ns a clock SAMP CLK ~~k dulator 4 - ns I Sampling DEMOD

-_ I DEMOD BIT Demodulator 5 - ns CLK Bit clock I DEMOD BYTE Demodulator 30 - ns CLK B a clock I DDS REF CLK External Reference 9 - ns clock I X60 CLK Processor clock 10 - ns I TX CLK Modulator Uto 20 - ns is clock I RX CLK Demodulator 20 - ns Uto is clock Pulse Width 10 -Modulator I PWMCLK ns - clock B BURST FRE Fractional-N 2.5 - ns UENCY 2 Counter clods B BURST FRE Fractional-N 2.5 - ns UENCY 10 Counter clods I_DIV2NCLK_0 I_DIV2NCLK 1 Divide-by- 4 - ns Z " clocks I_DIV2NCLK_2 I MOD NCCD CLK Programmable Godc 5 - ns I DEMOD NCCD Divider Inputs CLK

I DPLL MOD REF
CLK

pLL Input Gock 5 - ns I DPLL DEMOD
REF CLK

rise time - TBD ns fall time - TBD ns all clocks HIGH time 40 60 ~ %

I3~

~y, I I , C in ut ca acitance ~i I F
- TBD

in ut rise time - TBD ns in ut fall time - TBD ns in ut setu time 3 - ns I_X60_ADD_*

in ut hold time 1 - ns in ut setu time 3 - ns B_X60_DATA_* in ut hold time 1 - ns ou ut time TBD TBD ns I X60_CS_MEM
N, I_X60_CS_REG_N, n 3 - s input setup time TS
N
I

, _ _ _ I_X60_BURST_N, I M860_BDIP input hold timen 1 - s N, I_M860_R_WN, 0 X60 TEA out ut time TBD TBD ns N

0 X60_INTA output time BD TBD ns N, T

N

O_DREQON, output time TBD TBD ns I M8260 PSDVAL_N, I M8260_TT_0, input setup 2 - ns time I_M8260_TT_l, I_M8260_TT_2, input hold time 1 - ns fe n , i I 1 i r ~ , i III I I~ ~i~ ,~ 0 I
I ii I I ~ " I I,,TBD F
C I f i ~iii~~~, II II~, in ut ca chance I~~~~~.,il,r ~~
II
~
II
'' ~I
I, ~~~
-in ut rise time - TBD ns in ut fall time - TBD ns I_TX_DATA_7 I TX_DATA_6 I_TX_DATA_5 input setup time TBD - ns I_TX_DATA_4 I_TX_DATA_3 I_TX_DATA_2 I_TX_DATA_1 I_TX_DATA_0 input hold time TBD - ns I_TX_PRTY

I TX SOC

in ut setu time TBD - ns TX
ENB
N
B

_ in ut hold time TBD - ns _ _ TX
CLAV
B

_ ou ut time TBD TBD ns _ I ~~~i ~ ~I~Ip~l~l~~llRll'Id ~" ~~ L~Vi~l'~~~1~1~
l~~i~l~~ ~~~Il~~~li~i~ ~ i~i~Lu O RX DATA ,t u~~~ l~Iy49~~~1~~ ~i~~~~ail~,e~~i~'ll~~~"~, 7 (~!~i ~~ i~~,~n i~i~~ ~ ~~~~~il~il I
~~ ~~~

O RX DATA

O RX DATA

O RX DATA

_ output time BD TBD ns T

O RX DATA

O RX DATA

O_RX_DATA_0 O_RX_PRTY

in ut seta time TBD - ns B
RX
ENB
N

_ in ut hold time TBD - ns _ _ B RX CLAV

ou ut time TBD TBD ns ~ I 1,~'5'5~I'~ ~ ~ ~ d ~i~ idrr~1g rl 41 l li, I V4~ '' ~ V
a l i d ~I I ~~I i~~ n ~fr~~ii ~" ~~~iyy P
>~~1 O TX DAC I w DATA 7 ~ ~~~I V~ I ~~~I
. ~kildl O TX DAC I
DATA_6 0_~ DAC_I_DATAoutput time 2 3 ns O TX DAC I

O TX DAC I

O TX DAC I

0 TX DAC_I
DATA_1 0 TX_DAC_I_DATArise time - TBD ns 0_TX_DAC_Q_DATA_7 ~ DAC

Q
DATA

_ _ _ _ 0_~ DAC_Q_DATA_5 0_~ DAC_Q_DATA

O_~ DAC_Q_DATA_3fall time - TBD ns 0_~ DAC_Q_DATA

0_~ DAC_Q_DATA_1 O TX DAC DATA

O POWER AMP out ut time TBD TBD ns ON

O MOD DATA
RDY

0 MOD I DATA_0 0_MOD_I_DATA_ioutput time TBD TBD ns 0_MOD_Q_DATA_0 0_BURST FREQUENCY_0 0_BURST_FREQUENCY_1output time, TBD TBD ns DDS mode O BURST FREQUENCY

output time, BD TBD ns 0 BURST FRE Fractional-N

I_ADC_RC_I_DATA_7 I_ADC_RC_I_DATA_6 I ADC RC I DATA

I ADC input setup RC time I DATA

_ -_ 2 ns _ I_ADC_RC_I_DATA_3 I_ADC_RC_I_DATA_2 I_ADC_RC_I_DATA_1 I ADC RC_I_DATA

I ADC_RC_~DATA_7 I_ADC_RC_~DATA_6 I_ADC_RC_~DATA input hold time 2 - ns I ADC_RC_~DATA

I_ADC_RC_~DATA

I_ADC_RC_~DATA_2 ADC
I
RC

_ _ _~

I ADC_RC_(ZDATA_0 I_DEMOD_RSSI_VAL_7 I_DEMOD_RSSI_VAL_6 I_DEMOD_RSSI_VAL_5 I_DEMOD_RSSI_VAL_4dse time - TBD ns I_DEMOD_RSSI_VAL_3 I_DEMOD_RSSI_VAL_2 I_DEMOD_RSSI_VAL_1 I DEMOD RSSI

APPENDIX C
Compatibility 1.7 AIR INTERFACE
At a minimum, the modem aims to be compatible with the following communications systems (both uplink and downlink):
~ DOCSIS 1.1 ~ SES-Astra 1.8 BUS INTERFACES
The SB7016 Modem provides " seamless" interfaces with the following hardware standards.
~ Utopia Level I
~ PowerPC local bus, 32-bit and 64-bit APPENDIX D
Comprehensive list of registers Re ister Ma f for c 0x00000004 Modulator Reset n R/W

default value = 1'b0 access macro = CFG MOD RESET N x 0x00000008 Modulator Clock Divider Reset n R/W

default value = 1'b0 access macro = CFG MOD CLKGEN RESET N x Ox0000000C Demodulator Reset n R/W

default value = 1'b0 access macro = CFG DEMOD RESET N x 0x00000010 Demodulator Clock Divider Reset n R/W

default value = 1'b0 access macro = CFG DEMOD CLKGEN RESET N
x 0x00000014 TEA Enable R/W

default value = 1'b0 access macro = CFG TEA EN x 0x00000018 SB7016 Version R/E

default value = 32 bits access macro = CFG VERSION x Ox0000001C DRE~N R/W

default value = 2'bil access macro = CFG DRE N x 0x00000020 mod_samp_clk R/W

default value = 29'h10101 access macro = CFG MOD SAMP x 0x00000024 mod_samp_clk lock R/E

default value = 1 bits access macro = CFG MOD SAMP LOCK x 0x00000028 demod_samp_clk R/W

default value = 29'h10101 access macro = CFG DEMOD SAMP x Ox0000002C demod_samp clk lock R/E

default value = 1 bits access macro = CFG DEMOD SAMP LOCK x 0x00000030 demod_bit clk R/W

default value = 29'h10101 access macro = CFG DEMOD BIT x 0x00000034 demod_bit clk lock R/E

default value = 1 bits access macro = CFG DEMOD BIT LOCK x 0x00000038 modem_e_clk R/W

default value = 29'h10101 access macro = CFG MODEM E x Re inter Ma for fluff , I ~ ~ ~ ~,,P" I ' ~ IIII
~' I I li ~'~~ I~ ~!Il~
i ~~

i 0x00400004 , R/W
- ~
i PWM On Times 0x00400020 default value = 32'd0 ' access macro = FLUFF ON_TIME_x number of elements = 8 0x00400024 PWM Off Times R/W
-0x00400040 default value = 32'd0 access macro = FLUFF_OFF_TIME_x number of elements = 8 0x00400044 Divide-by-2~N counters R/W

default value = 16'h0 access macro = FLUFF DIV2N x 0x00400048 DAC Test R/W

default value = 8'h0 access macro = FLUFF DAC TEST x Ox0040004C 7040 Contra) R/W

default value = 8'h0 access macro = FLUFF 7040 CONTROL x 0x00400050 7041 Control R/W

default value = 8'h0 access macro = FLUFF 7041 CONTROL x 0x00400054 Digital Output Enable_n R/W

default value = 8'h0 access macro = FLUFF DIG OE N x creation date: Sat Feb 19 06:17: 56 2000 creation date: Sat Feb 19 06:17: 44 2000 creation date: Sat Feb 19 06.17:45 2000 R inter Ma od for m ' ' I 'III I I I, I
Ox001A0004 Modulator Enable R/W

default value = 1'b0 access macro = MOD ENABLE x Ox001A0008 Bypass Register R/W

default value = 8'b11111111 access macro = MOD BYPASS x Ox001A000C Modulation Selection R/W

default value = 2'b00 access macro = MOD MODULATION SEL x Ox001A0010 Frame Count Limit R/W

default value = 32'h0 access macro = MOD COUNT LIMIT x Ox001A0014 Burst Mode R/W

default value = 1'b0 access macro = MOD BURST MODE x Ox001A0018 Pipeline Delay R/W

default value = 16'd256 access macro = MOD PIPELINE DELAY x Ox001A001C Event Counter Readback R/E

default value = 32 bits access macro = MOD EVENT COUNTER x Ox001A0020 Power Amp On R/W

default value = 3'd2 access macro = MOD PWRAMP ON x Ox001A0024 Power Amp Off R/W

default value = 5'd23 access macro = MOD PWRAMP OFF x Ox001A0028 Generator Polynomial G1 R/W

default value = To133 access macro = MOD G1 x Ox001A002C Generator Polynomial G2 R/W

default value = To171 access macro = MOD G2 x Ox001A0030 QAM-i6 Pattern R/W

default value = 1'bi access macro = MOD AM16 PATTERN x Ox001A0034 PS Flush Bits R/W

default value = 3'h0 access macro = MOD PS FLUSH BITS x Ox001A0038 PS Invert Bits R/W

default value = 1'b0 access macro = MOD PS INVERT BITS x Ox001A003C Ranging Offset R/W

default value = 10'd512 access macro = MOD RANGING OFFSET x Ox001A0040 mod byte_clk to dds_syn clk relationship R/W

default value = 2'b00 access macro = MOD BYTE CLK SPEED x Ox001A0044 External Processing R/W

default value = 2'b00 access macro = MOD USE EXTERNAL x Ox001A0048 DAC Configuration R/W

default value = 8'b11000000 access macro = MOD DAC CFG x Ox001A004C Debug mux_sel R/W

default value = 6'b111 001 access macro = MOD MUX SEL x Ox001A0050 DDS Hop Delay R/W

default value = 16'd256 access macro = MOD DDS HOP DELAY x creation date. Sat Feb 19 06:17: 59 2000 Re ister Ma od ai for m I, ~ I II I
~I

Ox000E0004 Event Handler Registers R/W/E
-Ox000E0020 default value = 16 bits access macro = MOD AIP_RW_REG_x number of a%ments = 8 Ox000E0024 Event Handler Read-Only Registers R/E
-Ox000E0040 default value = 16 bits access macro = MOD AIP_RO_REG_x number of a%mentr = 8 Ox000E0044 Event Handler Flags R/W/E

default value = 4 bits access macro = MOD AIP EV FLAGS x Ox000E0048 Event Handler PC R/W/E

default value = 10 bits access macro = MOD AIP EV PC x Ox000E004C uSequencer Next Address R/E

default value = 10 bits access macro = MOD AIP USE NA x Ox000E0050 Fork LUT R/W
-Ox000E005C default value = 32'h0 access macro = MOD AIP_FORK_LUT_x number of elements = 4 Ox000E0060 R7 bit select R/W

default value = 12'h0 access macro = MOD AIP R7 BIT SEL x Ox000E0064 Counter Threshold R/W

default value = 10'h0 access macro = MOD AIP THRESHOLD x Ox000E0068 a uencer Counter Autodecrement creation date: Sat Feb 19 06:17: 59 2000 ster Map for 0x00800000 - Mod Event Handler Memory R/W
Ox00800FFC access macro = MOD EV_x number of elements = 1024 I
creation date: Sat Feb 19 06.18: 08 2000 ster Map for 0x00840000 - Mod Sequencer Memory R/W
Ox00840FFC access macro = MOD_SEQ_x number of elements = 1024 creation date: Sat Feb 19 06:18: 09 2000 Re ister Ma for i I II ~ I~~ I
I III ~~ III~I~~
II I I ~
VII II~~
I ~I~III II I
I III
~~ I
~ I I
~II
II~

I , II I I
I I I I
I I I R/W
i I I
~I Queue End Pointer II, I
~' 0x00020004 -0x00020020 default value = 9'h0 access macro = IQ_END_POINTER x number of elements = 8 0x00020024 Minimum Queue Size R/W
-0x00020030 default value = 9'h0 access macro = IQ_MIN_QUEUE SIZE_x number of elements = 4 0x00020034 Queue Start Pointer - R/W

0x00020050 default value = 9'h0 access macro = IQ_START POINTER
x number of a%ments = 8 0x00020054 ATM HEC Insert R/W

default value = 1'bi access macro = I HEC INSERT x 0x00020058 Utopia Parity Check R/W

default value = 1'b0 access macro = I PARITY CHECK x Ox0002005C In ut ueuin uto is enable W

Re inter Ma for ff ~i I I I
i I ' I i 0x00040004 Control Word R/W
-0x00040040 default value = 64'h0 access macro = FF_CW_x number of elements = 16 0x00040084 Control Word Size R/W
-Ox000400C0 default value = Td0 access macro = FF_CW_SIZE_x number of a%menLs = 16 Ox000400C4 AIP Register Size R/W
-Ox000400E0 default value = 5'd8 access macro = FF_AIP_REG_SIZE_x number of a%ments = 8 Ox000400E4 PCR Offset Size R/W

default value = Td42 access macro = FF PCR OFF SIZE
x Ox000400E8 PCR Count Size R/W

default value = Td42 access macro = FF PCR CNT SIZE
x creation date: Sat Feb 19 06:17: SS 2000 Re ister crambler Ma for i i I, s '~~I
~~~i~l~ II
I I ;~
ii ~
II ~' II
~ ~ III I ~IIi ~ I
~ ,~
I,I
I

, , I,I R/W/S
~ ,;
I ~
I , I~I! , 0x00060004 ~
;
, , Scrambler Seed default value = 16'b1111111111111111 access macro = SCRAMBLER SEED x 0x00060008 Scrambler Polynomial R/W

default value = 16'b0000111000000011 access macro = SCRAMBLER POLYNOMIAL
x Ox0006000C Scrambler Mode R/W

default value = 1'b0 access macro = SCRAMBLER MODE x 0x00060010 Scrambler 1 Control R/W

default value = T b 1111_100 access macro = SCRAMBLER SCRI CONTROL
x 0x00060014 Scrambler 2 Control R/W

default value = Tb1111_100 access macro = SCRAMBLER SCR2 CONTROL
x creation date: Sat Feb 19 06:18: OS 2000 creation date: Sat Feb 19 06:17: 58 2000 Resister Map for crcgen Ox000A0004 Data Mask WW
-Ox000A0080 default value = 8'h0 access macro = CRCGEN_DATA MASK x number of elements = 32 Ox000A0084 CRC Mask R/W
-Ox000A0100 default value = 32'h0 access macro = CRCGEN_CRC_MASK x number of elements = 32 Ox000A0104 CRC Byte Count R/W

default value = 3'h4 access macro = CRCGEN CRC BYTE COUNT
x Ox000A0108 Data Byte Count WW

default value = T h8 access macro = CRCGEN DATA BYTE COUNT
x creation date: Sat Feb 19 06:17: 48 2000 ister Map for creation date. Sat Feb 19 06:18: Ol 2000 creation date: Sat Feb 19 06:17: 57 2000 i I
0x00120004 Puncturing Rate Select R/W

default value = 3'b000 access macro = PUNC RATE SEL_x 0x00120008 Rate 2/3 Puncture Pattern R/W

default value = 16'b0010001000000000 access macro = PUNC R23 x Ox0012000C Rate 3/4 Puncture Pattern R/W

default value = 16'b0010010000000000 access macro = PUNC R34 x 0x00120010 Rate 5/6 Puncture Pattern WW

default value = 16'b0010011001000000 amess macro = PUNC R56 x 0x00120014 Rate 7/8 Puncture Pattern R/W

default value = 16'b0010101001100100 access macro = PUNC R78 x creation date: Sat Feb 19 06:18: 03 2000 Re inter Ma reamble insert for i I

, 0x00140004 Preamble Data R/W
-0x00140010 default value = 128'h0 access macro = PREAMBLE_INSERT PREAMBLE_DATA
x number of a%ments = 4 0x00140044 Preamble Length R/W
-0x00140050 default value = 8'h0 access macro = PREAMBLE INSERT_PREAMBLE
LENGTH x number of a%ments = 4 0x00140054 Flush Data R/W

default value = 128'h0 access macro = PREAMBLE INSERT FLUSH DATA
x 0x00140064 Flush Length R/W

default value = 8'h0 access macro = PREAMBLE INSERT FLUSH LENGTH
x 0x00140068 Ignore Trigger R/W

default value = 1'b1 access macro = PREAMBLE INSERT IGNORE TRIGGER
x Ox0014006C Preamble Repeat R/W

default value = 6'h0 access macro = PREAMBLE INSERT PREAMBLE
REPEAT x 0x00140070 Flush Repeat R/W

default value = 6'h0 access macro = PREAMBLE INSERT FLUSH REPEAT
x creation date: Sat Feb 19 06:18: 03 2000 I.
0x00180010 default value = 6'b000_000 access macro = MOD_IQMAP_QPSK_PATTERN x number of elements = 4 0x00180014 16-QAM Pattern WW
-0x00180050 default value = 6'b000 000 access macro = MOD_IQMAP_QAM PATTERN x number of elements = 16 0x00180054 tap coefficients WW
-Ox0018007C default value = 12'h0 access macro = MOD IQMAP_COEF_x number of a%ments = 11 0x00180080 DAC Values Unsigned R/W

default value = 1'b0 access macro = MOD I MAP DAC UNSIGNED x creation date: Sat Feb 19 06:18: 01 2000 Re ister emod Ma for d Ox003C0004 Demodulator Enable R/W

default value = 1'b0 access macro = DEMOD ENABLE x Ox003C0008 Bypass Register R/W

default value = 16'hFFFF

access macro = DEMOD BYPASS x Ox003C000C Demodulation Selection R/W

default value = 2'b00 access macro = DEMOD DEMODULATION
SEL x Ox003C0010 Algorithm Select R/W

default value = 2'b10 access macro = DEMOD ALG SEL x Ox003C0014 Data Source R/W

default value = 9'b111 000001 access macro = DEMOD DATA SOURCE x Ox003C0018 Event Counter Readback R/E

' default value = 32 bits creation date: Sat Feb 19 06:18: 00 2000 i access macro = DEMOD EVENT COUNTER x Ox003C001C SP Invert Bits WW

default value = 1'b0 access macro = DEMOD SP INVERT BITS x Ox003C0020 External Processing WW

default value = T b0 access macro = DEMOD USE EXTERNAL x Ox003C0024 RSSI R/E

default value = 8 bits access macro = DEMOD RSSI x Ox003C0028 Debug mux_sel WW

default value = 3'b000 access macro = DEMOD MUX SEL_x Ox003C002C Frame Count Limit R/W

default value = 32'h0 access macro = DEMOD COUNT LIMIT x Ox003C0030 Pipeline Delay R/W

default value = 16'd256 access macro = DEMOD PIPELINE DELAY x Ox003C0034 AIP Processor Delay R/W

default value = 16'd32 access macro = DEMOD AIP PROC DELAY x Ox003C0038 Ranging Offset R/W

default value = 10'di access macro = DEMOD RANGING OFFSET x Ox003C003C ADC Control R/W

default value = 12' b0 access macro = DEMOD ADC CONTROL x creation date: Sat Feb 19 06:17: 50 2000 Re ister emod ai Ma for d ~i ~ ~~~ ~y ~ i i ~ ~
~~
Uui~
~

Ox002A0004 Event , - Handler R/W/E
Registers Ox002A0020 default value =

bits access macro =
DEMOD_AIP
RW
REG
x number of a%ments =

Ox002A0024 Event R/E
- Handler Read-Only Registers Ox002A0040 default value =

bits access macro =
DEMOD_AIP_RO_REG
x number of a%ments =

Ox002A0044 Event R/W/E
Handler Flags default value =

bits access macro =
DEMOD
AIP
EV
FLAGS
x Ox002A0048 Event R/W/E
Handler PC

default value =

bits access macro =
DEMOD
AIP
EV
PC
x Ox002A004C uSe E
uencer Next Address default value = 10 bits access macro = DEMOD AIP USE NA x Ox002A0050 Pork LUT R/W
-Ox002A005C default value = 32'h0 access macro = DEMOD_AIP_FORK LUT x number of elements = 4 Ox002A0060 R7 bit select R/W

default value = 12'h0 access macro = DEMOD AIP R7 BIT_SEL x Ox002A0064 Counter Threshold WW

default value = 10'h0 access macro = DEMOD AIP THRESHOLD x Ox002A0068 uSequencer Counter Autodecrement R/W

default value = 1'b0 access macro = DEMOD_AIP USE AUTODECR_x Ox002A006C uSequencer Busy R/E

default value = 1 bits access macro = DEMOD AIP USE BUSY x Ox002A0070 Register Access Acknowledge Timeout R/W

default value = 10' b0001000000 access macro = DEMOD AIP REG TIMEOUT x creation date: Sat Feb 19 06:17: Sl 2000 Map for 0x00820000 - Demod .Event Handler Memory R/W
Ox00820FFC access macro = DEMOD_EV_x number of elements = 1024 creation date: Sat Feb 19 06:18: 07 2000 Register Map for demod_seq 0x00860000 - Demod Sequencer Memory R/W
Ox00860FFC access macro = DEMOD_SE~x number of elements = 1024 creation date: Sat Feb 19 06:18: 07 2000 Resister Map for rc I
Ox001C0010 tap coefFcients< 12,O,t R/W

default value = 12'b000000010110 access macro = RC COEF 3 x Ox001C0014 tap coefficients<12,O,t WW

default value = 12'b000000000110 access macro = RC COEF 4 x Ox001C0018 tap coefficients<12,O,t WW

default value = 12'b111111100001 access macro = RC COEF 5 x Ox001C001C tap coefficients<12,O,t WW

default value = 12'b000001010111 access macro = RC COEF 6 x Ox001C0020 tap coefficients< 12,O,t R/W

default value = 12'b111101100110 access macro = RC COEF 7 x Ox001C0024 tap coefficients<12,O,t WW

default value = 12'b111100100111 access macro = RC COEF 8 x Ox001C0028 tap coefficients<12,O,t R/W

default value = 12'b010010100001 access macro = RC COEF 9 x Ox001C002C tap coefficients<12,O,t WW

default value = 12'b011111111111 access macro = RC COEF 10 x Ox001C0030 ADC Values Unsigned R/W

default value = 1'b0 access macro = RC ADC UNSIGNED x Ox001C0034 clock_multiplication R/W

default value = 6'bi access macro = RC CLOCK MUL x creation date: Sat Feb 19 06:18:

Re ister Ma for inter I I I
olator I
VIII
I Illi Ox003E0004 l R/W
- Interpolator Taps Ox003E0010 default value = 128'h0 access macro = INTERPOLATOR_LUT VALS_x number of elements = 4 Ox003E0044 ai R/W

default value = 8'b00001100 access macro = INTERPOLATOR A1 x Ox003E0048 a3= a1+a2 R/W

default value = 8'b00011001 access macro = INTERPOLATOR A3 x Ox003E004C Loop Gain WW

default value = 4'b0010 access macro = INTERPOLATOR LOOP GAIN
x Ox003E0050 Lock Count WW

default value = 16'b0000000111110100 access macro = INTERPOLATOR_LOCK_COUNT_x Ox003E0054 block size WW

default value = 16'b0000010000000000 access macro = INTERPOLATOR BLOCK
SIZE x Ox003E0058 mean scale WW

default value = 10'b0001001100 access macro = INTERPOLATOR_MEAN SCALE
x Ox003E005C beta WW

default value = 8'b01111110 access macro = INTERPOLATOR BETA x Ox003E0060 beta comp WW

default value = 8'b00000010 access macro = INTERPOLATOR BETA_COMP
x Ox003E0064 loop filter value WE

default value = 12 bits access macro = INTERPOLATOR_LOOP_F_OUT
x Ox003E0068 Lock Flag WE

default value = 1 bits access macro = INTERPOLATOR LOCK FLAG
x Ox003E006C Flag Count R/E

default value = 16 bits access macro = INTERPOLATOR FLAG COUNT
x Ox003E0070 Clear Accumulator R/W

default value = 1'b0 access macro = INTERPOLATOR CLEAR
ACC x creation date: Sat Feb 19 06:17: 57 2000 Re inter a Ma for i 0x00220004 Load Configuration R/W

default value = 1'b0 access macro = E~LOADrx~

0x00220008 FFE weights (I) R/W
-0x00220024 default value = 12'h0 access macro = EQ CI x number of a%ments = 8 0x00220028 FFE weights (Q) R/W
-0x00220044 default value = 12'h0 access macro = E~C~x number of elements = 8 0x00220048 Mu R/W

default value = 12' b000000000001 access macro = E MU x Ox0022004C R2 ~ R/W
' default value = 12' b000010000000 access macro = E R2 x 0x00220050 Current FFE weights Iteadback (I) R/E
-Ox0022006C default value = 12 bits access macro = E~CI_CURRENT x number of elements = 8 0x00220070 Current FFE weights Readback (Q) R/E
-Ox0022008C default value = 12 bits access macro = E~C~CURRENT x number of a%ments = 8 0x00220090 lock det beta WW

default value = 10'b0111111110 access macro = E BETA x 0x00220094 lock det i-beta R/W

default value = 10'b0000000010 access macro = E BETA COMP x 0x00220098 Lock Count WW

default value = 16'b0000000111110100 access macro = E LOCK COUNT x Ox0022009C block size R/W

default value = 16'b0000010000000000 access macro = E BLOCK SIZE x Ox002200A0 treshold_1 WW

default value = 12'b0000000100 access macro = E MEAN COMP VALUE x Ox002200A4 Lock Flag WE

default value = 1 bits access macro = E LOCK FLAG x Ox002200A8 Flag Count WE

default value = 16 bits access macro = E FLAG COUNT x Ox002200AC Clear lock average WW

default value = 1'b0 access macro = E CLEAR ACC x Ox002200B0 select dd mode R/W

default value = 1'b0 access macro = E DD MODE x Ox002200B4 tap update enable R/W

default value = 1'b0 access macro = E UPDATE ENABLE x Ox002200B8 scale_cma R/W

default value = 12'b000001000000 access macro = E SCALE CMA x Ox002200BC scale dd R/W

default value = 12'b000100000000 access macro = E SCALE DD x creation date: Sat Feb 19 06:17: SS 2000 R inter Ma for cr ~, ~ I ~I
II
I I I II
~I I
I I i Ox001E0004 I WW
I
~
Loop A1 default value = 8'b01001100 access macro = CR LOOP A1 x Ox001E0008 Loop A3=ai+a2 WW

default value = 8'b00000110 access macro = CR LOOP A3 x Ox001E000C Loop Gain WW

default value = 4'b0000 access macro = CR LOOP GAIN x Ox001E0010 Reset WW

default value = 1'bi access macro = CR RESET x Ox001E0014 down sampling(symbol) rate 1 2 3 or 4 R/W

default value = 2'b0 access macro = CR DOWN SYMBOL FACTOR x Ox001E0018 max transition for phase interpolator R/W

default value = 16'b0001100100000000 access macro = CR PHASE MAX TRANSITION x Ox001E001C Lock Count value for in lock R/W

default value = 16'b0000001010111100 access macro = CR LOCK COUNT x Ox001E0020 mean scale WW

default value = 10'b0001100110 access macro = CR MEAN SCALE x Ox001E0024 Step Size WW

default value = 12'b000000100000 access macro = CR STEP SIZE x Ox001E0028 lock det block size R/W

default value = 16'b0000010000000000 access macro = CR BLOCK SIZE x Ox001E002C Sweep Max Value R/W

default value = 12'b11111111111 access macro = CR SWEEP MAX VALUE x Ox001E0030 Sweep Min Value R/W

default value = 12'b000000000000 access macro = CR SWEEP MIN VALUE x Ox001E0034 Symbol Max Value R/W

default value = 16'b001000000000000 access macro = CR SYMBOL MAX VALUE x Ox001E0038 lock det beta R/W

default value = 8'b01111110 access macro = CR BETA x Ox001E003C lock det beta R/W

default value = 8'b00000010 access macro = CR BETA COMP x i Ox001E0040 Flag Count R/E

default value = 16 bits access macro = CR FLAG COUNT_x Ox001E0044 Carrier Lock WE

default value = 1 bits access macro = CR LOCK x Ox001E0048 loopf_out R/E

default value = 12 bits access macro = CR LOOPF OUT x Ox001E004C sweep_value WE

default value = 12 bits access macro = CR SWEEP VALUE x creation date: Sat Feb 19 06:17: 47 2000 Register Map for bdmux Ox004C0004 Header Flags ~ WW
default value = 5'b00000 access macro =
creation date. Sat Feb 19 06:17: 43 2000 Resister Map for demod_iQ9en 0x00240004 QPSK Pattern R/W
-0x00240010 default value = 2'b00 access macro = DEMOD IQGEN_QPSK PATTERN x number of a%ments = 4 0x00240014 16-QAM Pattern WW
-0x00240050 default value = 4'b0000 access macro = DEMOD IQGEN_QAM PATTERN x number of a%ments = 16 0x00240054 Phase Ambiguity WW

default value = 2'b00 access macro = DEMOD I GEN PH AMB x creation date: Sat Feb 19 06:17:

default value = 3'b000 access macro = VITDEC RATE SEl_ x 0x00260014 Rate 2/3 Puncture Pattern WW

default value = 16'b0010001000000000 access macro = VITUEC R23 x 0x00260018 Rate 3/4 Puncture Pattern WW

default value = 16'b0010010000000000 access macro = VITDEC R34 x Ox0026001C Rate 5/6 Puncture Pattern WW

default value = 16'b0010011001000000 access macro = VITDEC R56 x 0x00260020 Rate 7/8 Puncture Pattern WW

default value = 16'b0010101001100100 access macro = VITDEC R78 x 0x00260024 Puncture Pattern Skip W/P

default value = 1'b0 access macro = VITDEC PATTERN SKIP x 0x00260028 Symbols Processed R/E/S

default value = 32 bits access macro = VITDEC SYMS PROCESSED x Ox0026002C Errors Detected R/E/S

default value = 32 bits access macro = VITDEC ERRS DETECTED x 0x00260030 Soft Reset W/P

default value = 1'b0 access macro = VITDEC RESET x creation date: Sat Feb 19 06: I8: 06 2000 Resister Mau for sd 0x00280004 Frame Marker WW

default value = 64'h0 access macro = SD FRAME MARKER x Ox0028000C Frame Marker Mask R/W

default value = 64'h0 access macro = SD FRAME MARKER MASK_x 0x00280014 Superframe Marker R/W

default value = 64'h0 access macro = SD SUPERFRAME MARKER x Ox0028001C Superframe Marker Mask R/W

default value = 64'h0 access macro = SD SUPERFRAME MARKER MASK
x 0x00280024 Missed Sync Limit R/W

default value = 8'h0 access macro = SD MISSED SYNC LIMIT x 0x00280028 Num Match R/W

i default value = 8'h0 i i access macro = SD NUM MATCH x Ox0028002C Frame Size R/W

default value = 16'h0 access macro = SD FRAME SIZE x 0x00280030 Sync Pattern WW

default value = 32'h0 access macro = SD SYNC PATTERN x 0x00280034 Sync Pattern Length WW

default value = 5'h0 access macro = SD SYNC_PATTERN LENGTH x 0x00280038 Sync Lock RIE

default value = 1 bits access macro = SD SYNC LOCK x Ox0028003C Sync Lost R/E/S

default value = 1 bits access macro = SD SYNC LOST x 0x00280040 Number of Syncs Detected R/E/S

default value = 32 bits access macro = SD NUM SYNCS x 0x00280044 Watermark R/E/S

default value = 32 bits access macro = SD WATERMARK_x creation date: Sat Feb 19 06:18: OS 2000 inter Mau for 0x00340004 - Control Word WW
0x00340040 default value = 8'b00000000 access macro = DEMOD_FDF_CW_DATA x number of a%ments = 16 0x00340044 - Control Word Mask R/W
0x00340080 default value = 8'b00000000 access macro = DEMOD_FDF_CW_MASK x number of elements = 16 creation date: Sat Feb 19 06.~ 17: 50 2000 creation date: Sat Feb 19 06:17: 52 2000 R ister Ma for ctemoa outer cone Ox002E0004 Outer Code 0 WW

default value = 18'h3_00_00 access macro = DEMOD OUTER CODE OUTER CODESEL_0 x Ox002E0008 Outer Code 1 R/W

default value = 18'h2 cc_10 access macro = DEMOD OUTER CODE OUTER CODESEL
1 x Ox002E000C Outer Code 2 default value = 18'h2_44 08 access macro = DEMOD OUTER CODE OUTER CODESEL_2 x Ox002E0010 Outer Code 3 WW

default value = 18'h2_3f Oa access macro = DEMOD OUTER CODE OUTER CODESEL
3 x Ox002E0014 Bytes Processed R/E/S

default value = 32 bits access macro = DEMOD OUTER CODE BYTE COUNT
x Ox002E0018 CRC Errors R/E/S

default value = 32 bits access macro = DEMOD OUTER CODE CRC ERR COUNT
x Ox002E001C fZS Decoder Errors R/E/S

default value = 32 bits access macro = DEMOD~OUTER CODE RSDEC ERR
COUNT x Ox002E0020 RS Decoder Invalid Frames R/E/S

default value = 16 bits access macro =

DEMOD OUTER CODE RSDEC INVALID FRAMES x Ox002E0024 RS Decoder Burst Hack WW

default value = 1'b0 access macro = DEMOD OUTER CODE RSDEC_BURST
HACK x creation date: Sat Feb 19 06:17: 54 2000 Resister Man for crcv 0x00300004 Data Mask WW
-0x00300080 default value = 8'h0 access macro = CRCV DATA MASK x number of a%ments = 32 0x00300084 CRC Mask R/W
-0x00300100 default value = 32'h0 access macro = CRCV_CRC MASK x number of elements = 32 0x00300104 CRC Byte Count WW

default value = 3' h4 access macro = CRCV CRC BYTE COUNT
x 0x00300108 Data Byte Count R/W

default value = T h8 access macro = CRCV DATA BYTE COUNT
x creation date: Sat Feb 19 06:17:49 2000 Re ister Ma for descramn~er I ~, ~~ ~I

, Descrambler Seed R/WIS
0x00320004 default value = 16'b1111111111111111 access macro = DESCRAM BLER_SEED x 0x00320008 Descrambler Polynomial WW

default value = 16'b0000111000000011 access macro = DESCRAMBLER POLYNOMIAL
x Ox0032000C Descrambler Mode WW

default value = 1'b0 access macro = DESCRAMBLER MODE x 0x00320010 Descrambler 1 Control WW

default value = Tb1111_100 access macro = DESCRAMBLER_DES1 CONTROL
x 0x00320014 Descrambler 2 Control ' WW

default value = Tb1111_100 access macro = DESCRAMBLER DES2 CONTROL
x creation date: Sat Feb 19 06:17: 54 2000 Resister Map for adrfilt 0x00380004 Address Data WW
-0x00380080 default value = 32'h0 access macro = ADRFILT ADDR_x number of elements = 32 0x00380084 Address Mask WW
-0x00380100 default value = 32'h0 access macro = ADRFILT_MASK x number of elements = 32 0x00380104 Filter Defined WW

default value =

32'b0000_0000 0000_0000 0000_0000 0000_0001 access macro = ADRFILT FILTER DEFINED
x 0x00380108 Pass If Match WW

default value =

32'b0000__0000_0000_0000_0000_0000_0000 access macro = ADRFILT PASS IF MATCH
x creation date: Sat Feb 19 06:17: 42 2000 for 0x00880000 - Timestamp Extractor Memory WW
Ox008800FC access macro = TSX_MEM x number of elements = 64 creation date: Sat Feb 19 06:18: 09 2000 Re inter Ma a is ciK cnt~
for c ~i~ ~I~I~ ~~ ~ I ~ o ~ i~ ~~ ~
~I ~
I I J
' ~ I

I I WE
Ox003A0004 ~
cpu access ID reg default value = 16 bits access macro = CPU TS CLK CNTL BLKID x Ox003A0008 clock recovery and generation control R/W

default value = 11'h0 access macro = CPU TS CLK CNTL_CONTROL
x Ox003A000C clock recovery and generation status R/E

default value = 8 bits access macro = CPU TS CLK CNTL_STATUS
x Ox003A0010 timestamp loss threshold WW

default value = 8'h0 access macro = CPU TS CLK CNTL TS LOSS
THRSHLD x Ox003A0014 timestamp delta max WW

default value = 32'h0 access macro = CPU TS CLK CNTL TS DELTA_MAX
x Ox003A0018 window timebase terminal count R/W

default value = 32'h0 access macro = CPU TS CLK_CNTL WTB TC
x Ox003A001C timestamp load Isb WW

default value = 32'h0 access macro = CPU TS CLK_CNTL SWTS FIELD
LSB x Ox003A0020 timestamp load msb WW

default value = 10'h0 access macro = CPU TS CLK_CNTL SWTS FIELD
MSB x Ox003A0024 timestam inc load Isb R/W

creation date: Sat Feb 19 06:17: 46 2000 li ' ' default value = 8'h0 access macro = CPU TS CLK CNTL SWTS INC
FIELD x Ox003A0028 SES timestamp spacer field WW

default value = 6'h0 access macro = CPU TS CLK_CNTL_SWTS SES
FIELD x Ox003A002C superframe timestamp Isb WW

default value = 32'h0 access macro = CPU TS CLK CNTL SF TS LSB
x Ox003A0030 superframe timestamp msb WW

default value = 10'h0 access macro = CPU TS CLK CNTL_SF TS_MSB_x Ox003A0034 superframe generator terminal count WW

default value = 32'h0 access macro = CPU TS CLK CNTL SF TC CNT
x Ox003A0038 superframe strobe length value WW

default value = 8'h0 access macro = CPU TS CLK_CNTL SF STRB LEN
x Ox003A003C timestamp data Isb WE

default value = 32 bits access macro = CPU_TS CLK_CNTL TSD FIELD
LSB x Ox003A0040 timestamp data msb WE

default value = 10 bits access macro = CPU TS CLK_CNTL TSD FIELD
MSB x Ox003A0044 timestamp count Isb WE

default value = 32 bits access macro = CPU TS CLK CNTL TSC FIELD
LSB x Ox003A0048 timestamp count msb WE

default value = 10 bits access macro = CPU_TS CLK CNTL_TSC FIELD
MSB x Ox003A004C Freq parameter NP number per loop slow R/W
-Ox003A0088 default value = 27'h0 access macro = CPU_TS_CLK_CNTL FP_LNP_S
x number of elements = 16 Ox003A008C Freq parameter loop number, loop type and R/W
- NP number Ox003A00C8 for end sequence slow default value = 25'h0 access macro = CPU TS_CLK CNTL_FP_LTE S_x number of elements = 16 Ox003A00CC Freq parameter NP number per loop nominal R/W

default value = 2Th0 access macro = CPU TS CLK CNTL_FP LNP N
x Ox003A00D0 Freq parameter loop number, loop type and R/W
NP number for end sequence nominal default value = 25'h0 access macro = CPU TS CLK CNTL FP LTE N
x Ox003A00D4 Freq parameter NP number per loop fast R/W
-Ox003A010C default value = 2Th0 access macro = CPU TS_CLK CNTL_FP LNP_F_x number of a%ments = 15 Ox003A0110 - Freq parameter loop number, loop type and NP number R/W
Ox003A0148 for end sequence fast default value = 25'h0 access macro = CPU_TS_CLK CNTL FP LTE_F x number of a%ments = 15 creation date: Sat Feb 19 06:17: 45 2000 R ister Ma for o I I I ~I ~~~ I
~ I ~
I

i 0x00360004 Queue End Pointer WW
-0x00360010 default value = 9'h0 access macro = OQ_END_POINTER x number of a%ments = 4 0x00360014 Maximum Queue Size WW
-0x00360020 default value = 9'h0 access macro = OQ_MAX_QUEUE_SIZE_x number of a%ments = 4 0x00360024 Queue Start Pointer WW
-0x00360030 default value = 9'h0 access macro = OQ_START POINTER_x number of elements = 4 0x00360034 ATM alpha R/W

default value = 4'h0 access macro = 0 ALPHA x 0x00360038 ATM delta WW

default value = 4'h0 access macro = O DELTA x Ox0036003C ATM cell discard_n R/W

default value = 4'billl access macro = O CELL DISCARD N x 0x00360040 ATM HEC check enable WW

default value = 1'b0 access macro = 0 HEC CHECK EN x 0x00360044 ATM cell delineation enable WW

default value = 1'b0 access macro = 0 CELL DELINEATION EN x 0x00360048 ATM HEC error count R/E/S

default value = 8 bits access macro = O HEC_ERROR COUNT x Ox0036004C ATM Queue Enable WW

default value = 1'b1 access macro = O ATM UEUE EN x 0x00360050 ATM Discard Header R/W
-Ox0036005C default value = 40'h0 access macro = OQ_HEADER x number of a%ments = 4 0x00360070 OQ ATM Master mode enable WW
default value = 1'b0 macro =
creation date: Sat Feb 19 06:18: 02 2000 creation date: Sat Feb 19 06:17.52 2000 APPENDIX E
References [1] Modem Architectural System Design, Internal SNC document, A.Mascioli, ASD-005-0002 0.3, April 19, 1999 [2] Modem Hardware System Description, Internal SNC document, A.Mascioli, HSD-005-0001_1.1, May 11, 1999 APPENDIX F
Glossary ADC Analog-to-Digital Converter AGC Automatic Gain Control AIP Air Interface Processor ALU Arithmetic Logic Unit ASR Arithmetic bit Shift Right ATM Asynchronous Transfer Mode BFRP Burst Frequency Receive Plan BFTP Burst Frequency Transmit Plan BGA Ball Grid Array CDMA Code Division Multiple Access CLP Cell Loss Priority (ATM) CPE Customer Premise Equipment (Terminal) CR Carrier Recovery CRC Cyclic Redundancy Code DAC Digital-to-Analog Converter DAVIC Digital Audio-Visual Council DDS Direct Digital Synthesizer DOCSIS Data Over Cable Service Interface Specification DSP Digital Signal Processing DVB Digital Video Broadcasting EQ Equalizer FDMA Frequency Division Multiple Access FEC Forward Error Correction FFE Feed-Forward Equalizer FIFO First-In First-Out Queue FIR Finite Impulse Response filter HEC Header Error Control (ATM) I In-phase component IIR Infinite Impulse Response filter ISR Interrupt Service Routine (software) LMDS Local Multipoint Distribution Service LSB Least-Significant Bit LSL Logical Shift bits Left LSR Logical Shift bits Right LUT Look-Up Table MAC Media Access Control (software) MAC Multiply and Accumulate (hardware) MF-TDMA Multi-Frequency Time Division Multiple Access MPEG Motion Picture Experts' Group MSB Most-Significant Bit NCO Numerically controlled oscillator PCR Program Count Reference PID Program Identifier (MPEG) PLL Phase Locked Loop PN Pseudo Noise sequence PTI Payload Type Indicator (ATM) PWM Pulse Width Modulator Q Quadrature phase component QPSK Quadrature Phase Shift Keying QAM Quadrature Amplitude Modulation RC Raised Cosine Filter RF Radio Frequency ROR Rotate bits Right RS Reed-Solomon RX Receive SAR Segmentation and Reassembly (ATM) SATCOM Satellite Communications TDMA Time Division Multiple Access TR Timing Recovery TX Transmit VCI Virtual Circuit Identifier (ATM) VPI Virtual Path Identifier (ATM) APPENDIX G
Table 1: FORK LUT Indices Table 2: Modulator Command Set for Frame Formatter Table 3: Frame Deformatter table Table 4: PLL Control Register Format Table 5: PLL Control Register Map Table 6: NCCD Control Register Format Table 7: NCCD Clock Dividers Register Map Table 8: Divide-by-2N Register Format Table 9: Divide-by-2N Register Map Table 10: DAC Control Register Format Table 11: DAC Register Map Table 12: Feature Pins Register Map Table 13: PWM Register Map Table 14: Frequency Hopping Register Map Table 15: Processing Delays for Modulator Functional Blocks Table 16: Input Queuing Memory Map Table 17: Frame Formatter Command Codes Table 18: Frame Formatter Register Map Table 19: Scrambler Control Register Format Table 20: Scrambler Register Map Table 21: Modulator Outer Code Select Register Format Table 22: Modulator Outer Code Select Register Map Table 23: CRC Generator Register Map Table 24: Interleaver Register Map Table 25: Parallel-to-Serial Register Map Table 26: Convolutional Encoder Register Map Table 27: Puncturing Module Register Map Table 28: Preamble Insert Register Map Table 29: Mapper Register Map Table 30: Modulator RC Filter Register Map Table 31: Power Amp Register Map Table 32: Demodulator RC Filter Register Map Table 33: Interpolator Register Map Table 34: Carner Recovery Register Map Table 35: IQ Generator Register Map Table 36: Viterbi Decoder Register Map Table 37: Sync Pattern Encoding Scheme Table 38: Sync Detect Register Map Table 39: Serial-to-Parallel Register Map Table 40: Deinterleaver Register Map Table 41: Frame Deformatter Command Codes Table 42: Frame Deformatter Register Map Table 43: Demodulator Outer Code Select Register Format Table 44: Outer Code Decoder Register Map Table 45: CRC Verifier Register Map Table 46: Decrambler Control Register Format Table 47: Descrambler Register Map Table 48: Address Filter Register Map Table 49: Output Queuing Memory Map Table 50: Output Queuing Register Map Table S 1: Processor Interface Configuration Registers Table 52: Register Address Space Partitioning Table 53: Data Address Space Partitioning Table 54: Interrupt Status Register Table 55: Interrupt Registers

Claims

We claim:

1. A broadband wireless modem comprising:
an air interface for configuring data for transmission;
a modulator for modulating data;
a demodulator for demodulating data.