CA2283560A1 - Translated memory protection apparatus for an advanced microprocessor - Google Patents

Translated memory protection apparatus for an advanced microprocessor Download PDF

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Publication number
CA2283560A1
CA2283560A1 CA002283560A CA2283560A CA2283560A1 CA 2283560 A1 CA2283560 A1 CA 2283560A1 CA 002283560 A CA002283560 A CA 002283560A CA 2283560 A CA2283560 A CA 2283560A CA 2283560 A1 CA2283560 A1 CA 2283560A1
Authority
CA
Canada
Prior art keywords
memory address
protection apparatus
memory protection
translated
advanced microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002283560A
Other languages
French (fr)
Other versions
CA2283560C (en
Inventor
Edmund J. Kelly
Robert F. Cmelik
Malcolm J. Wing
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intellectual Ventures Holding 81 LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2283560A1 publication Critical patent/CA2283560A1/en
Application granted granted Critical
Publication of CA2283560C publication Critical patent/CA2283560C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Executing Machine-Instructions (AREA)
  • Storage Device Security (AREA)

Abstract

A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.
CA002283560A 1997-08-11 1997-08-11 Translated memory protection apparatus for an advanced microprocessor Expired - Fee Related CA2283560C (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1997/014117 WO1999008191A1 (en) 1997-08-11 1997-08-11 Translated memory protection apparatus for an advanced microprocessor

Publications (2)

Publication Number Publication Date
CA2283560A1 true CA2283560A1 (en) 1999-02-18
CA2283560C CA2283560C (en) 2003-12-09

Family

ID=22261430

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002283560A Expired - Fee Related CA2283560C (en) 1997-08-11 1997-08-11 Translated memory protection apparatus for an advanced microprocessor

Country Status (5)

Country Link
EP (1) EP1004075A4 (en)
JP (1) JP3621116B2 (en)
KR (1) KR100421687B1 (en)
CA (1) CA2283560C (en)
WO (1) WO1999008191A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6954923B1 (en) 1999-01-28 2005-10-11 Ati International Srl Recording classification of instructions executed by a computer
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US7254806B1 (en) 1999-08-30 2007-08-07 Ati International Srl Detecting reordered side-effects
US6751583B1 (en) 1999-10-29 2004-06-15 Vast Systems Technology Corporation Hardware and software co-simulation including simulating a target processor using binary translation
US7363620B2 (en) 2003-09-25 2008-04-22 Sun Microsystems, Inc. Non-linear execution of application program instructions for application program obfuscation
US7424620B2 (en) 2003-09-25 2008-09-09 Sun Microsystems, Inc. Interleaved data and instruction streams for application program obfuscation
US8220058B2 (en) 2003-09-25 2012-07-10 Oracle America, Inc. Rendering and encryption engine for application program obfuscation
US7353499B2 (en) 2003-09-25 2008-04-01 Sun Microsystems, Inc. Multiple instruction dispatch tables for application program obfuscation
US7415618B2 (en) 2003-09-25 2008-08-19 Sun Microsystems, Inc. Permutation of opcode values for application program obfuscation
JP6103541B2 (en) 2014-03-18 2017-03-29 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Apparatus and method for controlling execution of binary code
US10754790B2 (en) 2018-04-26 2020-08-25 Qualcomm Incorporated Translation of virtual addresses to physical addresses using translation lookaside buffer information

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4914577A (en) * 1987-07-16 1990-04-03 Icon International, Inc. Dynamic memory management system and method
US4825412A (en) * 1988-04-01 1989-04-25 Digital Equipment Corporation Lockout registers
GB2239724B (en) * 1990-01-05 1993-11-24 Sun Microsystems Inc Apparatus for maintaining consistency in a multi-processor computer system using virtual caching
US5282274A (en) * 1990-05-24 1994-01-25 International Business Machines Corporation Translation of multiple virtual pages upon a TLB miss
US5437017A (en) * 1992-10-09 1995-07-25 International Business Machines Corporation Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system
US5577231A (en) * 1994-12-06 1996-11-19 International Business Machines Corporation Storage access authorization controls in a computer system using dynamic translation of large addresses

Also Published As

Publication number Publication date
WO1999008191A1 (en) 1999-02-18
EP1004075A4 (en) 2001-01-17
KR100421687B1 (en) 2004-03-10
CA2283560C (en) 2003-12-09
JP2001519955A (en) 2001-10-23
EP1004075A1 (en) 2000-05-31
KR20010014096A (en) 2001-02-26
JP3621116B2 (en) 2005-02-16

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