CA2234493A1 - State machine architecture with multiplexed random access memory - Google Patents
State machine architecture with multiplexed random access memory Download PDFInfo
- Publication number
- CA2234493A1 CA2234493A1 CA 2234493 CA2234493A CA2234493A1 CA 2234493 A1 CA2234493 A1 CA 2234493A1 CA 2234493 CA2234493 CA 2234493 CA 2234493 A CA2234493 A CA 2234493A CA 2234493 A1 CA2234493 A1 CA 2234493A1
- Authority
- CA
- Canada
- Prior art keywords
- memory
- pipeline
- controller
- output
- null
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000013598 vector Substances 0.000 abstract 7
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Abstract
A plurality of time-division multiplexed data streams which are merged into a single data stream containing a plurality of data words and which are characterized by state vectors, are concurrently processed.
The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof. A null cycle generator coupled to the pipeline and to the controller inserts null cycles into the concurrently processed data streams at regular time intervals and outputs a NULL signal to the controller during each null cycle. A multiplexer coupled between the controller and the memory multiplexes access to the memory between the controller/pipeline, and an alternate controller.
Read access to the memory by the controller or pipeline is inhibited while the NULL signal is output, and write access to the memory by the pipeline is inhibited while an OUTGOING NULL replica of the NULL
signal is being output by the pipeline during the final clock cycle.
Accordingly, the alternate controller may gain read access to the memory while the NULL signal is output, and may gain write access to the memory while the OUTGOING NULL signal is output.
The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof. A null cycle generator coupled to the pipeline and to the controller inserts null cycles into the concurrently processed data streams at regular time intervals and outputs a NULL signal to the controller during each null cycle. A multiplexer coupled between the controller and the memory multiplexes access to the memory between the controller/pipeline, and an alternate controller.
Read access to the memory by the controller or pipeline is inhibited while the NULL signal is output, and write access to the memory by the pipeline is inhibited while an OUTGOING NULL replica of the NULL
signal is being output by the pipeline during the final clock cycle.
Accordingly, the alternate controller may gain read access to the memory while the NULL signal is output, and may gain write access to the memory while the OUTGOING NULL signal is output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2234493 CA2234493C (en) | 1998-04-09 | 1998-04-09 | State machine architecture with multiplexed random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2234493 CA2234493C (en) | 1998-04-09 | 1998-04-09 | State machine architecture with multiplexed random access memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2234493A1 true CA2234493A1 (en) | 1999-10-09 |
| CA2234493C CA2234493C (en) | 2002-12-31 |
Family
ID=4162317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2234493 Expired - Fee Related CA2234493C (en) | 1998-04-09 | 1998-04-09 | State machine architecture with multiplexed random access memory |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2234493C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1376404A3 (en) * | 2002-06-28 | 2008-02-06 | Microsoft Corporation | Method and system for managing backup files |
| US7818532B2 (en) | 2002-06-28 | 2010-10-19 | Microsoft Corporation | Method and system for creating and restoring an image file |
| CN108345534A (en) * | 2017-01-24 | 2018-07-31 | Arm 有限公司 | The device and method for generating and handling tracking stream |
-
1998
- 1998-04-09 CA CA 2234493 patent/CA2234493C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1376404A3 (en) * | 2002-06-28 | 2008-02-06 | Microsoft Corporation | Method and system for managing backup files |
| US7818532B2 (en) | 2002-06-28 | 2010-10-19 | Microsoft Corporation | Method and system for creating and restoring an image file |
| US7877567B2 (en) | 2002-06-28 | 2011-01-25 | Microsoft Corporation | Transporting image files |
| CN108345534A (en) * | 2017-01-24 | 2018-07-31 | Arm 有限公司 | The device and method for generating and handling tracking stream |
| CN108345534B (en) * | 2017-01-24 | 2023-03-03 | Arm 有限公司 | Apparatus and method for generating and processing trace stream |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2234493C (en) | 2002-12-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20140409 |