CA2230162A1 - Phase locked loop circuit - Google Patents
Phase locked loop circuitInfo
- Publication number
- CA2230162A1 CA2230162A1 CA 2230162 CA2230162A CA2230162A1 CA 2230162 A1 CA2230162 A1 CA 2230162A1 CA 2230162 CA2230162 CA 2230162 CA 2230162 A CA2230162 A CA 2230162A CA 2230162 A1 CA2230162 A1 CA 2230162A1
- Authority
- CA
- Canada
- Prior art keywords
- arithmetic processing
- temperature information
- signal
- frequency
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A phase locked loop circuit includes a phase comparator, a temperature information output section, an arithmetic processing circuit, and a voltage controlled oscillator. The phase comparator compares the phase of an input signal with that of a frequency division signal obtained by frequency-dividing an output frequency signal. The frequency division signal has the same frequency as that of the input signal. The temperature information output section outputs temperature information based on an ambient temperature. The arithmetic processing circuit performs arithmetic processing by using the temperature information from the temperature information output section and an output from the phase comparator, and outputs the arithmetic processing result as a voltage control signal.
The voltage controlled oscillator outputs an output frequency signal in accordance with the voltage control signal from the arithmetic processing section.
The voltage controlled oscillator outputs an output frequency signal in accordance with the voltage control signal from the arithmetic processing section.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9124070A JPH10322198A (en) | 1997-05-14 | 1997-05-14 | Phase-locked loop circuit |
JP124070/'97 | 1997-05-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2230162A1 true CA2230162A1 (en) | 1998-11-14 |
CA2230162C CA2230162C (en) | 2000-11-28 |
Family
ID=14876205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA 2230162 Expired - Fee Related CA2230162C (en) | 1997-05-14 | 1998-02-23 | Phase locked loop circuit |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH10322198A (en) |
CA (1) | CA2230162C (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003308133A (en) * | 2002-02-18 | 2003-10-31 | Matsushita Electric Ind Co Ltd | Multi-phase clock transmission circuit and method |
KR100861966B1 (en) | 2007-02-02 | 2008-10-07 | 엘아이지넥스원 주식회사 | Apparatus for stability of yig osc in pll |
US7583152B2 (en) * | 2008-01-04 | 2009-09-01 | Qualcomm Incorporated | Phase-locked loop with self-correcting phase-to-digital transfer function |
JP5424473B2 (en) * | 2009-08-31 | 2014-02-26 | 京セラクリスタルデバイス株式会社 | Oscillator circuit |
EP2711800B1 (en) * | 2012-09-24 | 2019-11-20 | Telefonaktiebolaget LM Ericsson (publ) | I/O cell calibration |
JP6534200B2 (en) * | 2015-02-17 | 2019-06-26 | 古野電気株式会社 | Reference signal generator |
JP2016220157A (en) * | 2015-05-26 | 2016-12-22 | セイコーエプソン株式会社 | Standard signal generating device |
-
1997
- 1997-05-14 JP JP9124070A patent/JPH10322198A/en active Pending
-
1998
- 1998-02-23 CA CA 2230162 patent/CA2230162C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH10322198A (en) | 1998-12-04 |
CA2230162C (en) | 2000-11-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |