CA2229756A1 - Method and apparatus for correcting element mismatch in digital-to-analog converters - Google Patents
Method and apparatus for correcting element mismatch in digital-to-analog converters Download PDFInfo
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- CA2229756A1 CA2229756A1 CA 2229756 CA2229756A CA2229756A1 CA 2229756 A1 CA2229756 A1 CA 2229756A1 CA 2229756 CA2229756 CA 2229756 CA 2229756 A CA2229756 A CA 2229756A CA 2229756 A1 CA2229756 A1 CA 2229756A1
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- dac
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
- H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
- H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
- H03M1/0665—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using data dependent selection of the elements, e.g. data weighted averaging
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/464—Details of the digital/analogue conversion in the feedback path
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A method and apparatus for correcting element mismatch in digital-to-analog converters includes the application of a data-weighted averaging algorithm for use with signals that are not lowpass. The method allows the signal band of interest to be situated anywhere in the frequency domain. Multiple pointers are used, and the number of pointers determines the frequency at which the element mismatch cancellation occurs.
Description
METHOD AND APPARATUS FOR CORRECTING ELEMENT MISMATCH
IN DIGITAL-TO-ANALOG CONVERTERS
FIELD OF INVENTION
The present invention relates to a method and apparatus for correcting element mismatch in digital-to-analog converters.
BACKGROUND OF THE INVENTION
Digital-to-Analog Converters (DACs) can be used in any interface between a digital system and the physical world, as seen in Figure 1. The more bits the DAC can convert, the more resolution it has, with the result of a better quality analog signal output (e. g. better sound for a CD or DAT, better video for a TV signal, and the like). DACs have numerous applications in the telecommunications industry. The present invention addresses, although is not limited to, a particular application of a DAC in a telecommunication application.
The present invention addresses the simplest of DAC
implementations. To those versed in the art, the simplest DAC
implementation consists of converting a digital word to a numerical value, then summing that number of analog unit values, producing a net analog signal integrally related to the numerical value. For example, if one wanted to convert the binary number '011' to analog form, it would be evaluated as the number '3'. The DAC would select three elements from the unit array, and sum them to give the desired output, as in Figure 2.
As indicated above, the DAC sums a number of analog units together to produce a desired output value. Thus, the accuracy of the conversion is directly related to accuracy of the analog units summed, and the summing process. Numerically 1+1=2. However, physical units, of physical quantities, do not exhibit numerical accuracy. For example: when baking, one cup of water and one cup of water equals two cups of water. This may be true theoretically; however, if you were to count the number of water molecules an individual transfers, a large discrepancy would always be found. First, each individual cup will be numerically different, and secondly, the "adding"
process will cause a loss (spillage, evaporation, a drop or two left behind?. The present invention addresses a similar problem: that of attempting to obtain numerically accurate sums of inherently numerically inaccurate units.
The quality of the DAC is directly measured by the number of "true" bits it can convert (i.e. the 'resolution' of the DAC). This means that the DAC can convert with numerical accuracy down to +/- 1/2 bit. Typically this is limited by a number of factors, such as circuit noise inherent in the final unit elements and analog summation, mismatches between the unit elements, and the like.
IN DIGITAL-TO-ANALOG CONVERTERS
FIELD OF INVENTION
The present invention relates to a method and apparatus for correcting element mismatch in digital-to-analog converters.
BACKGROUND OF THE INVENTION
Digital-to-Analog Converters (DACs) can be used in any interface between a digital system and the physical world, as seen in Figure 1. The more bits the DAC can convert, the more resolution it has, with the result of a better quality analog signal output (e. g. better sound for a CD or DAT, better video for a TV signal, and the like). DACs have numerous applications in the telecommunications industry. The present invention addresses, although is not limited to, a particular application of a DAC in a telecommunication application.
The present invention addresses the simplest of DAC
implementations. To those versed in the art, the simplest DAC
implementation consists of converting a digital word to a numerical value, then summing that number of analog unit values, producing a net analog signal integrally related to the numerical value. For example, if one wanted to convert the binary number '011' to analog form, it would be evaluated as the number '3'. The DAC would select three elements from the unit array, and sum them to give the desired output, as in Figure 2.
As indicated above, the DAC sums a number of analog units together to produce a desired output value. Thus, the accuracy of the conversion is directly related to accuracy of the analog units summed, and the summing process. Numerically 1+1=2. However, physical units, of physical quantities, do not exhibit numerical accuracy. For example: when baking, one cup of water and one cup of water equals two cups of water. This may be true theoretically; however, if you were to count the number of water molecules an individual transfers, a large discrepancy would always be found. First, each individual cup will be numerically different, and secondly, the "adding"
process will cause a loss (spillage, evaporation, a drop or two left behind?. The present invention addresses a similar problem: that of attempting to obtain numerically accurate sums of inherently numerically inaccurate units.
The quality of the DAC is directly measured by the number of "true" bits it can convert (i.e. the 'resolution' of the DAC). This means that the DAC can convert with numerical accuracy down to +/- 1/2 bit. Typically this is limited by a number of factors, such as circuit noise inherent in the final unit elements and analog summation, mismatches between the unit elements, and the like.
The present invention addresses the mismatches between the unit elements. The importance of The present invention can be illustrated in its application in a DAC used in an oversampled Sigma-Delta Bandpass Analog to Digital Converter (ADC). The DAC in a oversampled ADC has very stringent requirements, and sets limits of performance on the overall ADC. Those versed in the art, know that the linearity of the DAC must be equivalent or higher than that of the overall ADC. For example: a sixteen bit ADC requires its DAC to be accurate to sixteen bits, even though the DAC may only be a two bit machine.
Numerical bit accuracy, or "linearity" is illustrated below in Figures 3 and 4. It is wellknown, to those versed in the art, that any circuit that has a non-linear transfer function tends to introduce 'harmonics' or distortion in the output of the circuit, which degrades performance as can be seen in Figures 5 and 6. In the case of a DAC, the amount of distortion is directly related to the resolution of the DAC.
More distortion means less resolution. In most circuit technologies today, it is typical to get circuit elements to match to within 0.1% of each other. This translates into a resolution of ten bits for a DAC. Hence, some kind of correction is required to realize DACs with higher resolution.
Conventional approaches to this problem, in Integrated Circuit DACs, have been to utilize some kind of trimming technique; attempts to try and match the DAC elements perfectly after the chip has been fabricated. This is expensive, and limited in accuracy, and therefore not suited for production in large volumes. Other methods have been to try and adjust the unit DAC elements internally with extra circuitry. This is a reasonable method; however, it is itself limited in accuracy and requires extra circuitry and complexity.
Another approach to this problem has been to use a 'smart algorithm'. This is a method to select which unit elements, out of a pool of elements, to sum at any given time. For example, if we want to select two unit elements from the pool, we do not need to select the same two elements every time. The way in which one decides which two elements to select, one alters the statistics of the error in the choice. Oversampled ADCs produce "statistically" correct values. By forcing the ADC's DAC to be "statistically" correct, the ADC will perform as if the DAC is in fact correct . These algorithms vary in the degree of the "statistical" correction they produce. Also, and equally important, the statistics are shaped in the frequency domain.
This frequency shaping is absolutely critical. To those skilled in the art, it is known that the usefulness of the algorithm depends explicitly on its ability to perform desired frequency shaping.
Numerical bit accuracy, or "linearity" is illustrated below in Figures 3 and 4. It is wellknown, to those versed in the art, that any circuit that has a non-linear transfer function tends to introduce 'harmonics' or distortion in the output of the circuit, which degrades performance as can be seen in Figures 5 and 6. In the case of a DAC, the amount of distortion is directly related to the resolution of the DAC.
More distortion means less resolution. In most circuit technologies today, it is typical to get circuit elements to match to within 0.1% of each other. This translates into a resolution of ten bits for a DAC. Hence, some kind of correction is required to realize DACs with higher resolution.
Conventional approaches to this problem, in Integrated Circuit DACs, have been to utilize some kind of trimming technique; attempts to try and match the DAC elements perfectly after the chip has been fabricated. This is expensive, and limited in accuracy, and therefore not suited for production in large volumes. Other methods have been to try and adjust the unit DAC elements internally with extra circuitry. This is a reasonable method; however, it is itself limited in accuracy and requires extra circuitry and complexity.
Another approach to this problem has been to use a 'smart algorithm'. This is a method to select which unit elements, out of a pool of elements, to sum at any given time. For example, if we want to select two unit elements from the pool, we do not need to select the same two elements every time. The way in which one decides which two elements to select, one alters the statistics of the error in the choice. Oversampled ADCs produce "statistically" correct values. By forcing the ADC's DAC to be "statistically" correct, the ADC will perform as if the DAC is in fact correct . These algorithms vary in the degree of the "statistical" correction they produce. Also, and equally important, the statistics are shaped in the frequency domain.
This frequency shaping is absolutely critical. To those skilled in the art, it is known that the usefulness of the algorithm depends explicitly on its ability to perform desired frequency shaping.
The present invention is the means and algorithm to simply and efficiently set nulls in the DAC error frequency distribution, at arbitrary frequencies. This has direct application to Bandpass ADCs and Bandpass DACs.
One algorithm takes the approach of randomly selecting the DAC unit elements, from a pool of units. By this means, one can eliminate the distortion inherent in the DAC. This is the simplest algorithm that works. It attempts to make the mismatch appear as white noise, equally distributed in the frequency domain. The drawback of this approach is that it achieves limited success in a particular class of DACs called Oversampled (or ED) DACs. These DACs operate on the principle that one is only interested in signals that have a bandwidth much smaller than the sampling rate (as opposed to nyquist DACs which can operate with signals with frequencies up to half the sampling rate).
Another algorithm that has been used is called Data-weighted averaging. This particular algorithm has especially good performance for E~ DACs. Unfortunately, its application is limited to use with lowpass E~ DACs. It is also important to mention that this is a narrowband algorithm (i.e.
only good for frequency bandwidths much less than the sampling rate) and does not yield as good performance for normal Nyquist-rate DACs. The Data-weighted Averaging algorithm can be seen in Figure 7, shown for a three bit DAC having eight elements.
This algorithm cycles through a11 the unit elements so that the average error between DAC elements is zero over a long period of time. For example, for a DC input of '3' into the DAC, the first cycle would consist of the first three elements being summed to give the analog output. For the second cycle, the four, five, and six elements would be summed. For the third cycle, the seven, eight and one elements would be summed (the 'pointer' would wrap around to start at the first element again) . Since we have selected a11 the elements at least once, over the last three cycles, the average error has been minimized. Over many cycles, it can be shown that the error for any low-frequency inputs is minimized. However, as mentioned above, this method of averaging the error does not work if the input is not low frequency compared to the sampling rate of the DAC.
SUMMARY OF THE INVENTION
The present invention generalizes the use of the Data-weighted Averaging algorithm for use with signals that are not lowpass. The present inventions allows the signal band of interest to be situated anywhere in the frequency domain. This is a significant advantage and improvement in the art.
The present invention utilizes a similar initial approach as the preceding algorithm; however, it makes use of multiple 'pointers' to the unit elements. The number of pointers determines exactly at what frequency the element mismatch cancellation occurs. For example, having one pointer (as in the original algorithm) cancels element mismatch error near to DC. For larger numbers of pointers, the simple formula to find the frequency at which the element mismatch is cancelled is:
f8 J cant -n where franc is the mismatch cancelling frequency, n is the number of pointers, and fs is the sampling frequency of the DAC . So, i f one wants to minimi ze the error around a frequency of fs/4, one would need four pointers to the DAC elements.
Each pointer is utilized in subsequent order and follows the same choosing algorithm as the normal Data-Weighted Averaging algorithm outlined above; see Figure 7. In Figure 8 we can see the operation of the algorithm for a three bit DAC with eight elements, trying to achieve mismatch cancellation at a frequency of fs/4. The result on the output of the DAC is shown below in Figure 9.
According to the invention, there is provided an apparatus for correcting element mismatch in digital-to-analog converters, comprising data-weighted averaging means for use with signals that are not lowpass, and multiple pointers, whereby the number of pointers determines the frequency at which the element mismatch cancellation occurs.
Other advantages, objects and features of the present invention will be readily apparent to those skilled in the art from a review of the following detailed description of preferred embodiments in conjunction with the accompanying drawings and claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The embodiments of the invention will now be described with reference to the accompanying drawings.
DETAILED DESCRIPTION OF THE INVENTION
The flowchart representation of the algorithm is shown in Figure 10, and is summarized as follows for a spectral null at Fs/n and a conversion for a digital value "m".
A first counter (counter = l:n) cyclically selects one out of ' n' pointers (pointer~l:"~ ) used each time a selection of units is to be made. Then the next 'm' units pointed to by that pointer are used. The pointer is then incremented by ' m' .
If the pointer value is greater than 'num' (the number of unit elements in the DAC), it 'wraps around' and resumes counting from '1'. Mathematically, we subtract 'num' from the current value of the painter .to yield the actual position of the pointer.
The entire process is then repeated for the next 'm' value.
This selection process forces a statistical null at Fs/n.
Since we want to use the pointers to the element array in sequence, a 'counter' controls exactly which pointer we use.
So, when DAC elements are to be selected, the 'counter' is checked, and that particular painter is used. For example, if the 'counter' was set to '1', then the first pointer is selected. The analog 'output' of the DAC is formed by summing a number of unit elements equal to the digital 'input' number into the DAC, starting at the element that the first pointer is pointing at. If the value of the pointer exceeds the number of unit elements, it reverts back to pointing at the first element in the array. Once the analog ' output' has been summed for the digital 'input' number, the 'counter' is incremented by one, in preparation for the next time the DAC must be used.
The present invention is designed as a digital circuit, as can be seen in Figure 11, and implemented in a BiCMOS
process. It is not just limited to a digital implementation, and can in fact be implemented in software as well. The operation of this digital circuit is the same as the discussion given above for Figure 10 . The ' Element Selection Logic' block is a simple combination of logic gates that selects ' in' output selection lines, starting at the element line given by the ' pntr' signal . The number of pointers is given by ' m' , and ' k' is given as the number of bits needed to represent the numbers from 0 to 'm'. 'n' is the number of input bits that the DAC
has, and 2n-1 is the number of unit elements to choose from the input digital code.
Numerous modifications, variations and adaptations may be made to the particular embodiments of the invention described above without departing from the scope of the invention, which is defined in the claims.
:L 0
One algorithm takes the approach of randomly selecting the DAC unit elements, from a pool of units. By this means, one can eliminate the distortion inherent in the DAC. This is the simplest algorithm that works. It attempts to make the mismatch appear as white noise, equally distributed in the frequency domain. The drawback of this approach is that it achieves limited success in a particular class of DACs called Oversampled (or ED) DACs. These DACs operate on the principle that one is only interested in signals that have a bandwidth much smaller than the sampling rate (as opposed to nyquist DACs which can operate with signals with frequencies up to half the sampling rate).
Another algorithm that has been used is called Data-weighted averaging. This particular algorithm has especially good performance for E~ DACs. Unfortunately, its application is limited to use with lowpass E~ DACs. It is also important to mention that this is a narrowband algorithm (i.e.
only good for frequency bandwidths much less than the sampling rate) and does not yield as good performance for normal Nyquist-rate DACs. The Data-weighted Averaging algorithm can be seen in Figure 7, shown for a three bit DAC having eight elements.
This algorithm cycles through a11 the unit elements so that the average error between DAC elements is zero over a long period of time. For example, for a DC input of '3' into the DAC, the first cycle would consist of the first three elements being summed to give the analog output. For the second cycle, the four, five, and six elements would be summed. For the third cycle, the seven, eight and one elements would be summed (the 'pointer' would wrap around to start at the first element again) . Since we have selected a11 the elements at least once, over the last three cycles, the average error has been minimized. Over many cycles, it can be shown that the error for any low-frequency inputs is minimized. However, as mentioned above, this method of averaging the error does not work if the input is not low frequency compared to the sampling rate of the DAC.
SUMMARY OF THE INVENTION
The present invention generalizes the use of the Data-weighted Averaging algorithm for use with signals that are not lowpass. The present inventions allows the signal band of interest to be situated anywhere in the frequency domain. This is a significant advantage and improvement in the art.
The present invention utilizes a similar initial approach as the preceding algorithm; however, it makes use of multiple 'pointers' to the unit elements. The number of pointers determines exactly at what frequency the element mismatch cancellation occurs. For example, having one pointer (as in the original algorithm) cancels element mismatch error near to DC. For larger numbers of pointers, the simple formula to find the frequency at which the element mismatch is cancelled is:
f8 J cant -n where franc is the mismatch cancelling frequency, n is the number of pointers, and fs is the sampling frequency of the DAC . So, i f one wants to minimi ze the error around a frequency of fs/4, one would need four pointers to the DAC elements.
Each pointer is utilized in subsequent order and follows the same choosing algorithm as the normal Data-Weighted Averaging algorithm outlined above; see Figure 7. In Figure 8 we can see the operation of the algorithm for a three bit DAC with eight elements, trying to achieve mismatch cancellation at a frequency of fs/4. The result on the output of the DAC is shown below in Figure 9.
According to the invention, there is provided an apparatus for correcting element mismatch in digital-to-analog converters, comprising data-weighted averaging means for use with signals that are not lowpass, and multiple pointers, whereby the number of pointers determines the frequency at which the element mismatch cancellation occurs.
Other advantages, objects and features of the present invention will be readily apparent to those skilled in the art from a review of the following detailed description of preferred embodiments in conjunction with the accompanying drawings and claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The embodiments of the invention will now be described with reference to the accompanying drawings.
DETAILED DESCRIPTION OF THE INVENTION
The flowchart representation of the algorithm is shown in Figure 10, and is summarized as follows for a spectral null at Fs/n and a conversion for a digital value "m".
A first counter (counter = l:n) cyclically selects one out of ' n' pointers (pointer~l:"~ ) used each time a selection of units is to be made. Then the next 'm' units pointed to by that pointer are used. The pointer is then incremented by ' m' .
If the pointer value is greater than 'num' (the number of unit elements in the DAC), it 'wraps around' and resumes counting from '1'. Mathematically, we subtract 'num' from the current value of the painter .to yield the actual position of the pointer.
The entire process is then repeated for the next 'm' value.
This selection process forces a statistical null at Fs/n.
Since we want to use the pointers to the element array in sequence, a 'counter' controls exactly which pointer we use.
So, when DAC elements are to be selected, the 'counter' is checked, and that particular painter is used. For example, if the 'counter' was set to '1', then the first pointer is selected. The analog 'output' of the DAC is formed by summing a number of unit elements equal to the digital 'input' number into the DAC, starting at the element that the first pointer is pointing at. If the value of the pointer exceeds the number of unit elements, it reverts back to pointing at the first element in the array. Once the analog ' output' has been summed for the digital 'input' number, the 'counter' is incremented by one, in preparation for the next time the DAC must be used.
The present invention is designed as a digital circuit, as can be seen in Figure 11, and implemented in a BiCMOS
process. It is not just limited to a digital implementation, and can in fact be implemented in software as well. The operation of this digital circuit is the same as the discussion given above for Figure 10 . The ' Element Selection Logic' block is a simple combination of logic gates that selects ' in' output selection lines, starting at the element line given by the ' pntr' signal . The number of pointers is given by ' m' , and ' k' is given as the number of bits needed to represent the numbers from 0 to 'm'. 'n' is the number of input bits that the DAC
has, and 2n-1 is the number of unit elements to choose from the input digital code.
Numerous modifications, variations and adaptations may be made to the particular embodiments of the invention described above without departing from the scope of the invention, which is defined in the claims.
:L 0
Claims
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An apparatus for correcting element mismatch in digital-to-analog converters, comprising data-weighted averaging means for use with signals that are not lowpass, and multiple pointers, whereby the number of pointers determines the frequency at which the element mismatch cancellation occurs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2229756 CA2229756A1 (en) | 1998-02-18 | 1998-02-18 | Method and apparatus for correcting element mismatch in digital-to-analog converters |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2229756 CA2229756A1 (en) | 1998-02-18 | 1998-02-18 | Method and apparatus for correcting element mismatch in digital-to-analog converters |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2229756A1 true CA2229756A1 (en) | 1999-08-18 |
Family
ID=29409292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2229756 Abandoned CA2229756A1 (en) | 1998-02-18 | 1998-02-18 | Method and apparatus for correcting element mismatch in digital-to-analog converters |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2229756A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1139570A2 (en) * | 2000-03-28 | 2001-10-04 | Kabushiki Kaisha Toshiba | Selecting circuit, digital/analog converter and analog/digital converter |
| EP1402644A2 (en) * | 2001-06-27 | 2004-03-31 | Nokia Corporation | Method and apparatus for suppressing tones induced by cyclic dynamic element matching (dem) algorithms |
-
1998
- 1998-02-18 CA CA 2229756 patent/CA2229756A1/en not_active Abandoned
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1139570A2 (en) * | 2000-03-28 | 2001-10-04 | Kabushiki Kaisha Toshiba | Selecting circuit, digital/analog converter and analog/digital converter |
| EP1139570A3 (en) * | 2000-03-28 | 2004-04-07 | Kabushiki Kaisha Toshiba | Selecting circuit, digital/analog converter and analog/digital converter |
| EP1402644A2 (en) * | 2001-06-27 | 2004-03-31 | Nokia Corporation | Method and apparatus for suppressing tones induced by cyclic dynamic element matching (dem) algorithms |
| EP1402644A4 (en) * | 2001-06-27 | 2004-09-01 | Nokia Corp | Method and apparatus for suppressing tones induced by cyclic dynamic element matching (dem) algorithms |
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