CA2220993A1 - Processeur monoinstruction pour donnees multiples - Google Patents

Processeur monoinstruction pour donnees multiples Download PDF

Info

Publication number
CA2220993A1
CA2220993A1 CA 2220993 CA2220993A CA2220993A1 CA 2220993 A1 CA2220993 A1 CA 2220993A1 CA 2220993 CA2220993 CA 2220993 CA 2220993 A CA2220993 A CA 2220993A CA 2220993 A1 CA2220993 A1 CA 2220993A1
Authority
CA
Canada
Prior art keywords
data
processing
shift
values
single instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2220993
Other languages
English (en)
Inventor
Paul Marriott
Tahar Ali Yahia
Qunshan Gu
Yvon Savaria
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ecole Polytechnique de Montreal
Original Assignee
Ecole Polytechnique de Montreal
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ecole Polytechnique de Montreal filed Critical Ecole Polytechnique de Montreal
Priority to CA 2220993 priority Critical patent/CA2220993A1/fr
Publication of CA2220993A1 publication Critical patent/CA2220993A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015One dimensional arrays, e.g. rings, linear arrays, buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Multi Processors (AREA)
CA 2220993 1997-11-07 1997-11-07 Processeur monoinstruction pour donnees multiples Abandoned CA2220993A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA 2220993 CA2220993A1 (fr) 1997-11-07 1997-11-07 Processeur monoinstruction pour donnees multiples

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA 2220993 CA2220993A1 (fr) 1997-11-07 1997-11-07 Processeur monoinstruction pour donnees multiples

Publications (1)

Publication Number Publication Date
CA2220993A1 true CA2220993A1 (fr) 1999-05-07

Family

ID=29275205

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2220993 Abandoned CA2220993A1 (fr) 1997-11-07 1997-11-07 Processeur monoinstruction pour donnees multiples

Country Status (1)

Country Link
CA (1) CA2220993A1 (fr)

Similar Documents

Publication Publication Date Title
US7249242B2 (en) Input pipeline registers for a node in an adaptive computing engine
US6496918B1 (en) Intermediate-grain reconfigurable processing device
US20030014457A1 (en) Method and apparatus for vector processing
KR100190738B1 (ko) 데이타 처리 시스템 및 방법
US5287532A (en) Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
JP3573755B2 (ja) 画像処理プロセッサ
US6446190B1 (en) Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor
US7873812B1 (en) Method and system for efficient matrix multiplication in a SIMD processor architecture
US4943909A (en) Computational origami
EP0425410B1 (fr) Processeur de signal avec une unité arithmétique et logique et une unité multiplieur-accumulateur pouvant être utilisées simultanément
US7725520B2 (en) Processor
US20100274988A1 (en) Flexible vector modes of operation for SIMD processor
EP0743593A1 (fr) Réplication de données
EP0726532A2 (fr) Architecture de réseau de processeurs pour la communication avec diffusion d'instructions
US6209078B1 (en) Accelerated multimedia processor
Taylor et al. A high-performance flexible architecture for cryptography
KR19980069855A (ko) 넓은 데이터 폭의 프로세서에서 다기능 데이타 정렬기
CA2725136A1 (fr) Techniques de microprocesseur pour le traitement et l'actualisation de signaux reels
WO2006136764A1 (fr) Processeur de donnees et procede d'acceleration de l'execution de sous-graphiques
US20040078554A1 (en) Digital signal processor with cascaded SIMD organization
US20190235863A1 (en) Sort instructions for reconfigurable computing cores
US6999985B2 (en) Single instruction multiple data processing
US6915411B2 (en) SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath
US20100115232A1 (en) Large integer support in vector operations
CN112074810B (zh) 并行处理设备

Legal Events

Date Code Title Description
FZDE Dead