CA2191162C - Current controlled gate pulse amplifier - Google Patents

Abstract

This circuit provides for a capacitor to be charged to a working level while a small current is allowed to flow through a transistor-resistor circuit which is paralleled with the gate circuitry of a thyristor. Under quiescent operating conditions when the gate circuitry is not energized, only a small current flows in the transistor-resistor circuit. Upon receipt of a turn on signal from the trigger circuit, the gate circuitry is switched on allowing the capacitor to discharge through the gate circuitry into the gate of the load thyristor.
A second transistor connected into the transistor-resistor circuit allows the initial steep pulse to be transmitted to the gate, but the gate current is limited as the second transistor biases the first transistor into a state where only a limited current may pass to the thyristor gate.

Description

CURRENT CONTROLLED GATE PULSE AMPLIFIER
This invention is an energy efficient method of delivering turn on gate pulses to a power thyristor gate terminals. A power thyristor, properly applied in electrical circuits, requires a minimum gate current rise time and level s to safely and successfully switch from its off-state to its on-state. This design's components can be set to provide the required output rise time and not only provide at least the minimum gate current but also regulate the output current level so that excess output does not occur. Because of this to regulating action, the amplifier draws the minimum power from the AC electrical supply.
This circuit is especially useful for application in the firing of a large number of series or parallel connected thyristors where it is desired that all the thyristors in a group is should be turned on at the same time. When connected to an amplifier like this, each thyristor receives the correct current, no more and no less, satisfying the thyristor requirements and at the same time significantly reducing the demand on the gate energy source.

? i ~ 1 16 2 GECAN 3152 BACKGROUND OF THE INVENTION
Gate current is required to activate the thyristor to conduct current between its anode and cathode. Prior art teachings will show that in order to have a reliable turn-on of s the main conducting body of the thyristor, a gate current with a prescribed rise time and level is required to ensure the initial turned on area is large enough to avoid hot spots during the initial rise of anode to cathode currents.
Much effort has gone into the design of circuitry to which is best adapted to provide this gate current, however, most mass-produced gate pulse amplifier designs end up providing the minimum required gate current to thyristors with the highest gate impedance but supply more gate current than necessary to thyristors which have gate Is impedances below the maximum. Because any thyristor might be connected to the gating circuit, it will be readily apparent that in general these gating circuits will supply more current than necessary. As a result, significantly more gate power is drawn from the gate power supply than would 2o be necessary if each thyristor received only its minimum gate current requirement. This effect becomes even more significant when large groups of thyristors are involved, such as a large commercial power converter or rectifier.
Most prior art circuits of this nature traditionally 2s place a fixed resistor between the gate pulse voltage source and the thyristor gate input which is sized to provide sufficient current when a thyristor with maximum gate impedance is connected into the circuit. When a thyristor with less than maximum gate impedance is connected into s the circuit, the resulting current will be higher than required and thus, power is wasted in both this series resistance and the thyristor gate itself. Because most thyristors will have gate impedances somewhat less than the maximum gate impedance, power will be wasted in most prior art resistor -lo thyristor gate combinations.
The resulting gate currents produced by the prior art circuits are obviously not equal because of the uneven gate impedances as set out above. Because of this, it will generally be found that turn-on stresses occur in some of the Is thyristors in a series string, resulting in an uneven distribution of voltage due to fractional differences in turn-on times, and similar stresses occur in parallel connected thyristors because of unequal current distribution during turn-on times.
2o SUMMARY OF THE INVENTION
The circuit of this invention finds its widest application in situations where large numbers of thyristors are grouped together in series or parallel configurations to supply power to a load. Because of the wide variations in 2s the gate to cathode impedances which exist in thyristors of the same family, prior art designers have generally inadvertently over supplied the gates of the thyristor with gate turn-on current.
This circuit is particularly suited to multi-thyristor s applications because it is relatively insensitive to variations in the gate to cathode impedances. This circuit is able to provide the correct amount of gate current to power thyristors whose gate impedances span a wide range of values.
to When triggered by a gate signal, the gating source circuit of this invention immediately produces a steep wave front for the gate of the power thyristor. In addition, the gate pulse may have an additional current superimposed on the leading edge of each gating pulse to tailor the gate pulse is to the firing characteristics specific to a particular thyristor family. A pair of transistors serve to regulate the gate pulse current to an acceptable level. The gate circuitry of this invention is important for another reason; this circuitry will supply gate pulse currents in which the pulses of gate 2o current are almost identical even though the pulses of gate current are generated in a large number of gate current generation circuits. This feature is important for the power converter and rectifier installations where circuit reliability and consistent gate turn on is a must. Equal gate currents 2s cause turn-on of thyristors to be more uniform among the group. This results in reduced turn-on stress because voltage is shared more evenly in the series cause and current is shared more evenly in the parallel case.
BRIEF DESCRIPTION OF THE DRAWINGS
s FIGURE 1 is a circuit diagram of the gate pulse amplifier of this invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Figure 1 illustrates a circuit 10 which accomplishes the objects of this invention.
to Terminals 12 and 14 are supplied with a suitable source of AC power. Diodes 16, 18, 20 and 22 provides a bridge to provide full wave rectified DC power to the series resistor-capacitor combination 26 and 28. The collector-emitter terminals of transistor 30 are connected in series with is resistors 32 and 34 across the capacitor 28.
A resistor 36 is connected between the base and collector of transistor 30, and a transistor 38 is connected into the circuit so that its base is connected between the emitter of transistor 30 and resistor 32. The emitter of 2o transistor 38 is connected to the junction of resistors 32 and 34. The collector of transistor 38 is connected to the junction of resistor 36 and the base terminal of transistor 30.

Resistor 34 is connected to the negative terminal 24 of the input diode bridge.
Resistor 40, resistor 42 and drain source terminals of N-Channel FET 44 are connected in parallel s across resistor 34.
A zener diode 48 is connected in parallel with resistor 40, as are the source gate terminals of P-Channel F ET 50.
The gate-drain terminals of P-Channel FET 50 to and a diode 52 are connected in parallel with resistor 42 and drain-source terminals of N-Channel FET 44.
A capacitor 54 is connected across the source drain terminals of P-Channel FET 50 and diode 52. Input optical amplifier 56 is connected to the gate terminal of FET
is 44 and to negative terminal 24.
Terminals 58 and 60 are connected to the gate and cathode terminals of the power thyristor which is being turned on by the above circuit. These terminals are connected to the drain terminal of FET 50 and negative 2o terminal 24. Diode 52 is connected across terminals 58 and 60.
The circuit functions as follows:

A suitable source of AC power is connected to terminals 12 and 14. Capacitor 28 is charged via resistor 26 to a predetermined potential by the diode bridge network.
Transistor 30 is biased into a conductive mode by resistor 36 and current flow through resistors 32 and 34 results.
Resistor 32 is of low value resistance, but the resistance value of resistor 34 is large, thus limiting the quiescent current to a very small value. Capacitor 54 is charged to a potential approximately equal to that of capacitor 28 under to steady state conditions.
At this time, FETs 44 and 50 are turned off as is transistor 38. Capacitor 28 is charged to the maximum potential as determined by the input AC voltage.
When an optical signal appears at optical Is receiver 56 the following events occur:
(1 ) N-Channel MOS FET 44 turns on;
(2) Current begins to flow in the branch, resistor 40, resistor 42 and the drain source terminals of N-Channel MOS FET 44;
20 (3) The current flow in (2) above results in a voltage drop across resistor 40 which turns P-Channel MOS
FET 50 on;

(4) Capacitor 54 immediately discharges through the source-drain terminals of P-Channel MOS FET 50 to supply an initial current to the terminals 58 and 60 of the gate input circuit of the power thyristor. This steep wave s front assures positive turn on of the thyristor gate.
(5) Transistor 30 begins to conduct a larger current as capacitor 54 discharges because of conduction of current through P-Channel MOS FET 50 to the thyristor gate.
to This is the condition existing in the circuit 10 during the initial few microseconds following receipt of an optical signal in optical receiver 56. As the optical signal persists the following events occur:
(1 ) Resistor 32 experiences a significant increase Is in current flow (because of conduction of FET 50).
(2) Current flow through resistor 32 turns transistor 38 on which shunts current away from the base of transistor 30.
(3) This has the effect of turning transistor 30 off, 2o tending to limit the current flow through source-drain terminals of FET 50 and thyristor gate and cathode terminals 58 and 60.

At this time the value of resistor 32 determines the magnitude of the current passed by transistor 30 to the gate terminal 58 under the steady state turn on conditions.
As soon as the optical signal on the optical s receiver 56 ceases, FET's 44 and 50 cease conducting and the preset thyristor gate current provided by transistors 30 and 38 ceases because FET 50 has been turned off.
At this time capacitor 28 begins to charge to its steady state value, as does capacitor 54, and transistor 30 to returns to its mode where it conducts the very small quiescent current through resistors 32 and 34.
Zener diode 48 protects the gate of the FET 50 from overvoltage surges. Diode 52 protects the current controlled gate pulse amplifier from high voltage spikes fed Is back into the amplifier 10 from the gate (58, 60) of the power thyristor under fault or high noise conditions.
Capacitor 54 is a very efficient device to produce the steep initial wavefront which is critical for efficient gate turn on. Once the gate has received the initial gate pulse, 2o the amplifier 10 reduces the current supplied to the gate terminals by the action of resistor 32 in combination with transistors 30 and 38.

In summary, this circuit is much more efficient than the prior art circuits utilizing a series resistor in the gate circuit to limit the gate current.
The effect of the regulated output gate current s produced by this invention enhances both series and parallel operation of large groups of thyristors because of the more uniform thyristor turn-on times. Each thyristor essentially receives the same gate current and this results in a positive effect in reducing the stresses produced in series and to parallel circuits during turn-on times.
The overall result in the reduction in power required by the gate pulse generation circuit and the additional longevity and reliability of the thyristor circuits which are being turned-on by the circuit of this invention.

Claims (8)

1. A circuit for supplying pulses of gate current to the gate of a power thyristor in response to receipt of gating signals from a gating signal device, comprising;
power supply means for supplying DC power to said circuit to energize said circuit, first transistor means responsive to the presence of a gating signal, to turn on and initiate a first current flow through said first transistor means and an impedance network associated therewith, second transistor means connected to the gate of said thyristor and being responsive to current flow through said impedance network to become conductive and permit current to flow into the gate of said thyristor, capacitor means associated with said second transistor means to provide an initial current through said second transistor means during the initial period when said second transistor means begins to conduct, said capacitor being changed by said power supply means, and third transistor circuit means connected between said power supply means and said second transistor means to regulate the level of current flow from said power supply means through said second transistor means to said gate.

2. A circuit as claimed in claim 1 wherein said third transistor circuit means comprises at least one transistor in a series circuit between said power supply and said gate to regulate the flow of current from said power supply to said gate when said second transistor means is conductive.

3. A circuit for the generation of pulses of gate current for the gate of a power thyristor comprising:
first transistor means connected with the gate of the thyristor and actuable by a gate signal source to turn-on and permit current to flow from a power source to said gate, capacitor means also connected into said circuit and to said first transistor means for supplying additional current to said gate upon initial turn-on of said first transistor means, a second transistor means serially connected into said circuit with said first transistor means to control the flow of gate current from said power supply to said gate to a predetermined level, said capacitor means being charged to a charged state by said power supply during periods of non-conduction of said first transistor means.

4. A circuit as claimed in claim 3 wherein said second transistor means comprises a pair of transistors connected into the circuit so that a first transistor of said pair is always in a conductive state.

5. A circuit as claimed in claim 4 wherein said first transistor carries pulses of gate current during periods of current flow from said power source through said second transistor means and through said first transistor means to said gate.

6. A circuit as claimed in claim 5 wherein a second transistor of said pair is connected to said first transistor in such a manner as to regulate the flow of gate current through said first transistor periods of flow of gate current in said circuit.

7. A circuit as claimed in claim 6 wherein said first transistor means comprises a pair of MOS FET transistors, in which a first transistor of said pair is a P-Channel MOS FET, and the second transistor of said pair is an N-Channel MOS
FET.

8. A circuit as claimed in claim 7 wherein said first transistor of said pair of MOS FET transistors conducts pulses of gate current of said gate.