CA2150219C - Micropin array and production method thereof - Google Patents
Micropin array and production method thereofInfo
- Publication number
- CA2150219C CA2150219C CA002150219A CA2150219A CA2150219C CA 2150219 C CA2150219 C CA 2150219C CA 002150219 A CA002150219 A CA 002150219A CA 2150219 A CA2150219 A CA 2150219A CA 2150219 C CA2150219 C CA 2150219C
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- CA
- Canada
- Prior art keywords
- micropins
- micropin
- insulating coating
- array
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Lead Frames For Integrated Circuits (AREA)
Abstract
A micropin array has a plurality of micropins having a given diameter and being aligned in parallel to one another at a given pitch, insulating tubular coatings disposed to cover individual micropins, and an adhesive provided to fill spacings among the insulating tubular coatings. A method for connection of the micropin array has the steps of providing a pad on a surface of each micropin of the array, alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure, and subjecting that structure to reflow treatment.
Description
~1~021~
MICROPIN ARRAY AND PRODUCTION METHOD THEREOF
The present invention relates to a micropin array, and more specifically relates to a method for connection of the micropin array.
Conventionally, in the PGA package of ah IC device, there are utilized l/O pins in the form of a set of micropins whi~h are separately and independently fixed to an LSI chip. Such micropins ar~ produced such that a lead wire material is treated by mechanical working ~uch as stamping with header processing to form individual micropins. Namely, the micropins are produced in a manner similar to the production method of the typical l/O pins attached to the typical PGA package. There may be other methods such as utilizing photolithographic technology to form chemically the micropins. These methods of producing micropins are disclosed, for example, in Japanese Patent Publication Nos. 62-24916, 62-32591, 62-32592 and 63-28515.
In the use of the conventional micropins for electrical connection to an LSI chip, the micropins are individually fixed to the LSI chip in a given alignment pitch, thereby disadvantageously requiring a highly-accurate alignment tool. Further, since the micropins are connected to the LSI chip one by one, micropins are easily curved or folded to thereby disadvantageously degrade the mechanical strength of an assembly.
MICROPIN ARRAY AND PRODUCTION METHOD THEREOF
The present invention relates to a micropin array, and more specifically relates to a method for connection of the micropin array.
Conventionally, in the PGA package of ah IC device, there are utilized l/O pins in the form of a set of micropins whi~h are separately and independently fixed to an LSI chip. Such micropins ar~ produced such that a lead wire material is treated by mechanical working ~uch as stamping with header processing to form individual micropins. Namely, the micropins are produced in a manner similar to the production method of the typical l/O pins attached to the typical PGA package. There may be other methods such as utilizing photolithographic technology to form chemically the micropins. These methods of producing micropins are disclosed, for example, in Japanese Patent Publication Nos. 62-24916, 62-32591, 62-32592 and 63-28515.
In the use of the conventional micropins for electrical connection to an LSI chip, the micropins are individually fixed to the LSI chip in a given alignment pitch, thereby disadvantageously requiring a highly-accurate alignment tool. Further, since the micropins are connected to the LSI chip one by one, micropins are easily curved or folded to thereby disadvantageously degrade the mechanical strength of an assembly.
2 o In the conventional method of producing mi¢ropins according to the mechanical working, there is a practical limitation in the diameter and length dimension of micropins due to a dimensional error in the header processing.
Therefore, it is difficult to practically produce a pin having a diameter less than 0.1 mm.
On the other hand, a fine pin having a diameter less than 0.1 mm can be formed by the photolithographic technology. However, the aspect ratio thereof, i.e., pin length/pin diameter ratio cannot be increased by this method.An object of the present invention is to provide a method for connection of a micropin array.
One type of micropin array to which the method has application includes a plurality of micropins arranged parallel to on~ another, an insulating coating provided to cover each of the micropins, and an adhesive provided to fill gaps between the micropins covered with the insulating coatings, wherein the micropins are positioned such that the center points of the cross sections of three adjacent micropins form vertices of an equilateral triangle.
Another type of micropin array to which the method has application includes a first plurality of micropins arranged in rows and columns at a predetermined pitch and parallel to one another, a first insulating coating provided to cover each of the first plurality of micropins, a second plurality of micropins positioned such that one of the second plurality of micropins is at the center point of a square defined by four adjacent micropins of the first plurality of micropins arranged in rows and columns, a second insulating coating provided to cover each of the second plurality of micropins, and an adhesive provided to fill gaps between the first and second pluralities of micropins covered with the first and second insulating coatings.
According to the present invention, there is provided a method for connection of a micropin array comprising the steps of: providing a pad on a surface of each micropin of the above-mentioned micropin arrays, alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on the pad to form a multilayer structure, and subjecting the multilayer structure to reflow treatment.
The invention will next be further described by means of preferred embodiments, utilizing the accompanying drawings, in which:
Figure 1 is a perspective view of a section of an embodiment of the micropin array;
Figure 2 is a perspective view of a section of another embodiment of the micropin array;
Figure 3 is a cross-sectional view of the embodiment of Figure 2;
Therefore, it is difficult to practically produce a pin having a diameter less than 0.1 mm.
On the other hand, a fine pin having a diameter less than 0.1 mm can be formed by the photolithographic technology. However, the aspect ratio thereof, i.e., pin length/pin diameter ratio cannot be increased by this method.An object of the present invention is to provide a method for connection of a micropin array.
One type of micropin array to which the method has application includes a plurality of micropins arranged parallel to on~ another, an insulating coating provided to cover each of the micropins, and an adhesive provided to fill gaps between the micropins covered with the insulating coatings, wherein the micropins are positioned such that the center points of the cross sections of three adjacent micropins form vertices of an equilateral triangle.
Another type of micropin array to which the method has application includes a first plurality of micropins arranged in rows and columns at a predetermined pitch and parallel to one another, a first insulating coating provided to cover each of the first plurality of micropins, a second plurality of micropins positioned such that one of the second plurality of micropins is at the center point of a square defined by four adjacent micropins of the first plurality of micropins arranged in rows and columns, a second insulating coating provided to cover each of the second plurality of micropins, and an adhesive provided to fill gaps between the first and second pluralities of micropins covered with the first and second insulating coatings.
According to the present invention, there is provided a method for connection of a micropin array comprising the steps of: providing a pad on a surface of each micropin of the above-mentioned micropin arrays, alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on the pad to form a multilayer structure, and subjecting the multilayer structure to reflow treatment.
The invention will next be further described by means of preferred embodiments, utilizing the accompanying drawings, in which:
Figure 1 is a perspective view of a section of an embodiment of the micropin array;
Figure 2 is a perspective view of a section of another embodiment of the micropin array;
Figure 3 is a cross-sectional view of the embodiment of Figure 2;
3 o Figure 4 is a perspective view of a section of the embodiment of Figure 2 with pads added thereto;
Figure 5 is a cross-sectional view of the embodiment of Figure 4;
Figure 6 is a cross-sectional view of the embodiment of Figure 4 with solder material added thereto;
Figure 7 is a side elevational view showing an assembly of an IC
5 chip and a circuit substrate connected to each other by the micropin array of Figure 6;
Figure 8 is a perspective view of a section of a further embodiment of the micropin array;
Figure 9 is a perspective view of a section of a still further 10 embodiment of the micropin array;
Figure 10 illustrates examples of wire materials used in the embodiments of the micropin array;
Figure 11 illustrates an alignment pitch of the wire materials;
Figure 12 is a sectional view showing one step of producing the 15 micropin array using a support tool;
Figure 13 is a perspective view of the support tool of Figure 12;
Figure 14 is a sectional view showing another step of producing the micropin array; and, Figures 15 and 16 are perspective views showing different 20 embodiments of the micropin array.
Hereinafter, preferred embodiments of the micropin array will be described in detail with reference to the drawings. In Figure 1 a plurality of micropins 1 having a given diameter and a length are arranged in parallel to oneanother at a constant interval or pitch. Each micropin 1 is covered by an 2 5 electrically-insulating tubular coating 2. An adhesive 4 is provided to fillspacings or gaps among the insulating tubular coatings 2 such that the pluralityof micropins 1 are fixed to one another by the adhesive 4 to form a micropin array 5.
In this embodiment, all of the insulating tubular coatings 2 have the 30 same diameter, with the micropins being horizontally-aligned along a line extending between their sectional centers. Adjacent micropins are disposed in -- 21~0~1~
threes at respective vertices of an equilateral triangle, the sectional centers of the three adjacent micropins forming a lattice having a given pitch.
Figure 2 is a perspective view containing a section of another embodiment of the present invention, and Figure 3 is a view through a vertical 5 side section of Figure 2. In this embodiment, the array is comprised of horizontally-aligned rows and vertically-aligned columns of two interposed sets of micropins 1. Each micropin of one set is surrounded by four adjacent micropins of the other set such that the sectional center of each micropin of the one set is disposed in registration with the diagonal center of the four adjacent micropins of the other set. Each micropin of the one set, having a thinner insulating coating 3, is disposed in a spacing surrounded by thicker insulating coatings 2 of four adjacent micropins of the other set. The sectional centers ofthe respective micropins 1 are aligned to form a staggered lattice. In this embodiment, the micropin 1 is composed of a typical pin material such as Kovar 15 and copper alloy that is typically used in pin grid arrays. The micropin 1 has a 100 ,um diameter and a 2.0 mm length so that the micropins are aligned in a staggered lattice having a pitch of 400 ~m. This alignment pitch corresponds to a pad pitch of a LSI chip which is connected to an external circuit through the micropin array. The individual micropins 1 are covered by two kinds of the 2 o tubular electrically-insulating coatings 2 and 3, having different film thicknesses.
These electrically insulating coatings 2 and 3 are made of, for example, polyimide resin, and their film thickness is determined according to the alignment pitch of the micropins 1.
In this embodiment, the alignment pitch of the micropins is set to 25 400 ,um, hence the thicker electrically-insulating coating 2 has a thickness of 150 ,um as illustrated in Figure 11. This value is calculated according to the following formula: (pitch C - diameter of pin)/2, taking account of the diameterof the micropin 1. On the other hand, the thinner electrically-insulating coating 3 has a thickness of 32 llm. As illustrated in Figure 11, this value is calculated 30 according to the following formula: (pitch C x~2 - 2xdiameter of micropin -~15021~
2xthickness of electrically-insulating coating 2)/2, in order to align the micropins in the staggered lattice.
Returning to Figure 2, the respective electrically-insulating coatings 2 and 3 enclosing the micropins 1 are fixed together by means of adhesive 4.
This adhesive 4 is preferably composed of a specific material selected such thatthe adhesive shrinks slightly during the course of curing so as to closely fix the electrically insulating coatings 2 and 3 of the micropins 1 with each other in order to accurately set the alignment pitch solely by the dimension or thicknessof the electrically insulating coatings 2 and 3. Further, the adhesive 4 should have excellent durability in order to avoid aging change of the alignment pitch of the micropins 1. Moreover, the adhesive 4 should have a good thermal resistance effective to withstand a thermal treatment after the curing, during the course of assembling of the micropin array 5 with an LSI chip. In view of these needed characteristics, the adhesive may be composed, for example, of polyimide resin, maleimide resin or denatured epoxy resin.
Figure 4 is a perspective view containing a section showing arrangement of pads 6 formed on opposite ends of the micropin array 5 of Figures 2 and 3 for electrical connection, and Figure 5 is a vertical side section of Figure 4 when viewed from the side direction.
2 o The pad 6 is formed from a thin film composed of copper, gold and so on, by photolithographic technology such that the pad has a disc shape of 150 ,um diameter and 10 ,um thickness.
Referring to Figure 6, in preparation for coupling to LSI chip, the pads 6 disposed on the ends of the Figure 5 micropin array is clad with a soldermaterial 7 composed of Au-Sn eutectic alloy having composition of 80/20 wt%
and having a melting point of 280~C. The solder material 7 may be composed of other clad alloy such as gold-germanium solder (88/12 wt%) and gold-silicon alloy (94/6 wt%). In the general cladding process of a solder material to l/O
pins in a typical PGA, firstly a pellet of the Au-Sn alloy is formed such that its 3 o weight is calculated according to a header size of the pin. For example, if a pin header is formed in the size of 0.7 - 0.8 mm on the pin having diameter of 0.3 -- ~150213 0.5 mm, the Au-Sn pellet should have the weight of 0.7 - 1.0 mg. Then, the pellet is placed on the pin header to thereby carry out reflow processing.
However, in case of treatment of a small size pin, i.e., micropin, it might be diffficult in view of handling of micropins and tiny solder material pellets to clad accurately a tiny amount of Au-Sn alloy of about 0.1 mg calculated according to the micropin size onto the pin header without substantial variation. In view of this, cladding of Au-Sn solder material 7 over the micropin array 5 can be alternatively effected by metallization with using photolithographic technology in a manner similar to the formation of the pads 6 on the end surface of micropin array 5. Namely, a gold film and a tin film are applied over the pads 6 while controlling their film thickness to set weight ratio of Au/Sn = 80/20. Stated otherwise, gold metallization and tin metallization are carried out to set volume ratio of Au/Sn = 1.55. Then, the metallized gold and tin are subjected to reflowtreatment to form an eutectic alloy of Au-Sn to thereby clad the solder material7. In such case, if a single layer of the metallized gold is superposed on another single layer of the metallized tin, an eutectic reaction may occur locally only along a boundary therebetween, thereby failing to form uniform eutectic alloy composition in the solder material. In view of this, it might be preferable to repeatedly laminate alternately thin films of gold and tin to form a multi-layer structure which is then subjected to the reflow process. In such case, the gold thin film is metallized at a thickness of, for example, 1 ,um, and the tin thin film is metallized at a thickness of 0.7 ,um.
Figure 7 shows a complete assembly in which an LSI chip 8 is mounted on a substrate 9 using the thus-produced micropin array 5.
Figures 8 and 9 show modified micropin arrays in which the respective micropins 1 are surrounded by the electrically-insulating tubular coatings 2 and 3 composed of a porous material such as foam of Teflon resin.
Using the porous insulating coatings can reduce a net dielectric constant to increase a signal transmission speed through the micrapin array.
Hereinafter, the description is given for the method of producing the inventive micropin array with reference to the drawings, in which the array - ~15021~
is formed, as an example, of a staggered lattice having 100,um of pin diameter and 400 /~m of alignment pitch. Figure 10 shows tWQ kinds of coated wire materials 10 and 11 having different insulating coating thicknesses for use in the production of the inventive micropin array. The coated wire materials 10 and 11 have a core 1, i.e., micropin 1 composed, for example, of a single copper wire which is coated by either of thicker and thinner polyimide resins 2 and 3.
The coated wire materials 10 has 400 ,~lm of diameter, and the other coated wire material 11 has 164,um of diameter. Since the copper core has 100 ,um of diameter, the thicker polyimide coating 2 has 150 ,um of thickness, and the 1C other thinner polyimide coating 3 has 32 ,um of thickness. As illustrated in Figure 11, the core diameter and the coating thickness are determined according to a pin diameter of the objective micropin array and the alignment pitch C of the micropins. Namely, the diameter a of the coated wire material 10 is set identical to the pitch C of the micropin array, and the diameter b of theother coated wire material 11 is calculated accordingly.
Referring to Figure 12, the coated wire materials 10 and 11 are alternately aligned with one another. More specifically, referring to Figure 13,a winding tool 13 having centrally a gap is utilized to wind therearound the coated wire materials 10 and 11 as indicated by the arrow such that the wire materials are regularly and closely aligned with one another. This winding tool 13 is provided with a recess having a V-shaped section of angle 90~. The wire materials are sequentially wound along the annular recess from the bottom to the top of the V-shaped recess.
Referring to Figure 14, which is a sectional view taken along the 2 5 line A-A' of Figure 13 , the wound wire materials 10 and 1 1 are fixed by means of an adhesive while being supported by the tool 13. In this case, the tool is coated provisionally on its surface with a release agent such that the bundle ofthe wire materials can be easily removed from the tool 13 after the curing of the adhesive. The adhesive should have sufficient electric reliability after curing and high fluidity effective to sufficiently flow into spacings between the coated wire materials.
021~
Referring to Figure 15, a micropin array 5 of a given length is selectively cut out from the fixed or molded bundle of the coated wire materialswound around the tool 13, that length being taken from the straight portion which extends over the gap provided in the tool 13. The cut micropin array 5 5 iS then polished. Alternatively, referring to Figure 16, when aligning the pins in a square lattice, instead of the coated wire material 11, an insulating string such as a polyimide balk string 14 having the same diameter as that of the coated wire material 11 is inserted among the adjacent coated wire materials 10.
Further in case of producing a micropin array in which the micropins are aligned10 at an angle of 60~ with respect to adjacent micropins, there are utilized coated wire materials 10 and 11 having the same diameter.
In addition, the electrically-insulating coating may be composed of a porous material such as foam of Teflon resin so as to reduce a net dielectric constant of the array matrix to thereby increase a signal transmission speed 15 through the micropins.
As described above, the inventive method of producing the micropin array is based on the technique that coated wire materials having desired natures and diameter are wound sequentially so as to align micropins at a given pitch. Thereafter, the bundle of the coated wire materials is molded 20 or impregnated by an adhesive, and then is cut to form a micropin array.
By such method, there can be produced an improved micropin array having a high aspect ratio, i.e., pin length/pin diameter ratio more than 20, which could not be realized by the typical mechanical working of pin such as stamping. Further, the thus produced micropin array can simplify later 2 5 assembling process and can improve the mechanical strength of the assembled micropins.
According to the present invention, wire materials having electrically-insulating coatings are successively superposed to align with one another to form a bundle of the coated wire materials. This bundle is fixed by 30 an adhesive and then is cut to produce a micropin array. The thus-produced 'Z15021~
micropin array features advantageously fine pin diameter, close pin alignment pitch and high aspect ratio.
Figure 5 is a cross-sectional view of the embodiment of Figure 4;
Figure 6 is a cross-sectional view of the embodiment of Figure 4 with solder material added thereto;
Figure 7 is a side elevational view showing an assembly of an IC
5 chip and a circuit substrate connected to each other by the micropin array of Figure 6;
Figure 8 is a perspective view of a section of a further embodiment of the micropin array;
Figure 9 is a perspective view of a section of a still further 10 embodiment of the micropin array;
Figure 10 illustrates examples of wire materials used in the embodiments of the micropin array;
Figure 11 illustrates an alignment pitch of the wire materials;
Figure 12 is a sectional view showing one step of producing the 15 micropin array using a support tool;
Figure 13 is a perspective view of the support tool of Figure 12;
Figure 14 is a sectional view showing another step of producing the micropin array; and, Figures 15 and 16 are perspective views showing different 20 embodiments of the micropin array.
Hereinafter, preferred embodiments of the micropin array will be described in detail with reference to the drawings. In Figure 1 a plurality of micropins 1 having a given diameter and a length are arranged in parallel to oneanother at a constant interval or pitch. Each micropin 1 is covered by an 2 5 electrically-insulating tubular coating 2. An adhesive 4 is provided to fillspacings or gaps among the insulating tubular coatings 2 such that the pluralityof micropins 1 are fixed to one another by the adhesive 4 to form a micropin array 5.
In this embodiment, all of the insulating tubular coatings 2 have the 30 same diameter, with the micropins being horizontally-aligned along a line extending between their sectional centers. Adjacent micropins are disposed in -- 21~0~1~
threes at respective vertices of an equilateral triangle, the sectional centers of the three adjacent micropins forming a lattice having a given pitch.
Figure 2 is a perspective view containing a section of another embodiment of the present invention, and Figure 3 is a view through a vertical 5 side section of Figure 2. In this embodiment, the array is comprised of horizontally-aligned rows and vertically-aligned columns of two interposed sets of micropins 1. Each micropin of one set is surrounded by four adjacent micropins of the other set such that the sectional center of each micropin of the one set is disposed in registration with the diagonal center of the four adjacent micropins of the other set. Each micropin of the one set, having a thinner insulating coating 3, is disposed in a spacing surrounded by thicker insulating coatings 2 of four adjacent micropins of the other set. The sectional centers ofthe respective micropins 1 are aligned to form a staggered lattice. In this embodiment, the micropin 1 is composed of a typical pin material such as Kovar 15 and copper alloy that is typically used in pin grid arrays. The micropin 1 has a 100 ,um diameter and a 2.0 mm length so that the micropins are aligned in a staggered lattice having a pitch of 400 ~m. This alignment pitch corresponds to a pad pitch of a LSI chip which is connected to an external circuit through the micropin array. The individual micropins 1 are covered by two kinds of the 2 o tubular electrically-insulating coatings 2 and 3, having different film thicknesses.
These electrically insulating coatings 2 and 3 are made of, for example, polyimide resin, and their film thickness is determined according to the alignment pitch of the micropins 1.
In this embodiment, the alignment pitch of the micropins is set to 25 400 ,um, hence the thicker electrically-insulating coating 2 has a thickness of 150 ,um as illustrated in Figure 11. This value is calculated according to the following formula: (pitch C - diameter of pin)/2, taking account of the diameterof the micropin 1. On the other hand, the thinner electrically-insulating coating 3 has a thickness of 32 llm. As illustrated in Figure 11, this value is calculated 30 according to the following formula: (pitch C x~2 - 2xdiameter of micropin -~15021~
2xthickness of electrically-insulating coating 2)/2, in order to align the micropins in the staggered lattice.
Returning to Figure 2, the respective electrically-insulating coatings 2 and 3 enclosing the micropins 1 are fixed together by means of adhesive 4.
This adhesive 4 is preferably composed of a specific material selected such thatthe adhesive shrinks slightly during the course of curing so as to closely fix the electrically insulating coatings 2 and 3 of the micropins 1 with each other in order to accurately set the alignment pitch solely by the dimension or thicknessof the electrically insulating coatings 2 and 3. Further, the adhesive 4 should have excellent durability in order to avoid aging change of the alignment pitch of the micropins 1. Moreover, the adhesive 4 should have a good thermal resistance effective to withstand a thermal treatment after the curing, during the course of assembling of the micropin array 5 with an LSI chip. In view of these needed characteristics, the adhesive may be composed, for example, of polyimide resin, maleimide resin or denatured epoxy resin.
Figure 4 is a perspective view containing a section showing arrangement of pads 6 formed on opposite ends of the micropin array 5 of Figures 2 and 3 for electrical connection, and Figure 5 is a vertical side section of Figure 4 when viewed from the side direction.
2 o The pad 6 is formed from a thin film composed of copper, gold and so on, by photolithographic technology such that the pad has a disc shape of 150 ,um diameter and 10 ,um thickness.
Referring to Figure 6, in preparation for coupling to LSI chip, the pads 6 disposed on the ends of the Figure 5 micropin array is clad with a soldermaterial 7 composed of Au-Sn eutectic alloy having composition of 80/20 wt%
and having a melting point of 280~C. The solder material 7 may be composed of other clad alloy such as gold-germanium solder (88/12 wt%) and gold-silicon alloy (94/6 wt%). In the general cladding process of a solder material to l/O
pins in a typical PGA, firstly a pellet of the Au-Sn alloy is formed such that its 3 o weight is calculated according to a header size of the pin. For example, if a pin header is formed in the size of 0.7 - 0.8 mm on the pin having diameter of 0.3 -- ~150213 0.5 mm, the Au-Sn pellet should have the weight of 0.7 - 1.0 mg. Then, the pellet is placed on the pin header to thereby carry out reflow processing.
However, in case of treatment of a small size pin, i.e., micropin, it might be diffficult in view of handling of micropins and tiny solder material pellets to clad accurately a tiny amount of Au-Sn alloy of about 0.1 mg calculated according to the micropin size onto the pin header without substantial variation. In view of this, cladding of Au-Sn solder material 7 over the micropin array 5 can be alternatively effected by metallization with using photolithographic technology in a manner similar to the formation of the pads 6 on the end surface of micropin array 5. Namely, a gold film and a tin film are applied over the pads 6 while controlling their film thickness to set weight ratio of Au/Sn = 80/20. Stated otherwise, gold metallization and tin metallization are carried out to set volume ratio of Au/Sn = 1.55. Then, the metallized gold and tin are subjected to reflowtreatment to form an eutectic alloy of Au-Sn to thereby clad the solder material7. In such case, if a single layer of the metallized gold is superposed on another single layer of the metallized tin, an eutectic reaction may occur locally only along a boundary therebetween, thereby failing to form uniform eutectic alloy composition in the solder material. In view of this, it might be preferable to repeatedly laminate alternately thin films of gold and tin to form a multi-layer structure which is then subjected to the reflow process. In such case, the gold thin film is metallized at a thickness of, for example, 1 ,um, and the tin thin film is metallized at a thickness of 0.7 ,um.
Figure 7 shows a complete assembly in which an LSI chip 8 is mounted on a substrate 9 using the thus-produced micropin array 5.
Figures 8 and 9 show modified micropin arrays in which the respective micropins 1 are surrounded by the electrically-insulating tubular coatings 2 and 3 composed of a porous material such as foam of Teflon resin.
Using the porous insulating coatings can reduce a net dielectric constant to increase a signal transmission speed through the micrapin array.
Hereinafter, the description is given for the method of producing the inventive micropin array with reference to the drawings, in which the array - ~15021~
is formed, as an example, of a staggered lattice having 100,um of pin diameter and 400 /~m of alignment pitch. Figure 10 shows tWQ kinds of coated wire materials 10 and 11 having different insulating coating thicknesses for use in the production of the inventive micropin array. The coated wire materials 10 and 11 have a core 1, i.e., micropin 1 composed, for example, of a single copper wire which is coated by either of thicker and thinner polyimide resins 2 and 3.
The coated wire materials 10 has 400 ,~lm of diameter, and the other coated wire material 11 has 164,um of diameter. Since the copper core has 100 ,um of diameter, the thicker polyimide coating 2 has 150 ,um of thickness, and the 1C other thinner polyimide coating 3 has 32 ,um of thickness. As illustrated in Figure 11, the core diameter and the coating thickness are determined according to a pin diameter of the objective micropin array and the alignment pitch C of the micropins. Namely, the diameter a of the coated wire material 10 is set identical to the pitch C of the micropin array, and the diameter b of theother coated wire material 11 is calculated accordingly.
Referring to Figure 12, the coated wire materials 10 and 11 are alternately aligned with one another. More specifically, referring to Figure 13,a winding tool 13 having centrally a gap is utilized to wind therearound the coated wire materials 10 and 11 as indicated by the arrow such that the wire materials are regularly and closely aligned with one another. This winding tool 13 is provided with a recess having a V-shaped section of angle 90~. The wire materials are sequentially wound along the annular recess from the bottom to the top of the V-shaped recess.
Referring to Figure 14, which is a sectional view taken along the 2 5 line A-A' of Figure 13 , the wound wire materials 10 and 1 1 are fixed by means of an adhesive while being supported by the tool 13. In this case, the tool is coated provisionally on its surface with a release agent such that the bundle ofthe wire materials can be easily removed from the tool 13 after the curing of the adhesive. The adhesive should have sufficient electric reliability after curing and high fluidity effective to sufficiently flow into spacings between the coated wire materials.
021~
Referring to Figure 15, a micropin array 5 of a given length is selectively cut out from the fixed or molded bundle of the coated wire materialswound around the tool 13, that length being taken from the straight portion which extends over the gap provided in the tool 13. The cut micropin array 5 5 iS then polished. Alternatively, referring to Figure 16, when aligning the pins in a square lattice, instead of the coated wire material 11, an insulating string such as a polyimide balk string 14 having the same diameter as that of the coated wire material 11 is inserted among the adjacent coated wire materials 10.
Further in case of producing a micropin array in which the micropins are aligned10 at an angle of 60~ with respect to adjacent micropins, there are utilized coated wire materials 10 and 11 having the same diameter.
In addition, the electrically-insulating coating may be composed of a porous material such as foam of Teflon resin so as to reduce a net dielectric constant of the array matrix to thereby increase a signal transmission speed 15 through the micropins.
As described above, the inventive method of producing the micropin array is based on the technique that coated wire materials having desired natures and diameter are wound sequentially so as to align micropins at a given pitch. Thereafter, the bundle of the coated wire materials is molded 20 or impregnated by an adhesive, and then is cut to form a micropin array.
By such method, there can be produced an improved micropin array having a high aspect ratio, i.e., pin length/pin diameter ratio more than 20, which could not be realized by the typical mechanical working of pin such as stamping. Further, the thus produced micropin array can simplify later 2 5 assembling process and can improve the mechanical strength of the assembled micropins.
According to the present invention, wire materials having electrically-insulating coatings are successively superposed to align with one another to form a bundle of the coated wire materials. This bundle is fixed by 30 an adhesive and then is cut to produce a micropin array. The thus-produced 'Z15021~
micropin array features advantageously fine pin diameter, close pin alignment pitch and high aspect ratio.
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method for connection of a micropin array of the type that includes:
a plurality of micropins arranged parallel to one another;
an insulating coating provided to cover each of the micropins, the insulating coating being composed of a porous material and, an adhesive provided to fill gaps between the micropins covered with the insulating coatings;
wherein the micropins are positioned such that the center points of the cross-sections of three adjacent micropins form vertices of an equilateral triangle;
the method comprising the steps of:
providing a pad on a surface of each micropin of the micropin array;
alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure; and, subjecting the multilayer structure to reflow treatment.
a plurality of micropins arranged parallel to one another;
an insulating coating provided to cover each of the micropins, the insulating coating being composed of a porous material and, an adhesive provided to fill gaps between the micropins covered with the insulating coatings;
wherein the micropins are positioned such that the center points of the cross-sections of three adjacent micropins form vertices of an equilateral triangle;
the method comprising the steps of:
providing a pad on a surface of each micropin of the micropin array;
alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure; and, subjecting the multilayer structure to reflow treatment.
2. A method for connection of a micropin array of the type that comprises:
a first plurality of micropins arranged in rows and columns at a predetermined pitch and parallel to one another;
a first insulating coating provided to cover each of the first plurality of micropins;
a second plurality of micropins positioned such that one of the second plurality of micropins is at the center point of a square defined by fouradjacent micropins of the first plurality of micropins arranged in rows and columns;
a second insulating coating provided to cover each of the second plurality of micropins; and, an adhesive provided to fill gaps between the first and second pluralities of micropins covered with the first and second insulating coatings;
wherein at least one of the first and second insulating coatings is composed of a porous material;
the method comprising the steps of:
providing a pad on a surface of each micropin of the micropin array;
alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure; and, subjecting the multilayer structure to reflow treatment.
a first plurality of micropins arranged in rows and columns at a predetermined pitch and parallel to one another;
a first insulating coating provided to cover each of the first plurality of micropins;
a second plurality of micropins positioned such that one of the second plurality of micropins is at the center point of a square defined by fouradjacent micropins of the first plurality of micropins arranged in rows and columns;
a second insulating coating provided to cover each of the second plurality of micropins; and, an adhesive provided to fill gaps between the first and second pluralities of micropins covered with the first and second insulating coatings;
wherein at least one of the first and second insulating coatings is composed of a porous material;
the method comprising the steps of:
providing a pad on a surface of each micropin of the micropin array;
alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure; and, subjecting the multilayer structure to reflow treatment.
3. A method for connection of a micropin array of the type that comprises:
a first plurality of micropins arranged in rows and columns at a predetermined pitch and parallel to one another;
a first insulating coating provided to cover each of the first plurality of micropins;
a second plurality of micropins positioned such that one of the second plurality of micropins is at the center point of a square defined by fouradjacent micropins of the first plurality of micropins arranged in rows and columns;
a second insulating coating provided to cover each of the second plurality of micropins; and, an adhesive provided to fill gaps between the first and second pluralities of micropins covered with the first and second insulating coatings;
wherein at least one of the first and second insulating coatings is composed of a porous material;
wherein the first insulating coating has a thickness T1 calculated using the following equation:
T1 = (C- R1)/2 where C represents the pitch of the first plurality of micropins, and R1 represents the diameter of the first plurality of micropins;
and wherein the second insulating coating has a thickness T2 calculated using the following equation:
T2 = {~ 2 C - (R1 + R2 + 2T1) }/2 where C, R1 and T, have the above-mentioned meanings, and R2 represents the diameter of the second plurality of micropins;
the method comprising the steps of:
providing a pad on a surface of each micropin of the micropin array;
alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure; and, subjecting the multilayer structure to reflow treatment.
a first plurality of micropins arranged in rows and columns at a predetermined pitch and parallel to one another;
a first insulating coating provided to cover each of the first plurality of micropins;
a second plurality of micropins positioned such that one of the second plurality of micropins is at the center point of a square defined by fouradjacent micropins of the first plurality of micropins arranged in rows and columns;
a second insulating coating provided to cover each of the second plurality of micropins; and, an adhesive provided to fill gaps between the first and second pluralities of micropins covered with the first and second insulating coatings;
wherein at least one of the first and second insulating coatings is composed of a porous material;
wherein the first insulating coating has a thickness T1 calculated using the following equation:
T1 = (C- R1)/2 where C represents the pitch of the first plurality of micropins, and R1 represents the diameter of the first plurality of micropins;
and wherein the second insulating coating has a thickness T2 calculated using the following equation:
T2 = {~ 2 C - (R1 + R2 + 2T1) }/2 where C, R1 and T, have the above-mentioned meanings, and R2 represents the diameter of the second plurality of micropins;
the method comprising the steps of:
providing a pad on a surface of each micropin of the micropin array;
alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure; and, subjecting the multilayer structure to reflow treatment.
4. A method for connection of a micropin array of the type that comprises:
a first plurality of micropins arranged in rows and columns at a predetermined pitch and parallel to one another;
a first insulating coating provided to cover each of the first plurality of micropins;
a second plurality of micropins positioned such that one of the second plurality of micropins is at the center point of a square defined by fouradjacent micropins of the first plurality of micropins arranged in rows and columns;
a second insulating coating provided to cover each of the second plurality of micropins; and, an adhesive provided to fill gaps between the first and second pluralities of micropins covered with the first and second insulating coatings;
wherein at least one of the first and second insulating coatings is composed of a porous material;
wherein the first insulating coating has a thickness T, calculated using the following equation:
T1 = (C- R)/2 where C represents the pitch of the first plurality of micropins, and R represents the diameter of both the first and second pluralities of micropins;and wherein the second insulating coating has a thickness T2 calculated using the following equation:
T2 = {~ 2 C - 2(R + T1) }/2 where C, R and T, have the above-mentioned meanings;
the method comprising the steps of:
providing a pad on a surface of each micropin of the micropin array;
alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure; and, subjecting the multilayer structure to reflow treatment.
a first plurality of micropins arranged in rows and columns at a predetermined pitch and parallel to one another;
a first insulating coating provided to cover each of the first plurality of micropins;
a second plurality of micropins positioned such that one of the second plurality of micropins is at the center point of a square defined by fouradjacent micropins of the first plurality of micropins arranged in rows and columns;
a second insulating coating provided to cover each of the second plurality of micropins; and, an adhesive provided to fill gaps between the first and second pluralities of micropins covered with the first and second insulating coatings;
wherein at least one of the first and second insulating coatings is composed of a porous material;
wherein the first insulating coating has a thickness T, calculated using the following equation:
T1 = (C- R)/2 where C represents the pitch of the first plurality of micropins, and R represents the diameter of both the first and second pluralities of micropins;and wherein the second insulating coating has a thickness T2 calculated using the following equation:
T2 = {~ 2 C - 2(R + T1) }/2 where C, R and T, have the above-mentioned meanings;
the method comprising the steps of:
providing a pad on a surface of each micropin of the micropin array;
alternately laminating thin films of gold and a member selected from the group consisting of tin, germanium and silicon on each pad to form a multilayer structure; and, subjecting the multilayer structure to reflow treatment.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP202936/1990 | 1990-07-30 | ||
| JP2202936A JP2536676B2 (en) | 1990-07-30 | 1990-07-30 | Micro pin assembly and manufacturing method thereof |
| CA002048170A CA2048170C (en) | 1990-07-30 | 1991-07-30 | Micropin array and production method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002048170A Division CA2048170C (en) | 1990-07-30 | 1991-07-30 | Micropin array and production method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2150219A1 CA2150219A1 (en) | 1992-01-31 |
| CA2150219C true CA2150219C (en) | 1998-05-26 |
Family
ID=25674713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002150219A Expired - Fee Related CA2150219C (en) | 1990-07-30 | 1991-07-30 | Micropin array and production method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2150219C (en) |
-
1991
- 1991-07-30 CA CA002150219A patent/CA2150219C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2150219A1 (en) | 1992-01-31 |
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