CA2140172A1

CA2140172A1 - Aluminum-palladium alloy for initiation of electroless plating

Info

Publication number: CA2140172A1
Application number: CA002140172A
Authority: CA
Inventors: Mark D. Kellam
Original assignee: Astarix Inc
Current assignee: Astarix Inc
Priority date: 1995-01-13
Filing date: 1995-01-13
Publication date: 1996-07-14

Abstract

Thin layers of aluminum (13) and palladium (12) are deposited and annealed to produce aluminum-palladium alloy (14). The surface of the alloy (14) is exposed and treated with an aluminum etchant to produce a catalytic surface (15). The catalytic surface is used for electroless plating of nickel, providing excellent plating uniformity and adhesion, as well as a reduced plating induction time. Several variants of the basic method are possible.

Description

7~
Al ~ P~ m Alloy For Tnifi lh~n Of Elecfroless Plafing Field of the Invention The present invention relates to electroless plating and more particularly to a catalytically active "seed" layer for the initiation of electroless plating. It also relates to the formation of high-resoluvion conductive wiring paHerns on c~ . .. and advanced packaging substrates.
Baclcg~ound of the Invention Eiectroless plating is a method used to deposit a thin film or a layer of some material on a substrate. The principal step is the immersion of the substrate in a plating bath containing ions of the material to be deposited, causing some of these ions to precipitate at the substrate's surface.
Unlike ~ v~loLil~ methods, electroless plating does not require an externally applied electric field to facilitate the ion deposition process. The electroless plating may be selective, i.e., the deposition may occur only at locations that exhibit appropriate el~ v~ Ol properties. For example, the ions may be deposited mainly on those portions of the substrate that are made of a material identical (or exhibiting affinity~ to the material being deposited. Another of many possibilities is that portions of the substrate may be treated or activated with a catalyst to cause the ion deposition to occur at a rapid rate. The material or catalyst present in the selected areas before the deposition is sometimes referred to as Useed material" or seed layer". The ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is referred to as the "plating process selectivity". The deposition rate may also depend on the physical .1:. c of the activated areas, e.g, their sizes, aspect ratios, and distances separating them.
If the thickness of the material deposited in various locations at the substrate is similar, the plating process is said to be uniform. For many ~ ' ' 5, it is crucial that the plating process be uniform, that it exhibit high selectivity, and that the deposited film strongly adheres to the substrate. The adhesion is commonly measured with a "scotch tape" test, whene adhesion is deemed acceptable if a piece of a ''scvtch ta,oe" can be pressed onto the plated sufface and lifted off without desvroying any plated features. One of the ways to increase the adhesion is to subject the plated artifact to an annealing process. The conditions or process parameters such as the I , ~, ion ~ v~ . in the plating path, and duration of the bath, which provide desirable uniformity, selectivity, and some physical properties of the deposited layer usually fail within certain ranges, the ..- ..1 ~:.... of which is called a "f^rl~ ^gi~l process window". To ensure the ~ bllily and consistency of the plating process, it is desirable that vhe process window be as large as possible.
Electroless plating of solid metals from a solution containing metal ions onto a catalytically active surface has been widely used in the printed circuit board industry for production of wiring layers and inter-layer (via~ rnnn^ctinnc More recently, this body of knowledge has been applied to producing metal .v.,,.~l films in the integrated circuit (IC~ industry. The electroless plating I

. .

-. 214~172 technique has several advantages over other well known m~tal deposition techniques such as sputtering and evaporation. One advantage is that the electroless plating process uses materials and capital equipment that are inexpensive compared to the other methods. Another advantage is that the technique deposits films only in selected, catalytically active regions. This property of selective growth allows the user to reduce th~ number of lithographic patterning and etching steps used to define the regions to be covered by the deposited metal. It also facilitates dense pattetning of materials such as copper, that are difficult to etch "~i.ùlly . Yet another advantage is that the growth rate of the deposited metal is relatively i ~ of the angles or relative heights of lo~,o~ ,lu. features on the substrate being plated. This prop~rty enables deposition into f~atures having high aspect ratios, such as deep via holes on multi-layer circuit boards, that could not be uniformly covered by the '1ine of sight" deposition techniques such as sputtering and evaporation.
The most commonly published use of electroless plating in the integrated circuit industry is for filling contact or via holes. The traditional contact is a hole, patterned and etched in a dielectric film placed on top of a conducting film so that the surface of the conducting film is exposed within the hole. An upper level of conductor, patterned over the contact hole, makes a physical and electrical contact with the lower conductor in the contact region. Electroless plating has b~en used to grow metal selectively onto the surface of the lower conductor that is exposed in the contact hole.
This produces a metallic "plug" which electrically oouples the upper conductor to the lower conductor. The "plug" is plated until its top surfaoe substantially ooincides with the top surface of the dielectric, and the resulting planarity of the structure prevents problems that might occur in the subsequent processing if tu~ .. variations were present in the vicinity of the contact region.
Although electroless plating-based processes, such as contact-hole filling, offer many advantages to the process designer, the technique has only found limited acceptance within the IC
l~ community. Although the technique appears to be relatively simple, the chemical reactions occurring at the plated surface can be complex. Some of the factors inhibiting the wider application of el~ctrol~ss plating are the difficulties in controlling the plating procesS and in obtaining uniform plating thickness on the entire substrate, as well as the sensitivity to exhibited by the process. Many of these problems are related to the previously known surface activation techniques, i.e., methods used to render the plated surface catalytically active.
The present invention teaches a new surface preparation technique that provides a more active surface on which to plate, thereby improving the latitude of the plating procesS and the uniformity of the plated materials.
Many surface activation techniques have boen r~ported in both the patent and scientific literature. Frequently, these techniques ~re designed for plating a specific material onto a specific substrate material, and rely on certain prop~rties of these materials.
The most common applications of electroless plating to integrated circui t . ~ - - f~ I ; - ~g oomprise plating of nickel, cobalt, palladium, or copper onto one of two types of substrate surfaces.
The first type of substrate surface comprises conductive regions of substrates that are generally formed of silicon, aluminum, or aluminum alloys. The second type of substrate comprises a non-oonductor such as silicon dioxide or a polymeric insulator. The reported surface activation techniques 214~i 72 applied to these substrates usually fall into one of three categorles: (I) catalyst film deposition by evaporation or sputtering (2) catalyst film drposition by ~ al surface ..-r,l r: ,-I;--A, and (3) catalytic film deposition from â colloidal suspr!nslon.
Palladium ând platinum are frequently used âS catalytic surface activators in electroless plating memods. Catalytic films of pallâdium or platinum for subsrquent electroless plating cân be readily deposited by evâporation or sputtering techniques (Harada et al., J. El~.l.~,.l.~ll.. Soc., Nov.
198rj, p. 2428). The films deposited with these techniques can be pattr~rned by well known lithr,~rhir techniques, e.g., subtractive etching or liftoff. r~arge features and/or dense patterns of small features are relatively easy to plate with this method. US Pat. No. 4,182,781 teaches a method to fabricate elevated metal bumps on aluminum bonding pads. rn accordance wim this method, a palladium film is deposited and patterned on me upper surface of an aluminum wiring layer on an integrated circuit. An insulating layer is deposited over the surface of m,.~ substrate and patterned to provide holes exposing the palladium film surface in regions where elevated metal bumps are desrred. The substrate is then immrrsed in an electroless plating bath, resulting in a deposition of metal features that are self-aligned to the apertures opcned in the insulating film.
While mis technique is effective for fabricating the relatively large features discussed in the patent, me palladium film disclosr~d appears not to provide sufficient catalytic activity to enâble plating of the small features commonly fabricated in modern integrated circuit . . - - ~ r~ g particularly if those small features are located far away from other plated features.
It has been reported that the cablytic activity of pâlladium films deposited by evaporation and sputtering is lower than that of palladium films deposited by other techniques, for example ~I~I.~,.I.t:llu~..lly deposited films. This low activity has a significant detrimental impact on the uniformity of structures formed by this process and on the resulting yield. (Svendsen, et al., J
El~ll~lU-III;~.II. SOC7 Nov. 1983, p 2252, and Osaka e~ al., J. Electrochem. Soc., Sept. 1983, p. 2081) Features that are small or separated with large distances from other features are si~ ;&~.--lly more difficult to plate. These size-dependent and proximity-dependent effects are often related to the presence of stabilizing agents (stabilizers) in the plating solutions. Stabilizers are added to most ~'.IIIUI~ available plating solutions to prevent the ~ of the plating bath. Generally, the stabilizers reduce or even prevent the auto-catalytic plating reaction from occurring on small particles mat may be present in the bath. The presence of such particles may result from a of the plating bath with the airbome dust. The stabilizing agents also exert a significant and beneficial impact on the electrical and mechanical properties of the deposited film, although the ' - for this action are not always clearly . ' J It is intuitively clear, however, that any mr!chanism that prevents undesirable auto-catalytic plating on small particles in the bath may also impede the desirable plating of small, isolated features present on me substrate. Plating of small features may be enhanced by modifying the bath ...... I~;li.. orprooessconditions.Forinstance,theabilitytoplatesub-micromr!terfeaturescanbe improved by raising the plating bath l~ IrAlul c:, or by reducing the amount of the stabilizing agents in the bath. This , .,v~ l is obtained the prioe of a reduoed plating selectivity and reduced bath stability.

The plating non-unifomlity and process selectivity also depend on the detailed history of the catalytic surface. Subjecting this surface to any post-patteming clean-up processes or exposing it to air before plating reduce the ability to uniformly plate the desired features. US Pat. No. 5,127,986 discloses the placement of a protective chromium film, that is deposited over a palladium catalyst film. The chromium has two beneficial effects: (I) the adhesion of the dielectric offer the areas comprising the seed metal covered with the catalyst and chromium films is increased compared to the adhesion of the same dielectric to the seed metal covered by the cahlyst film only, and e) the chromium film shelters the palladlum catalyst from the adverse effects of some processes to which the substrate is sub~ected before plating. The chromium film can be removed by etching it '` '~ prior to the pladng process, thus reducing the exposure of the catalyst to oxidation or other proces~induced ~ gr~ nn Direc h:UII I~Ual i~UII~ of this technique to those using .1..11. ' ' "~, deposited catalysts, and to the present invention, ~ that the use of a protective layer only provides a fresh surface upon which to plate. The catalytic activity of this surface is similar to a freshly deposited palladium film and is s~..iG.l.11~7 lower than that provided by other techniques, including the present invention.
A wide range of ele llu.l....-l~al surface ~ ~n~l;r;~ Al --- techniques to enable the catalytic plating on metallic and dielectric materials have been disclosed. As disclosed in US Pat. No.
5,169,680, aluminum films used in VLSI circuits can be rendered catalytically active by electroless plating of a seed layer of palladium from a bath containing a dilute aqueous solution of PdC12 and HCl. Typically, the pre-existing aluminum oxide is removed by a short immersion in a dilute HF
solution prior to the palladium activation. The degree of activation achieved by this technique depends strongly on the processing history of the aluminum surface, the . . ~ of the activator l - . ' s, the t~ , and duration of the exposure of the aluminum surface to the activator. This method can achieve very high levels of activation, but suffers from a very small aprocess windowa. If the exposure to the activator solution is too brief, thc insufficient surface activation and the resulting plating non-unifommity will occur. If the exposure to the activator solution is too long, the plated metal will exhibit poor adhesion. While this process has been ~' ~ ' ' ' to work, the d. v .lulu. ~ of a stable, ~,. udu.il,l~ l lU~ Ul il g i ...l )l.-....'' ' l ' ~ ;.~.. is difficult. Using a similar technique, US Pat. Nos. 4,122,215 and 4,125,648 teach a similar method of activating aluminum surfaces by contact of the aluminum with a solution containing nickel ions.
US Pat No. 4,372,996 illustrates another method of activating aluminum surfaces using the electroless deposition of zinc. The zinc is then used as a catalytic seed material for subsequent plating of the nickel film. This process is commonly refereed to as azincating", and is extremely effective for activating larger dimension patterns but suffers from a reduced process window in the presence of features with small dimensions, such as used in many integrated circuits. The process exhibits a tradeoff between activation and adheslon similar to the one discussed above for ,)f" " based activation.
Several techniques have been disclosed that use alloys of palladium to seed electroless plating. Copper deposition from a thermally grown Qlm of palladium silicide was discussed in Mak, et. al7 Appl. Phys. Letters, 59, Dec. lg91. US Pat. No. 5,098,526 discloses selective plating in regions 214~172 where a reaction between a palladium film and a dielectric film deposited over it is induced with a oh ~ -~ Iaser- US Pat- No- 4,746,375 traches the method of activating refractory mehls by a high-le~ elaLule exposure to a carburizing atmosph~re.
A significant amount of prior art is directed toward the,.~ r;. ,~ ", of dielectric surfaces to enable electroless plating onto the modified material. US Pat. Nos. 3650913, 3976816, 4132832, 4220678, 4258087, 4261747, 4278712, 4282271, 4317846, 4318940, 4323594, and 4863758 all discuss variants of the widely known method consisting of exposure of a non conducting surface to a medium containing dispersed catalytic particles. Many of these patents teach various methods of making and using solutions containing tin and palladium ions or colloidal dispersions of tin-palladium particles. US Pat. No. 4,042,730 teaches thê activation of dielectric surfaces by sequential exposure to tin- and palladium containing baths. US Pat. No. 5,108,553 activates a dielectric surface by contact to a dispersion of carbon particles and US Pat. No. 4,910,049 uses ' particles that are laminated onto the dielectric. Yet another approach involves chemical treatment of dielectric polymer surfaces to render them catalytically active. This approach is taken by the authors of US
Pat. Nos. 4078096, 4112139, 4910045, 5135779, 51659il, and 5160600. US Pat. No. 5,183,795 discloses the novel technique for the patterned activation of silicon dioxide that has been implanted with catalytically active ions.
Summar~ Of The Invention As can be seen from the preceding discussion, surface activation methods practiced heretofore do not provide " '~, high surface activity, uniformity of plating across a broad spectrum of pattern densities and sizes, and strong adhesion to the plat~d film. These difficulties have historically limited the, ,- of electroless plating in int~grated circuit ~ urcl~UIillo-It is therefore an obj~ct of the invention to provide a catalytic "seed" layer upon which metal may be selectively deposited by electroless plating.
It is another object of the invention that the surface of the catalytic "sred" layer present an extremely active surface to an electroless plating solution, so that small, isolated regions of the A'seed" layer are plated at a rate of the same ord~r as the plating rate observed in large regions or denæ arrays of small regions.
It is yet another obj~ct of the invention to provide a catalytic "seed" layer that exhibits good adhesion between the seed layer and the substrate, and between th~ seed layer and the metal film selectively deposited on its surface.
According to the present invention, electrol~ss plating of nickel and other selected metals can be selectively activated on a film deposited by evaporation or sputtering, comprising an alloy of aluminum and palladium placed above a metallic adh~sion ~..1.~ .. ~..,~..l layer. The aluminum-palladium alloy is treated just prior to plating by an aluminum etchant that renders the surface of the alloy extremely active. Films grown by electroless plating onto this "se~d" layer are free of the non-uniformity associated with pattrrn density and siæ, and exhibit excellent adhesion between the substrate, the seed film, and the plated layer.

Brief D~ liu.. Of The Drawings Fig. IA shows a cross section view of a eatalyst film stack as deFosited on the substrate.
Fig. ~B illustrates the formation of an r' ' palladium alloy after annealing thecatalyst staek.
Frlg. IC illustrates the removal of the un-redeted aluminum (whieh failed to form the alloy) from the staek surface, thus exposing the alloy.
fig. 2A shows a eross æct~on view of a eatalyst staek with palladium on the top surfaoe.
Fig. 2B illustrates the formation of an r' ' palladium alloy after annealing theeatalyst staek. In this ease the palladium is eompletely reacted.
fig. 2C illustrate the activation of the stack surface afler exposure to an aluminum etehant.
Fig 3 illustrates a method for llftoff patternlng of the eatalyst staek.
Fig. 4 shows a eross section of the strueture in Fig. 3 after annealing etehin& and platlng on the exposed eatalyst.
Fi& 5 shows a eross æction of a struetune that uses the invention to form planarized via "plugs" by electroless plating onto the Al-Pd alloy.
Fig. 6 illustrates a multi-layer ' . strueture that is appropriate for applieation of a "Top Level V}a"
Fig. 7 shows a eross æction of a top Ievel via connection between an upper and lower level of wirlng. The plated metal strap is seeded using the Al-Pd eatalyst.
Detailed D~ Of The Present Inventiûn Aecording to the preænt Invention, a "æed" film for the subæquent electroless plating is formed by first fabrieating a thin layer of F~ " r' ' alloy, and then exposing the alloy surfaee to an alumlnum etehant. The plating proeess is easily initiated on this surfaee aeross a wide range of feature sizes and pattern densities. Furthermore, the catalytic surface provides excellent adhesion of the plated films.
Paliadium and aluminum readily form a range of inter-mehllic alloy compounds including solid solutions of about 2% palladium in aluminum to about 20% aluminum in palladium. In addition to the solid solutions a number of comFounds may be formed including PdA13, Pd2A13, PdAI, and Pd2AI, Alumlnum, palladium, and their alloys may be deposited onto a substrate by a number of well known thln film techniques, including vacuum evaporation and sputtering. The deposited materials forming the catalytic surfaces in aecordanee with the preænt invention may be patterned on the substrate using methods well known in the field of ,.. ~.. ,. ,. I . ,. l.. ~ .. ~- l, .. ;
Some of the applieable methods are l-l,ol--l;ll ~ ,l,;, patterning and etehing, and Yiftofr techniques. The aluminum-palladlum alloy, whieh is to serve as a seed layer for the subsequent electroless plating, may be formed by a number of techniques. One posslble method is to deposit the alloy by ' ' evaporation from two separate, heated crueibles, one containlng aluminum and the other containing palladium. Another possible method is sputtering from a metal target formed of 2143~72 the ' palladium alloy. Yet another method is ' sputtering from two separate targets, each containing one of the constituent metals. While these methods are widely known in the art and practiced in the deposition of some alloys, they are difficult to practice for the palladium-aluminum alloy for the purposes of the precent invention. Variations in relative c~ ~rnr~inn rates and differences in the sputter yield of the , can lead to variations in the final alloy , resulting in differ~nt ~ - of the alloy in different locations on the substrate, and in decreased repeatability of the process. The best currendy , ' ' method of deposition of the ' palladium alloy is the sequential deposition of each component, either by .... or sputtering, followed by a ther nal annealing treatment that causes formation of the alloy by the inter-diffusion of the component metals. This process produces a variable ...... ~ of the alloy across the film thickness. However, by controlling the thicknesses of the initial palladium and aluminum films, as well as the time and Ic~ Ialulc of the annealing stage, highly C results can be achieved. fig. IA shows the catalyst film stack created by c~"~depositing a titanium adhesion layer 11, a palladium layer 12 and an aluminum layer 13 onto a substrate 10. Fig. IB shows the formation of an . ' palladium alloy layer 14 by annealing the substrate. The titanium layer is effective in providing good adhesion of the palladium Rlm to the substrate and does not play a role in the catalytic activity of the surface .
Usually, the term activity" is used in a qualitative manner, to compare the ease of plating under various ~ U~DIa..~t:s. For the purposes of this disclosure, the term "relative surface activation" is defined qualitatively by the ability of a surface to se~d the plating process on small (i e., haYing dimensions not exceeding 5 ..u., ul--el~- ,) feature~c that are placed some distance from any other features. To make the concept of the surface activation;.. ~I.. 1~.. I of the relative "activity" of the plating bath, the plating process used to evaluate the surface activation must ensure that small, isolated, active features are plated without deposition of the plating material in undesired areas. Normally, the loss of plating selectivity in the bath generally occurs first in regions that are densely covered with small active features, hence the surface activity tests should be conducted on substrates having both densely and sparsely spaced small features. Normally, a delay occurs between the time of the contact of the substrate with the plating solution and the onset of plating, as evidenced by the evolution of hydrogen bubbles from Its surface. A strong correlation exists between this delay time and the relative activity of the surface, however, this delay does not distinguish between the activity of the surface and the activity of the plating bath.
The catalytic activity of the alloy requires an exposure of the alloy surface to an aluminum etchant prior to plating. The etchant is chosen to have a higher etch rate of aluminum than that of palladium. It should be apparent to a person skdlled in the art that many etching methods are applicable here, for example wet etching in HCI or H3PO4. Cenerally, most of appropriate etchants will exhibit a slow etch rate of the alloy, thus increasing the l~ In~ I window of the process.
fig. 1C shows the substrate after its exposure to the aluminum etchant and creation of the enhanced-activity catalytic surhce 15. After the alloy surface is etched, rinsed and dried, the substrate is contacted with an electroless plating solution that plates metal onto the activated catalyst.

21~0172 While in the above describ~d preferred t .. ': the aluminum film is deposited on top of the palladium to form the initial stack, it should be clear to a person skilled in th~ art that an initial stack created by depositing palladium on top of aluminum could be used as well. Figs. 2A-C
show the formation of an ` ' ~ctivity cablytic surface in a structure where the deposition order of the palladium and aluminum films is reversed with respect to that discussed above. The reference numerals in Figs. 2A-C refer to the materials identical to those in Figs. IA-C. The titan~um film 11 in figs. 2A-C is optional, and present only if required to achieve good adhesion between the aluminum 13 and the substrate 10.
If the alternative stack structure of Fig. 2A is used, the ~ ui~ that the alloyed region be exposed to an aluminum etchant places some constraints on the subsequent processing. Note that in the above described preferred ~ ' " ' shown in fig. I A, any remaining aluminum 13 that did not form the F`'l- " ' alloy afler the anneal (Fig IB) will be removed during the aluminum etch. The aluminum 13 of Fig. IB is removed by the etchant until the alloy layer becomes exposed, after which etching of the alloy provides . ' ' activity surface 15 (Fig. IC) for plating. If the palladium is deposited after the aluminum as shown in fig. 2A, the currently preferred ~.. .1--~.1; . is to adjust the anneal time and lt ~ lu~ c to insure that the entire palladium film of the initial stack is convert~d to an aluminum alloy film 14 (Fig. 2B). Otherwiæ, any portions (not shown in Fig. 2B) of the palladium film 12 (fig 2A) that did not form the alloy and remained on the surface of alloy 14 would be difficult to remove. Due to the low chemical reactivity of palladium, most known methods applicable to palladium etching would quickly attack both the alloy and the aluminum as well. As shown in Fig. 2C, when the palladium is fully converted to an alloy, a contact with the aluminum etchants will produce an enhanced-activity catalytic surface 15 as in the previous case shown in Fig. IC
It should be apparent to a person skilled in the art that an em~rgence of etching methods capable of etching palladium faster than alurninum would enhance the applicability of the structure and process shown in Figs. 2A-C
Either of the structures and proc~sses discuss~d in connection with Figs. i A-C and 2A-C may have spec~fic advantages depending on the application. Examples of ~t~ ' " for each will be presented in a later section.
While several of the prior art techniques can create surface whose catalytic activities match that of the present invention, the adhes~on of the plated film to the substrate, r~sulting from these prior art techniques, is reduced as a tradeoff for the increased activity. The present invention produces films that will pass the traditional "scotch tape" adhesion test with and without subsequent ann~aling A series of ~~ comparing the ~c -rv-li~d--.~ of various activation techniques were performed. The results are ' in Table 1. The test pattern contained square via holes, I
micrometer wide in each direction. The pattern contained both the isolated holes and dense arrays of holes. This pattern was fabricated on a s~licon wafcr coated with a 100 nm thick layer of Plasma Enhanced Chemical Vapor Deposited (BECVD) silicon dioxide. The via pattern was reactive ion etched (RIE) and the resist undercut by a short exposure to buffered oxide etch (bOE). The deposited 21~172 catalyst series were then evapora~ed and lift~d off. The wet cablyst series test wafers were prepared by patterning a 0~ micrometer thick layer of aluminum on the surface of the oxide. Mckel plating was performed in an Allied Kelite Niklad 75X bath, operated at a pH of 6.2 and at 62 degrees C Details of the specific process steps for the Yarious wet activation steps may be found in the earlier listed prior art references. A wide range of process variations were explored for each type of process, producing s~lh~ f~ y similar results.
The applicant believes that one plausible explanation of the observed excellent adhesion of the plated material and increase in the catalytic activity of the plating surface in accordance to the present invention is as follows. When a palladium/aluminum alloy is etched by removing aluminum, a palladium-rich, i. . l~ irregular surfaoe is formed by the voids left after removing aluminum As aluminum atoms are removed, deep valleys form. At the bottoms of valleys, etching stops by eventually c .~.u. c, high - of palladium atoms. Palladium peaks that may be fully undercut by aluminum will float away as the aluminum is removed. Eventually, if the of palladium is sufficiently high, the aluminum etch is r clf ' -- C leaving an active catalytic surhoe of a complex shape formed mostly by palladium atoms which remain after removal of aluminum atoms. This surfaoe has peaks and valleys and other shapes not capable of exact description. It is a difficulty of language. It is a difficulty of n-ul~l.ol~,y. The result is a surface structure which cannot be precisely defined other than by th~ prooess by which it was formed. This "crumpled" surface might have large area, ther~by preventing the stabilizing agents from plating inhibition. The surface i- - - " ' ' may be also responsibl~ for good bonding of the plating material to the surface.
A detail~d process sequence is now presented for the ~ " ' . ' alloy catalyst used in the ~ in the last row of Table 1. The general method presented here will then be extended to describe several possible . r'' " of the present invention. It should be apparent to those skilled in the art of ~.. -i- .. l.. l.. fabrication that the thin film catalyst stacks can be patterned by a variety of methods, e.g. subtractive etching or liftoff. Whenever a liftoff process is compatible with the sp~cific application, it enables the patterning without the side effects associated with wet chemical etching. Therefore, liftoff is considered a preferred method for patterning catalytic surfaces in accordance with the present invention.
For the e,~,u, ' in Table 1, silicon substrates were prepared by depositing a 100 nm thick layer of a PECVD silicon dioxide. The substrates werc coated with a l,l,u~u,...~:~ivt:
resist, exposed to a light pattern using an optical stepper, and develop~d. The resist pattern was then transferred to the silicon dioxide film by anisotropic Reactive lon Etching (RIE). The wafers were exposed to a bri~f, low power RIE in oxyg~n to r~move any polymeric residues from the exposed silicon surface, and then wet-etched in dilute (50:1) Iyd.u[luu.;~ acid (H~ to und~rcut the resist edges by about 15 nm. This undercut provid~s a break in the deposited metal and enables the subsequent liftoff in a solvent. After rinsing and drying, the wafers were loaded into an evaporator with a wafer holder designed to provide planetary motion. After evacuating the air from the evaporation chamb~r, the wafers were coated with 10 nm titanium, followed by 10 nm palladium, then, finally, 20 nm aluminum. While plan~tary motion is not normally used with liftoff techniques, it provides better coverage of the vertical sides of the substrate's features with the catalytic film.
This improves the plating on any vertical features that are to be subjected to the subsequent electroless plating. If the thickness of the silicon dioxide film is greater than the thickness of the deposited Ti/Pd/AI stack, and the undercut angle of the resist is greater than about 10 degrees, the use of the planetary motion will not int~rfere with the ability to liftoff the deposited film. Fig. 3 shows a cross-section, at this point in the procrss, of one of the ~ub:~u~ llr plated features. The overhang of the resist 17 over the etched dielectric 16 causes a dia~ illu;~y in the deposited metal films of titanium 11, palladium 12, and aluminum 13. The metal deposited over the resist-covered regions was lifted off by immersion in an acetone bath with ultrasonic agitation. After the liftoff, the substrate was rinsed in isopropyl alcohol, rinsed in distilled wafer and finally dri~d.
The adhesion of palladium to substrate materials such as silicon dioxide, polyimide, or aluminum that has been even briefiy exposed to r ~ oxygen, is generally poor. The titanium, included in the film stack, is added as a buffer to improve the adhesion b~tween the palladium and the substrate. A wide range of materials, for example, chromium, or titanium-tungsten alloys can also be used for this purpose.
The wafers were then annealed on a hot plate to cause the inter-diffusion of the aluminum and palladium to occur. A series of isochronal anneals of I minute each, at ~ . ranging from 150 degrees C to 350 degrees C, all showed a sufficient inter-diffusion to facilitate the enhanced surface activation required for the plating. Control wafers which received no annealing exhibited a low surface activation level, similar to that of a freshly deposited palladium film. At t~ alu~
above 300 degrees C, a color change from white to tan in the Qlm surface indicated that the alloyed region, caused by inter-diffusion of the aluminum and palladium, had reached the surface. Anneals at higher ~ .a~ul~ or longer times appeared to be neither b~neficial or d~trimental for the subser~uent plating Just before the el~ctroless d~position, th~ wafers were exposed to the following pre-plating processes:
Step 1:
Bath A: 20seconds DIW 1000 ml BOE 5ml Step Z:
Distill~d water rinse 60 seconds Step 3:
Bath B: a~tJ.. "~i.l.al.-ly30seconds DIW 1000 ml Glacial Acetic Acid 15 ml HCI 5 ml Step 4:
Distilled water rinse 120seronds The BOE etchant in bath A is designed to remove the pre-existing (e.g., resulting fnom any exposures to . ' ' oxygen) oxide from the aluminum film surface. Alternately, this component can be added to bath B and bath A could be eliminated, however, a better uniformity of the subsequent plating was observed when using the two bath system. The duration of bath B depends on the thickness of the aluminum film, and on the anneal history of the substrate. When the aluminum that did not form the alloy is removed, the exposed alloy surface will darken in color. Continuing the bath for a short time (on the order of 10 seconds) after this color change is sufficient to fully activate the surface. Extending the bath duration past the color change to 2 minutes did not have a significant effect on the surface activation level. After a rinse cycle, the substrates are subjected to the electroless plating bath. As shown in Fig. 4, the plated nickel metal 19 grows only on the selectively activated regions of the substrate. Following the deposition of 0.5 ~llleL~lD of nickel, the substrates were rinsed and adhesion tests performed. Adhesion testing was repeated after annealing for 30 minutes at 400 degrees C in an inert atmosphere to insure that the annealing did not degrade the adhesion by oxidation or other chemical reaction. No adhesion failures were observed using this process.
The etchants disclosed in bath A and bath B are sample . ~ ....l .. ,~:l ;....~. chosen after a number of r ' ' involving other possible etchants- A number of successful bath .ul~ .l were discovered with roughly equivalent ~. r....- ~ in activating the catalyst. The etchants that were successful had two common properties. Fir$, som~ component of the etching bath should be effective in removal of aluminum oxide. This is important even in the case where the alloy is grown fmm an aluminum film diffusing through palladium to the surface. Surface analysis shows that the surface of these structures is covered primarily by aluminum oxide after even a brief exposure to: ' . ' ;~
oxygen. Second, the etchant should remove aluminum at a higher rate than palladium. Palladium etchants containing nitric acid were not as effective. The above properties by the etching baths used by the inventor should not be however construed as a limitation of the claimed invention and ane listed solely for the purposes of a complete description of a possible fabrication process of an : ' ' activity catalytic surface.
Theplatingbathusedinthee~,:lil.l~llkll~...l.o~ ..loftheinventionwasbasedona nickel-boron chemistry, commercially available as Niklad 75X from Allied Kelite. The enhanced activity of the surface produced by etching the aluminum-palladium alloy is thought to be due to the surface morphology of the palladium that remains after the etch treatment. Thus the invention should be effective in activating any of the electroless plating chemistries that can commonly be activated by palladium. These include nickel, copper, cobalt, palladium, and gold. ~ul~llc llllU-~:, surfaGeswithsimilarl.~l~,l.olG~ ,maybeproducedbyannealingandsubsequentetchofother compositeseedlayersanalogoustotheTi/Pd/Alhlmusedinthepreferred~.. l,o.l;.. ~.. l Two example .~ ' ' of the Al-Pd alloy catalyst to ~...;. . - -1 l. ..-related processes are given below. The first example is a method for producing planarized inter conductor vias filled with metal depositecl by electroless plating. Referring to fig. 5, which shows the final result of the process, a lower level of conductive wiring made on aluminum alloy conductor layer 113 is patterned over a substrate 110 that is covered with a first dielectric coating 111. In this case a Al-Pd alloy Il 21~172 layer 114 i9 i/~ul~U~ ~ inlo the top surface of a .u.~ metal layer and pattemed using the same photoresist masking layer as the one used to pattcm the wiring. An aluminum metal stack is produced by a sequential deposition of a titanium-tungsten barrier metal layer 112, an aluminum alloy conductor layer 113, and finally a 50 nm layer of palladium. The barrier metal is used to limit ' dirruD;o.. of the metal and the silicon substrate and may not required if the i~.t~.. ullllecl layer does not contact the silicon. The Qlm is pattemed by .u,~ ,I.u 1 - 1~ , ' y and reactiYe ion etching in a chlorine based chemistry. The film stack is annealed at 400 degrees C for 30 minutes, which is sufficient to diffuse the aluminum across the entire thickness of the palladium film, thus forming a surface layer of alloy 114. A second dielcctric 116 is deposited, pattemed and etched to provide vias that expose regions of the alloy surface. The exposed alloy surface is treated with the etchant process described in the last section, producing a catalytically active surface 115, and then exposed to an electroless plating bath until the via holes are Qlled with the deposited metal 117. A
second layer of metal 118 is deposited and pattemed over the dielectric surface, covering the via ~'plugs" to make contact to the lower metal level.
The second application uses a very thin deposited catalyst stack including an adhesion : ' Iayer. In this example, the aluminum film is placed over the palladium film, and, as previously mentioned, the alloy-forming anneal duration may be shorter, as it is not necessary to ensure that the entire top Qlm of aluminum is converted to a I " ' -' alloy. The structure described above is called a Top Level Via and is the subject of a co-pending patent application Serial Number 08/092,202 and entitled "Top Level Via Structure for rlu~;,al.. ;,~g Pre fabricated Multi-Level In~ u....~l," the ~ i aliull of which is ill~ultJula~i by reference herein.
A detailed description of the process for fabricating top level vias is given in the above described patent application, and is only briefly ~IIIIIIIIOI.~ here for the illustrative purposes. The top level via is a structural means for electrically connecting at least two previously I~ llura~ wires that may be formed on two separate levels of; . ,1 ~, .. " .~l For instance, Fig. 6 shows a cross-section of a ' 1, initially . ' structure where an upper level of wiring 118 crosses a lower level of wiring 113, the wiring levels separated from each other by an inter-conductor dielectric 116.
The lower level of wiring contains a barrier metal 112, and is isolated from the substrate 110 by a first dielectric 111. The barrier metal is used to limit J;rru~iull of the metal and the silicon substrate and is not required if the ;. ,~.. ~r~ I layer docs not contact the silicon. A top level via is formed by first opening an aperture in a ~l~olu~ ilive~ resist . The aperture overlaps a portion of both the upper and lower wires. The inter-layer dielectric is etched allisu~ ally through the hole in the resist, using an etchant that will not remove the upper conductor wire 118. Thus, the etch will remove the region of the second dielectric 116 that is exposed within the resist aperture but is not covered by the upper conductor 118. A catalyst layer comprising , "), deposited films of 20 nm Ti 20 nm rd, and 20 nm Al is deposited and lifted off. The substrate is then annealed to form an alloy of aluminum and palladium. Just before the plating process, thc wafers are exposed to aluminum etchants, as described in the previous scction, and then exposed to an electroless plating solution. The selective plating of mebl on the deposited Al-Pd catalyst film results in the structure 2l4al7~
shown in Fig. 7. The strap metal 121, plated on the active surface of the catalyst stack 120 provides a low-resistanoe connection between the two prc C^t ri~ i wires 113 and 118.
It should be mentioned at this point that pure aluminum is rarely used in commercial integrated circuit fabrication. Most processcs use a dilute alloy of aluminum that may contain copper or silicon, added to enhance the IC reliability and yield. Several of these alloys were tested in the process described in this disclosure and found to exhibit no significant differenoes. It should be apparent to a person skilled in the art that any reference to aluminum in this disclosure could also refer to one of these commonly used aluminum alloys.
Numerous ....~.iir;. ~li.. - . and variations will become apparent to those skilled in the art. It is to be understood that the above description is intended to be merely illustrative of the spirit of the invention and should not be taken in a limiting sense. The scope of the invention is defined by referenoe to the attached claims.

Table 1 film activityt adhesiontt as adhesion after a deposited 400 C amnealing Deposited Pd lOnmPdoverlOnmTi poor 100% 100%
Wet Pda2 longPda2exposure excellent 0% o%
Wet PdC12 short Pda2 exposllre moderate 0% 50%
Wet M excellent 0% 0%
Zincate moderate 0% 50%
Pd-AI film stack, 20nmAl,lOnmPd,10 poor 100% 100%
no alloy formed nm Ti Pd-Altttalloy with 20nmAl,lOnmPd,10 excellent 100% 100%
anneal nmTi t) Defln~d by the ability to plate isolated vias tt) Percentage of the deposited film ar~a remaining after peel test ttt) Present invention

Claims

1. A structure for facilitating deposition of a plating material on a substrate, said structure comprising:
an alloy layer of a base material and a catalyst material, said alloy layer having a first surface disposed proximal to said substrate, and an active catalytic surface for plating said plating material, said active catalytic surface disposed distal from said substrate, wherein said active catalytic surface is formed by removing atoms of said base material from said alloy layer, and wherein said active catalytic surface is formed substantially by atoms of said catalytic material which remain after removal of said atoms of said base material.

2. The structure of claim 1, further comprising:
a substrate; and an adhesion layer disposed between said substrate and said alloy layer.

3. A method for rendering a surface of an alloy catalytically active for deposition of a plating material, said alloy including a base material and a catalyst facilitating deposition of a plating material, said method comprising a step of treating a surface of said alloy with an etchant, said etchant having a removal rate of said base material exceeding a removal rate of said catalyst, thereby rendering said surface catalytically active.

4. A method of claim 3, wherein said catalyst comprises palladium.

5. A method of claim 3, wherein said base material comprises aluminum.

6. A method of claim 5, wherein said catalyst comprises palladium.

7. A structure of claim 1, wherein said base material comprises aluminum.

8. A structure of claim 1, wherein said catalyst comprises palladium.

9. A structure of claim 8, wherein said base material comprises aluminum.

10. A structure of claim 2, wherein said base material comprises aluminum.

11. A structure of claim 2, wherein said catalyst comprises palladium.

12. A structure of claim 11, wherein said base material comprises aluminum.

13. A structure of claim 2 further including plating material and wherein said plating material is disposed on said active catalytic surface of said alloy.

14. A structure of claim 12 further including plating material and wherein said plating material is disposed on said active catalytic surface of said alloy.

15. A semiconductor device comprising:
a first layer of conductive material;
a layer of insulator disposed on said conductive material, said layer of insulator having at least one hole therethrough; and a plating initiation layer for facilitating deposition of a plating material, said plating initiation layer containing an alloy of a base material and a catalyst, said alloy having an active catalytic surface for plating said plating material, said alloy further having a vacancies-containing region in the vicinity of said catalytic surface, said vacancies being present in locations from which atoms of said base material have been removed, and said plating initiation layer being disposed at the bottom of said hole, thereby contacting said first layer of conductive material.

16. A structure of claim 15, wherein said plating initiation layer is further disposed on portions of side walls of said hole.

17. A structure of claim 16, wherein said plating initiation layer comprises an adhesion layer, said adhesion layer being attached to said alloy and to said portions of side walls of said hole.

18. A structure of claim 17 further comprising a second conductive layer, said plating initiation layer being further in contact with said second conductive layer.

19. A structure of claim 15, wherein said alloy comprises aluminum and said catalyst comprises palladium.

20. A structure of claim 16, wherein said alloy comprises aluminum and said catalyst comprises palladium.

21. A structure of claim 17, wherein said alloy comprises aluminum and said catalyst comprises palladium.

22. A structure of claim 18, wherein said alloy comprises aluminum and said catalyst comprises palladium.

23. A structure of claim 15, wherein said plating material is disposed on said active catalytic surface of said alloy.

24. A structure of claim 16, wherein said plating material is disposed on said active catalytic surface of said alloy.

25. A structure of claim 17, wherein said plating material is disposed on said active catalytic surface of said alloy.

26. A structure of claim 18, wherein said plating material is disposed on said active catalytic surface of said alloy.

27. A structure of claim 19, wherein said plating material is disposed on said active catalytic surface of said alloy.

28. A structure of claim 20, wherein said plating material is disposed on said active catalytic surface of said alloy.

29. A structure of claim 21, wherein said plating material is disposed on said active catalytic surface of said alloy.

30. A structure of claim 22, wherein said plating material is disposed on said active catalytic surface of said alloy.

31. A structure of claim 1, wherein said catalytically active surface is formed by removing atoms of said base material from said alloy layer by exposing said alloy layer to an etchant having a higher etch rate of said base material than said catalytic material.

32. A structure for facilitating deposition of a plating material on a substrate, said structure comprising:
an alloy layer of a base material and a catalyst material, said alloy layer having a first surface disposed proximal to said substrate and an active catalytic surface for plating said plating material, said active catalytic surface disposed distal from said substrate, wherein said active catalytic layer is formed by removing atoms of said base material from said alloy layer, thereby exposing atoms of said catalytic material along said active catalytic surface and increasing the catalytic activity of said surface.

33. The structure of claim 32, further comprising:
a substrate; and an adhesion layer disposed between said substrate and said alloy layer.

34. A structure of claim 32 wherein said base material comprises aluminum.

35. A structure of claim 32 wherein said catalyst comprises palladium.

36. A structure of claim 35 wherein said base material comprises aluminum.

37. A structure of claim 33 wherein said base material comprises aluminum.

38. A structure of claim 33 wherein said catalyst comprises palladium.

39. A structure of claim 38 wherein said base material comprises aluminum.

40. A structure of claim 33 further including plating material and wherein said plating material is disposed on said active catalytic surface of said alloy.

41. A structure of claim 39 further including plating material and wherein said plating material is disposed on said active catalytic surface of said alloy.

42. A structure of claim 1 further including plating material and wherein said plating material is disposed on said active catalytic surface of said alloy by an electroless process.

43. A structure of claim 32 further including plating material and wherein said plating material is disposed on said active catalytic surface of said alloy by an electroless process.