CA2104124A1 - Device for shutting off an adaptive algorithm - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A device is proposed which is to be used in telephone systems for cancelling echoes which are generated at the transition of four wire lines to two wire lines. Therefor a signal processor and a microprocessor are provided, where the signal processor is rapid and handles the direct signal processing. It contains a double talk detector and a calculating device using an adaptive algorithm. The microprocessor monitors the echo cancelling and sets the stepsize of the adaption. A direct path is arranged between the detection device and the calculating device in such a way, that when a double talk state is detected, the adaption is immediately and completely shut off inside the calculating device. The microprocessor, which only periodically monitors the detection device, sets the stepsize of the adaption at a reduced value, when said microprocessor in a periodical check will find, that the double talk state is present. The adaption having a reduced stepsize is maintained during a long predetermined time period, during which the direct path between the detection device and the calculating device is blocked.

Description

WOg2/15156 PCT/SE92/00081 - 2 1 ~

A DEVICE FOR SHUTTING OFF AN ADAPTIVE ALGORITHM
TECHNICAL FIELD
The present invention is related to a device for the shutting off an adaptive algorithm which is used :in a calculating unit, which is comprised in a circuit for the cancelling of echoes in a four wire line. Echoes of the kind referred to here are generated by the fact that in many telephone systems a four wire line is joined to a two wire line at a location close to the subscriber.

PRIOR ART
In long distance telephone circuits normally two wire lines are used at a location close to the subscriber and a four ~ire line is used between telephone or switch stations, and presently the transmission on this four wire line is most often digital. At the connection between the two wire line and the four wire line an interface circuit or hybrid circuit is located providing for the conversion of the signals and the transfer thereof between the line systems. In the four wire line an echo occurs on two outgoing lines when a sig~al arrives on the other incoming two lines of said four wire line. In order to eliminate this echo conventionally a particular device is arranged like a balance filter. This echo cancelling device may be of the kind adapting itself in such a way that the outgoing echo will be as small as possible. In the case where messages are transferred both on the two incoming wires and the two outgolng wires - this state is conventionally referred to as double talk - the criterion mentioned above will not be suitable, that the echo, that is the signal in the two outgoing wires, should be as small as possible. In this case the automatic adaption of the echo cancelling circuit must be stopped and then be restarted when the state of double talk is not present any longer. In order to detect if double talk is present a detector is provided therefor which is connected to the two incoming wires and to the two outgoing wires. When the levels of the signals in these two wire groups will indicate a double talk condition, the detector will give a signal that the double talk state is present and will stop the automatic adaption of the balance filter.

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W092/15156 ~ l 2 1~ pcr/sFs2/ooos The echo cancelling circuit may contain, as is previously known, a calculating device using an adaptive algorithm in order to calculate a signal which is subtracted from the signal which is present on the two outgoing lines. The fact that the algorithm is adaptive means that it is dependant of at least one or several coefficients and that these coefficients may be changed in order to obtain the int~nded result of the calculation. ~he effect should be such that the signal which is derived from the result of the algorithm will give, when it is subtracted from the signal on the two outgoing wires, a signal level which is as close as possible to zero. Therefor another -detection device of the signal level in the two outgoing wires must be arranged which may compare the signal level to the -desired zero level or perform some other test and then sends the result of the comparison or the test to the calculation device. When a signal is transmi~ted on the two outgoing wires in the four wire line from the subscriber connected to the two wire line, the mentioned change of the coe~ficients in the adaptive algorithm must not be continued any longer since otherwise this signal on the two outgoing wires of the four wire line would be experienced as an echo and rause a completely erroneous adaption of the echo cancelling device.
The same situation applies when signals are arriving on the two incoming wires of the four wire line as well as on the two outgoing wires of the four wire line, that is for a double talk condition. Hereinbelow t~us the term double talk will also encompass the case where only a signal from the two wire line connected to a subscriber is present but no signal is arriving on the two incoming wires of the four wire line.

Examples of the prior art echo suppressors are given in US-A-4 005 277, US-A-4 360 712 and US-A-3 992 594. US-A-4 360 712, EP-Al-O 310 055 and US 4 894 820 disclose circuits for shutting off the adaptive algorithm. US 4 845 746 discloses control of the size of adaption steps DESCRIPTION OF THE INVENTION
The present inventlon i5 related to a way of shutting off or modifying the adaptive algorithm used in double talk ~3UB$TITUTE ~ EET

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WO92/lS156 ,~ 2 ~ P~T/S~92/0~081 suppressors and to perfor~ this by means of the components which are provided in many present telephone systems associated with hybrid circuits. The particular features and characteristics of the invention are set out in the appended claims.

The particular circuits and systems in which the invention can be used are described in "An 8-channel D',P with Adaptive Balance Filters for Analog Subscriber Lines", P.~Q. Sjoberg et al~ IEEE l9gl International Solid State Circuits Conference, pp. 236 - 237, and Slide Supplement thereto, pp. 172 - 173, which are incorporated as references herein.

Thus in an echo cancelling device as above comprising calculating circuits using an adaptive algorithm a direct connection is provided between the device for detection of the lS double talk condition and the calculating circuits. This path is connected directly into the circuits and will shut off the adaption, that is will inhibit a further modification of the coefficients being used inside the adaptive algorithm. On this direct path such a signal is transmi~ted for shutting off the adaption as soon as a double talk state is detectedO A
microprocessor is provided for monitoring the echo cancelling device and also for monitoring, periodically in small time periods, the double talk detector. If the microprooessor will find that a double talk condition is present .it will in turn shut of~ the direct path between the double talk detection device and the calculating circuits in such a way that the adaption, that is the modification of the changing coefficients in the algorithm, can be continued. Further the microprocessor will send a signal to the calculating signals to make the adaption being performed wiht a reduced stepsize, that is wit'-a reduced convergence rat~, compared to the normal convergence rate determined by the normal stepsize or possibly with a stepsize equal to zero. This state with an adaption using a reduced stepsize or a stepsize equal to zero may also be maintained during a time period continuing during several times when the microprocessor normally should have checked if the double talk detection device had detec~ed tha~ a double talk SUE~TlTUlrE SIHEET

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WO92/1~156 2 ~ O ~12 ~ PCT/SE92/00081 state was present.

DESCRIPTION OF THE DRAWINGS
The invention will now be described with reference to the accompanying drawings in which Figure l schematically shows the device ~ccording to the invention, Figure 2 is a fragmentary figure showing the manner in which the direct shutting off is performed, Figure 3 shows a flow diagram illustrating the program of a microprocessor comprised in the device according to the invention.

PREFERRED EMBODIMENT
In Figure l is shown a two wire line l connected to a near-end subscriber and a four wire line comprising two wires 3 for signals incoming to the near end subscriber and two other wires 5 for signals from the near end subscriber. These two groups each comprising two wires are in Figure l illustrated in single full lines like the two wire line l. The signals in the two directions in the four wire line 3, 5 are supposed to be transmitted digitally and the signals on the line l to the near-end subscriber are transmitted analogically in the common way. For the connection of the two wire line l to the four wire line 3, 5 therefor a digital-to-analog converter 7 is required which is connected to the incoming two wires 3 in the four wire line and converts the di~ital signals on the wires 3 into analog signals. In the same way for the two wires 5 for the outgoing signals on the four wire line an analog-to digital converter 9 is connected transforming incoming analog signals to digital signals which are transmitted on the wires 5.

The output terminals of the digital-to-analog converter 7 and the input terminals of the analog-to-digital converter 9 are connected to a converter ll performing the coupling of the four wire line 3, 5 to the two wire line l. This convers:ion or SWE3STITW~E E;HEET

WO92/3515fi 2 ! ~ ~ ~ 2 i~ PCT/SE92/00081 transfer inside the converter ll is necessarily in~omplQte and thus signals incoming on a wire group thereto are forwarAed in the other two connected wire groups although the signal strength could be significantly reduced. Owing to the digital-to-analog converter 7 no signals can be, however, forwarded on the wires 3 from the converter ll. Signals on the two wire line l of the near-end subscriber are in contrast forwarded through the analog-to-digital converter 9 to the wires 5. The same is also true for signals arriving on the four wir~ line in its incoming por~ion 3 because the transition from the two wire line l for this signal is not perfect~ This will result in an echo in the wires 5, that is a signal in the wires 5, which is a more or less precise picture having a reduced signal level of the signal arriving on the incoming wires 3 of the four wire line.

In order to cancel or suppress the echo resulting in t~ls way in the outgoing two wires 5 of the four wire line an ecno cancelling device 13 is provided. The echo cancelling device genera~es in the conventional way a signal which is subtracted from the signal in the outgoing two wire lines 5 in a connecting node 15. The signal which is subtracted by the echo cancelling device 13 from the signal in the outgoing wires 5 of the four wire line in the node 15, is generated by a calculating device 17, which through a line l9 connected to the incoming wires 3 of the four wire line receives signals from these incoming wires 3 and with guidance obtained from this received signal will calculate a signal which is provided to the node 15 through a line 21.

The calculating unit 17 will thus on the line 21 send a signal which in the node 15 is subtracted from the other incoming signals to this node and the resulting signal will be t~ansmitted from the node l5 on the outgoing wires 5 of the four wire line ~nd then this transmitted, resulting signal is fed back to the calculating unit 17 through a line 23. The calculating unit uses this sensed signal or error signal in the line 23 to calculate a new signal to be fed to the node 15 through the line 2l.
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WO 92/1~15~. 2 1 O l~ 1 2 l1 PCT/SE92/0008l In dependance of the signal sensed in line 23 certain coefficients are modified in the calculating algorithm which is the basis of the operation of the calculating unit 17. This modification of a coefficient can be macle by adding to the former value of the respective coefficient the result of a multiplication of thP mentioned, sensed signal, a scaling or convergence factor and an insignal to the respective coefficient. The insignal to a coefficient is derived from the actual signal on the incoming line 3 through the line 19 but delayed with a suitable amount. Owing to the size of said convergence factor t~e algorithm used by the calculating unit 17 the output signal on the line 21 will have a more rapid or a slower progression to the ideal value for the echo suppréssion.
This ideal value of the signal output on the wire 21 from the calculating unit 17 is thus the value which as true as possible depictures the echo which is expected to be transmitted on this wire.

Instead of using the error signal in line 23 as above the calculation unit 17 could make some other calculation to find out if the adaption has ~o be modified and how much and in what direction it has to modified.

However, when a signal arrives on the two wire line 1 and is allowed to pass through the wires 5, this signal is not an echo and the calculating device 17 would give a totally erroneous result if the adaption was allowed to continue. The same state will appear if signals arrive both on the wires 3 and are forwarded on the wires 5 in ~he four wire line. This latter state is referred to as double talk and herein also the case is encompassed that only a signal arrives on the two wire line 1 and is forwarded on the outgoing wires 5 of the ~our wire line.

In order to detect this double talk state there is provided a particular detector 25. This will on its output terminal 27 provide a signal that a double talk state is present. The detector 25 may be a single circuit u~ing the signal level in the inco~ing wires 3 and the ou~going wires 5 of the four wire $ ~ S~

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WO92/15156 2 ~ . 2 ~ PCT/SE92/OOOX1 line. Therefor, thus the detection device 25 has both its input terminals connected to the incoming wires 3 and the outgoing wires 5 of the four wire line. The output terminal of the detection device 25 is connected to the calcu:Lating device 17 through a line which passes through an AND-gate 29. The signal transmitted in this way through the AND-gate 29 from the double talk detection device 25 will in this way throu~h a line 30 arrive to the calculating device 17 and if this signal indicates that a double state is present, the adaption will be immediately stopped. This stopping or inhihition of the adaption is directly performed inside the calculating circuits in the calculating device 17. Thus in this case the signal is calculated which is provided by the calculating device 17 only by means of the coefficient values which were present when the double talk state signal was obtained.

The device also contains a microprocessor 31 monitoring the echo cancelling device 13. The microprocessor 31 ln particular monitors if a double talk state is present. Therefor the microprocessor 31 periodically checks a register 33 in which a signal flag is inscribed by the detection device 25 that a double talk condition is present. The register 33 is thus connected to the output terminal of a double talk detection device 25 and also to the microprocessor 31.

When the microprocessor 31 will find, by reading the register 33, that a double talk state is present, the microprocessor 31 will shut off the direct path between the output terminal of the detection device 25 and the calculating device 17. This is made by means of the AND-gate 29, and thus an output terminal of the microprocessor 31 is connected to an input terminal of the AND-gate. The microprocessor 31 thus on its out~ut terminal, which is connected to the AND-gate 29, will provide a logically low signal, a zero, when it has detected, by reading the register 33, that double talk is present, but in normal cases it will provide a logically high signal, a one, on this output terminal, and thus the direct path will then not be blocked. The line between the microprocessGr 31 and the AND-gate may also con~ain a register 35, from which some other unit $~E~STlTUllrE SHIEIE~T

WO92/151~6 2 ~ 2 l-~ PCT/SE92/00081 which is not shown can read if the microprocessor 3l is in a state when it controls the adaption inside the calculating unit 17 to a state having a reduced stepsize or a stepsize equal to zero. This is made by setting a signal flag in the register 35.
Thus when the microprocessor 31 sends a logically blocking signal, a zero, to the AND-gate 29, the direct connection is broken between the output of the de~ection device 25 and the calculating unit 17.

Further, the microprocessor 31 will forward through a line 37, connected to an input ~erminal of the calculating unit 17, a signal that the adaption now will be performed with a reduced stepsize, that is with a lower convergence rate, in the normal case having a value for instance less than a tenth or a hundredth of the normal value, or possibly that the stepsize will be set to zero, that is that the state of no adaption will be continued. This state o~ a reduced stepsize or a stepsize equal to zero will then be maintained during at least a predetermined time period extending over several times at which the microprocessor 31 normally would have read the register 31 in order to establish i~ a double talk state was present.

When the said predetermined time period has elapsed, the microprocessor 31 will again read the register 33, which is connected to the output terminal of the double talk detection device 25. If a double talk state now is not present any more, which is indicated by the value inscribed in the register 33, the microprocessor on its line 37 will provide a signal to the calculating unit 17 that the adaption of the calculating algorithm inside the calculating unit 17 will be continued with the normal stepsize or convergence rate. Otherwise naturally the state having a reduced size or a stepsize equal to zero is continued in the adaption until the microprocessor 31 again will read the register 33.

The various components and oircui~s being comprised in the echo cancelling device 13 have a rapid nature and consist of hardware components and circui~s particularly designed for their purpose. They can be comprised in a signal processor ~3ilJB51r9TlJTE SHEE~T

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WO9~/lSl56 2 ' ~! A ~ PCT/SE92/00081 which in many cases is provided in modern telephone systems at the transition of a four wire line and a two wire line. A
microprocessor 31 also is provided at these transition points in modern systems but the microprocessor is comparatively slow and cannot make more complicated logical determinations and in particular measurements of time what is not possible in a simple way with circuits being provided :in a signal processor, especially not in the echo cancelling part thereof.

Such a signal processor and a microprocessor can control the connection of several two wire lines 1 and four wire lines 3, 5.
In Figure 2 is illustrated in more detail how the direct shutting of~ of the modification of the coefficients inside the calculating unit can be made and how the microprocessor 31 will change the stepsize of the adaption of the coefficients. Only the case of the modification of one coefficient is illustrated in this Figure and it should be understood that in practice several coefficients are modified in the same way.

A formerly used coefficient value Cn_l arrives on a line 39 to an adder 41. The adder 41 provides a new modified coefficient Cn on its output 43O In the adder 4~ a small en~ity i6 added to the former coefficient value Cn_1 and this entity arrives on the oth~r input 45 of the adder 41. This small modifying entity arriving on the line 45 is normally formed from a signal which is derived from a delayed value of the incoming telephone signal on the line 3 of the four-wixe line through the line 19 and the error signal on the line 23 and it arrives to an input line 47 of a multiplicator 49. In the multiplicator 49 the signal on the llne 47, which is a signal derived from, e.g.
normally delaye~ by fixed time, the signal on the incoming line 3 is muluiplied by a factor, which is the same for all coefficients C and is fed to the multiplicator 49 from a storage place or register 52 via a line 50. The value stored in the register 52 is in turn derived by the multiplication in a multiplicator 54 of a scaling factor and the error signal in line 23. The scaling factor is herein referred to as a stepsize and is stored in a field 53 in a storage area 51 and is fed to $U13~TIll LITE SHIEET

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W092/1~156 21 ~ 2 ~ pcr/sEs2/ooosl the multiplicator 54 from the ~torage area 51 through a line 55.

The coefficients C may then be multiplied by suitable values derived by delaying the signal on the incoming line 3 and the results may be added to form the signal to be subtracted in line 21 but this is not illustrated in the Figure.

In practice the multiplicators 49 and 54 may be the sarne circuit and then additional logic is needed to switch the signals accordingly.

The microprocessor 31 has access to the storage area 5:L through a bus line 57 which is comprised in the line shown at 37 in Figure l. The microprocessor 3l thus may change the various stored numbers in the storage area 51 and in particular the stepsize which is stored in the field 53. As has been mentioned above this modification of the stepsize is re.latively slow.

The direct shutting off o the adaption, that is of the modification of a coefficient Cn_l, is instead made in another way. A multiplexor 59 is with one of its inputs connected to the output of the multiplica~or 49 and with its other output to the input line 45 of the adder 410 The multiplexor 59 will on its other input receive predetermined signals representing a value O and this input may thus ~or instance be connected to ground. On the control input 63 of the multiplexor the direct control signal will arrive for the shutting off of the adaption which in Figure l arrives on the line 30 to the calculating unit 17. Thus it will be understood that with a suitable signal on the control input 63 always the value o is fed to the adder 41, whereby the adaption, that is the modification of the coefficiency Cn l~ will stop totally.

In Figure 3 a flow diagram of the procedure executed by the microproc2ssor 31 i5 illustrated. In the procedure shown the microprocessor 31 polls the register or flipflop 33 at time intervals Tl. If it detects a double talk state, the micropro-cessor 31 will wait a time period T2 before it starts the adap-$~lB$-rlT~JTE S~J~

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tion again and cuts off the direct path between the double talk detector and the adaption circuits. Also, the case is illustrated principally when the register or flipflop 33 is set and reset by the double talk detector.

From the start lO1 of the program the microprocessor will in a step 103 set the flipflop 35 to a logical one and this flipflop will on its output enable signals from the double talk detection device 25 to pass directly through the gate 29 to the calculating unit 17. Also in this step 103 the normal large adaption step is set inside the calculation unit in its calculation circuits. Next in the steps 105 and 107 the microprocessor will wait a definite time Tl until it performs the next check of the register 33. Therefore it will in step 105 set a first timer (timer No. l) to a polling time Tl and then it will start this first timer. In step 107 the microprocessor tests if this time T1 has elapsed by testing if timer No. 1 indicates a zero value. If it does not, the microprocessor will again perform the same test. If the time has elapsed the program proceeds to step 109.

In step 109 the microprocessor tests if a double talk condition is present by checking if register 33 contains a logical one.
If it does not contain a logical one another time period T~ is set up by the fact that the program in the microprocessor returns to step 105. If a double t~lk condition exists, the program proceeds to a step 111 where another timer No. 2 is initialized to a time period T2 and then this second timer is started. In a step 113 it is ~ested if this time T2 f timer No. 2 has elapsed. If it has not the program will perform this test again until the time ~'2 has elapsed. In the latter case the program proceeds to a step 115. Here it is again tested if register 33 contains a logical one, that is if a double talX
condition still is present. If this condition is not satisfied, that is if register 33 contains a logical zero, the program returns to the former step 105 to perform another wait cycle of length T1 until it again rhecks register 33. If in step 115 it is detected that a doubIe talk condition still is present the program proceeds to a step 117 where first the calculation SUBSTITU~ E SHEET
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circuits inside the calculation unit are initialized to have a small adaption step. Then this adaption with small steps is started by setting register 35 to a logical zero. Thereby the register or flipflop 35 on its output will have a logically low signal so that the AND-gate 29 will block the direct path between the double talk detector 25 and the calculation unit 17.

In the next step 119 the microprocessor 31 resets the register 33. However, this step has to be omitted in the embodiment first discussed herein.

Thus in this first embodiment the program proceeds directiy from step 117 to a step 121 where the first timer is again initialized to the same time Tl as in the beginning of the loop and this first timer i5 started. In a step 123 then it is tested if this time T1 of timer No. 1 has elapsed in the same way as above when this time Tl has elapsed the program proceeds to a step 125 where it again tests i~ register 33 contains a logical one, that is if a double talk condition still is present. If a double talk condition is present another time period of length T1 is initialized in the step 121. However, if there is no double talk condition the program returns to the beginning and will in step 103 again enable that the direct path between the double talk detector 25 and the calculating unit 17 and the steps as described above will all be performed again.

In another embodiment of this procedure the step 115 will be omitted and a step 119 is inserted between the steps 117 and 121, as is mentioned above. In step 119 the flipflop 33 is reset, that is set to zero, by the microprocessor 31 itself. In this case also it is supposed that this flipflop 33 only can be set, that is set to a logical one, by the double talk detaction device 25 and that it cannot be reset by this detector. Instead it is always reset by the microprocessor 31. In the latter case, thus the microprocessor will always wait a time period T2 when no adaption is allowed in the calculating unit 17 due to a signal on the direct path from the double talk detector 25 to SaJE~STlTUTE S~ET
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khe calculating unit 17. After this time T2 the adaption is allowed again but with a small step. This adaption with a small step will then be performed for at least a time period between two regular polls of the flipflop 33.

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Claims (8)

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1. A device for shutting off the adaption in a calculating unit comprising an adaptive algorithm and connected at the transition of a four wire line connected to a far end subscriber and a two wire line connected to a near end subscriber and being comprised in a circuit for the cancelling of echoes in the four wire line, said calculating unit being arranged in such a way that the adaptive algorithm comprises at least one coefficient and that this coefficient is periodically modified, this modification being dependent of a predetermined factor or step and a value which is determined periodically or is determined at each time when said circuit senses that an echo is present, the algorithm being such that a larger value of this factor or step will cause a more rapid convergence of the algorithm to a desired value and a smaller value will cause a slower convergence of said algorithm, characterized in that a direct path is provided between the double talk detection device and the calculating unit and that the double talk detection device, that a signal on this path to the calculating unit is arranged to stop the adaption immediately, that is to stop said modification of coefficients, when a double talk state is detected, and that a microprocessor is arranged to monitor at definite time periods the double talk detection device and at the detection of the case where the detection device has detected a double talk state in turn shut off the direct path between the detection device and the calculating device and modify the factor or step used in the adaptive algorithm of the calculating device to a small portion of its former value, that is to continue the adaption with a slower convergence, or to set said factor or step equal to zero, that is to continue the state of no adaption.

2. A device according to claim 1, characterized in that the microprocessor is arranged always to continue the adaption with a reduced factor or step or with a factor or step equal to zero during a predetermined time period and during all of this time maintain the direct path blocked between the detection device and the calculating device.

3. A device according to one of claims 1 - 2, characterized in that the microprocessor is arranged to start the adaption with a factor or step having a reduced value or a value equal to zero at a time which is delayed a predetermined time period after the time when the microprocessor has determined that the double talk detection device has detected a double talk state.

4. A device for shutting off the adaption in a calculating unit comprising an adaptive algorithm and connected at the transition of a four wire line connected to a far end subscriber and a two wire line connected to a near end subscriber and being comprised in a circuit for the cancelling of echoes in the four wire line, said calculating unit being arranged in such a way that the adaptive algorithm comprises at least one coefficient and that this coefficient is periodically modified, this modification being performed by the addition of said coefficient and a first value derived from at least a predetermined positive factor or step and/or a second value which is determined periodically or is determined at each time when said circuit senses that an echo is present, the algorithm being such that a larger value of the factor or step will cause a more rapid convergence of the algorithm to a desired value and a smaller value will cause a slower convergence of said algorithm, characterized in that a direct path is provided between the double talk detection device and the calculating unit and that the double talk detection device, that a signal on this path to the calculating unit is arranged to stop the adaption immediately, that is to stop said modification of coefficients, when a double talk state is detected, that said calculating unit comprises an adder circuit for performing the said addition to the respective coefficient, the input terminal of the adder, which is connected to receive said derived first value, also being connected to said direct path in such a way that a signal on the direct path will always feed a value of zero to this input.

5. A device according to claim 4, characterized in that said first value is derived from said factor or step and said second value by a multiplication thereof.

6. A device according to claim 4, characterized in that a microprocessor is arranged to monitor at definite time periods the double talk detection device and at the detection of the case where the detection device has detected a double talk state in turn shut off the direct path between the detection device and the calculating device and modify the factor or step used in the adaptive algorithm of the calculating device to a small portion of its former value, that is to continue the adaption with a slower convergence, or to set said factor or step equal to zero, that is to continue the state of no adaption.

7. A device according to claim 6, characterized in that the microprocessor is arranged always to continue the adaption with a reduced factor or step or with a factor or step equal to zero during a predetermined time period and during all of this time maintain the direct path blocked between the detection device and the calculating device.

8. A device according to one of claims 6 - 7, characterized in that the microprocessor is arranged to start the adaption with a factor or step having a reduced value or a value equal to zero at a time which is delayed a predetermined time period after the time when the microprocessor has determined that the double talk detection device has detected a double talk state.