CA2085189A1 - Circuit arrangement for protecting interface circuits against overvoltages - Google Patents
Circuit arrangement for protecting interface circuits against overvoltagesInfo
- Publication number
- CA2085189A1 CA2085189A1 CA 2085189 CA2085189A CA2085189A1 CA 2085189 A1 CA2085189 A1 CA 2085189A1 CA 2085189 CA2085189 CA 2085189 CA 2085189 A CA2085189 A CA 2085189A CA 2085189 A1 CA2085189 A1 CA 2085189A1
- Authority
- CA
- Canada
- Prior art keywords
- circuit arrangement
- overvoltages
- transformer
- fuse element
- voltage potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
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- 230000004048 modification Effects 0.000 claims description 4
- 238000012986 modification Methods 0.000 claims description 4
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- 230000005540 biological transmission Effects 0.000 description 7
- 230000006378 damage Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 241000272470 Circus Species 0.000 description 1
- 101150049278 US20 gene Proteins 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- 238000005259 measurement Methods 0.000 description 1
- LQZPJQKYAOYUJS-UHFFFAOYSA-N n,n-diethyl-2-phenothiazin-10-ylethanamine;hydron;chloride Chemical compound Cl.C1=CC=C2N(CCN(CC)CC)C3=CC=CC=C3SC2=C1 LQZPJQKYAOYUJS-UHFFFAOYSA-N 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/18—Automatic or semi-automatic exchanges with means for reducing interference or noise; with means for reducing effects due to line faults with means for protecting lines
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Emergency Protection Circuit Devices (AREA)
- Interface Circuits In Exchanges (AREA)
- Devices For Supply Of Signal Current (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
The circuit arrangement protects an interface circuit connected to two-wire subscriber lines against overvoltages occurring on the subscriber lines. The interface circuit has a transformer for signal infeed and/or signal outfeed whose center tap at the line side is at a DC voltage potential. The protection occurs in that the line-side center tap (17, 27) of the transformer (T10, T20) is connected via a fuse element (Si10, Si20) to the DC
voltage potential, and in that the connection between fuse element and DC voltage potential is connected to ground via a surge arrestor element (Ts10, Ts20).
The circuit arrangement protects an interface circuit connected to two-wire subscriber lines against overvoltages occurring on the subscriber lines. The interface circuit has a transformer for signal infeed and/or signal outfeed whose center tap at the line side is at a DC voltage potential. The protection occurs in that the line-side center tap (17, 27) of the transformer (T10, T20) is connected via a fuse element (Si10, Si20) to the DC
voltage potential, and in that the connection between fuse element and DC voltage potential is connected to ground via a surge arrestor element (Ts10, Ts20).
Description
~8~ 8~
B~C~ROUND OF TH~ I ~ NT~Q~
The present invention i~ directed to a circuit arrangement for protecting an interfa~e circuit colmected to two-wire subs¢riber lines again~t overvoltages appsaring on the ~ubscriber linesO The inter~ace circuit has a transformer.~or ~ignal in~eed ~nd/or signal outfeed, a mi~dle tab ther~of at the line æide being ~t a DC
voltage potential.
Such interface circuits, for example, are used ~or signal tran~mission in ISDN telecommunication ~ystem~. ~he paired use o~
such interface clrcuits Por the two-wire transmi~sion sub~criber line and the two-wire reception ~ubscriber line is known from "ISDN
Das kuenftige Fernmeldenetz der Deutschen Bundespost~, Second Edition, R.v. Decker's Verlag, page 39, FIG. 2-5.
The illustrated ISDN networX termination has a respective interface circuit in each of the transmisslon and reception directions, thes~ being respectively connected via two-wire subscriber lines to the corresponding interface circuit of the connected terminal e~uipment. For signal in~eed or signal outfeed, each of these interface circuits has a transformer that has a middle tap at the line side for what ie referred to as the phantom ~eed of the terminal equipment, thi middle tap being at a ~C
voltage potential.
In the network termination, the middle taps of th~
trans~ormers for the two interface voltages are connected to a feed voltage source. In the terminal equipment, the corresponding middle taps are connected to a supply voltage generation.
It is possible for overvoltages that can lead to a destruction o~ the inter~ace circuits to appear on the s~bscriber lines. ~hese overvoltage~ can b~e caused by contact of the subscriber line to the 220 Y mains voltagl3, by induced voltages, as well as by atmo6pheric ~ 2~8~8~
dischargee and can cau~e a leakage current to ground. Atmo~pheric discharge~ result in high-energy, trenchant overvoltage~ on the subscriber line that only briefly load the components oP the connected interface circuit.
The trenchant overvoltage~ which an inter~ace circuit mu~t resist in a telecommunication ~ystem are described in the YTZ
guideline 12 TRl. The~e overvoltage~ mu~t not a per~anent functional disruption of the interface circuit. Glven contact o~
the subscriber line6 with the 220 V mains voltage, by contrast, only a destruction of the interface circuit need be prevented and the functionability need no longer be established after ~uch a contact. All of these overvoltages have ground as a re~erenc~
potential and can cause leakage currents at all locations at which an interface circuit is coupled to ground.
For protecting the inter~ace circuit in the prior art, subscriber lines are conneoted to ground via ~urge arrester elements, for example surge arresters fill~d with inert gas or varistors. Up to a prescribed response voltage, these 6urge arr~sters are high-impedance. When this voltage is exceeded, they become conductive and remain in this condition until the current flow falls below a defined minimum current.
As a further measure, series resistances (transfer impedances~
that are temperature-dependent can be provided in the interface circuit and react with an exponential increase in thçir value of resistance to the leakage current caused by the overvoltage.
Both measures have the di~advantage that they negatively influence the symmetry properties of interface circuits due to component tolerances. Thus, for example, the parasitic capacitance between the terminals of surge arresters has a cert~in distribution of values, the symmetry being modified as a re~ult ther~of.
B~C~ROUND OF TH~ I ~ NT~Q~
The present invention i~ directed to a circuit arrangement for protecting an interfa~e circuit colmected to two-wire subs¢riber lines again~t overvoltages appsaring on the ~ubscriber linesO The inter~ace circuit has a transformer.~or ~ignal in~eed ~nd/or signal outfeed, a mi~dle tab ther~of at the line æide being ~t a DC
voltage potential.
Such interface circuits, for example, are used ~or signal tran~mission in ISDN telecommunication ~ystem~. ~he paired use o~
such interface clrcuits Por the two-wire transmi~sion sub~criber line and the two-wire reception ~ubscriber line is known from "ISDN
Das kuenftige Fernmeldenetz der Deutschen Bundespost~, Second Edition, R.v. Decker's Verlag, page 39, FIG. 2-5.
The illustrated ISDN networX termination has a respective interface circuit in each of the transmisslon and reception directions, thes~ being respectively connected via two-wire subscriber lines to the corresponding interface circuit of the connected terminal e~uipment. For signal in~eed or signal outfeed, each of these interface circuits has a transformer that has a middle tap at the line side for what ie referred to as the phantom ~eed of the terminal equipment, thi middle tap being at a ~C
voltage potential.
In the network termination, the middle taps of th~
trans~ormers for the two interface voltages are connected to a feed voltage source. In the terminal equipment, the corresponding middle taps are connected to a supply voltage generation.
It is possible for overvoltages that can lead to a destruction o~ the inter~ace circuits to appear on the s~bscriber lines. ~hese overvoltage~ can b~e caused by contact of the subscriber line to the 220 Y mains voltagl3, by induced voltages, as well as by atmo6pheric ~ 2~8~8~
dischargee and can cau~e a leakage current to ground. Atmo~pheric discharge~ result in high-energy, trenchant overvoltage~ on the subscriber line that only briefly load the components oP the connected interface circuit.
The trenchant overvoltage~ which an inter~ace circuit mu~t resist in a telecommunication ~ystem are described in the YTZ
guideline 12 TRl. The~e overvoltage~ mu~t not a per~anent functional disruption of the interface circuit. Glven contact o~
the subscriber line6 with the 220 V mains voltage, by contrast, only a destruction of the interface circuit need be prevented and the functionability need no longer be established after ~uch a contact. All of these overvoltages have ground as a re~erenc~
potential and can cause leakage currents at all locations at which an interface circuit is coupled to ground.
For protecting the inter~ace circuit in the prior art, subscriber lines are conneoted to ground via ~urge arrester elements, for example surge arresters fill~d with inert gas or varistors. Up to a prescribed response voltage, these 6urge arr~sters are high-impedance. When this voltage is exceeded, they become conductive and remain in this condition until the current flow falls below a defined minimum current.
As a further measure, series resistances (transfer impedances~
that are temperature-dependent can be provided in the interface circuit and react with an exponential increase in thçir value of resistance to the leakage current caused by the overvoltage.
Both measures have the di~advantage that they negatively influence the symmetry properties of interface circuits due to component tolerances. Thus, for example, the parasitic capacitance between the terminals of surge arresters has a cert~in distribution of values, the symmetry being modified as a re~ult ther~of.
2~5~
.D~ L51~L~ OD~SU~N
It i~ an object of the present invention to provlde a circuit arrangement which protects the interface circuit against the ab~ve;
described overvoltag~s without affecting the ~ymmetry propertie~.
Based on the circuit arrange~erlt described above, the present invention achieves this object in that the center tap o~ the transfor~er ~t the line ~ide 1~ connected to the DC voltage potential via a fuse element, and i.n that the connection between fuse element and DC voltage potentiall is connected to ground via a surge arrester element.
Since the elements ~or overvoltage prote~tion are not directly connected to the two-wire subscriber line, they do not act on the sy~metry properties. The cen~er tap represents a re~erence point for the signal transmission and ~or the symmetry of the arrangement that can be connected to a DC voltage potential without affecting the signal transmission properties or the symmetry proper ies with tolerance-affected ~omponent parts.
The leakage currents that ocour for overvoltages are conducted to ground by this arrangement via the elements for over voltage protection on the basis of the line-side winding o~ the transformer. This path can be designed such that this can occur without destroyiny the interface circuit.
It is particularly the line side winding of the transfor~er that must be dimensioned for the case ffl surge arresting. Since limits are pla~ed on the dimensioning thereo~ due to the goal o~ an optimally compact structure, the line-side winding of the transformer is preferably designed ~uch that the leakage currents of trenchant overvoltages can flow without permanent modi~icatlon and that the fuse element interrupts the current path ~or overvoltages that last longer.
2~8~9 There i8 a dependency on the pul~e duration of the leakage current for a maximally possible loadability of the trans~or~er.
The ~horter the leakage current, the higher the peak value of the leakage value can be without ~ausing a destruction or permanent modi~ication of the transmi~aion propartiee. The maximum pos6ible loadability o~ the tran~for~er (aG a function of pul~e duration and pulse amplitude~ is influenced by the w1nding format, structur2, thermal behavior and other material con~tants and can h~ calculated therefrom or be identi~ied by measurement~ This ~unction can b~
utilized to dimension the line~side winding such that the afore-mentioned, trenchant overvoltages do not cause a permanent modification.
Longer-lasting overvoltages, particularly from contact o~ the subscriber line with the 220 V mains voltage~ lead to high thermal loads. Appropriate dimen~ioning of the fuse element can prevent this lo~d from occurring. The trans~ormer can be dimensioned corresponding smaller. A sa~eky fuse is preferably employed as the ~use element. The dependenGy of the interruption of current and currPnt duration present given safety ~uses enables the selection of a fuse that meets the above recited conditions.
In ~ development of the present invention, the surge arrester element is used in co~mon by ~ plurality of interface circuitæ~
This is possible since the surge arrester element is directly connected to a point that lies ~t a co~mon DC voltage potenti~l and does not carry signals.
B~IEF DESCRIPTION OF ~H~ DRAWINÇS
The features of the present invention which are believed to be novsl, are set f~rth with particularity in the appended claims.
The invention, together with further obiects and advantages, may best be understood by reference to the follo~ing description taken in conjunction with the accompanying drawings, in the ~everal Figures in which like re~erence numerals identi~y like elements~
and in which:
FIG. 1 i~ a circuit diagram of inter~ace circuits of an ISDN-50 interface of the pr~or art 7 FIG. 2 is a circuit diagra~ of interPace circuits o~ an exemplary e~bodiment o~ inter~ace circuits o~ a ISDN-So inter~ace having the overvoltage protection cf the present invention.
DESCRIPTION_OF THE ~REFERRED EMBODIM~
FI~. 1 shows interface circuits o~ an ISDN-So interface of the prior art. These inter~ace circuits can be realized as a component part of a subscriber circuit of a teleco~munication ystem that contains other parts ~or signal generating and connection control that are not relevant to the present invention. A respect~ve, identically constructed interface circuit 10, 20 is provided ~or the transmission and reception directions of the ISDN-So interface.
The transmission circuit S of the subscriber circuit has the terminals 11 and 12 connected to the primary winding of a transformer T10. For protecting the transmission circuit S, these tarminals are connected via 2ener diodes ZD10, ZD11 to ground, the breakdown voltage of these Zener diodes being above the peak voltage of the signal to be transmitted.
: The ter~inals 13 and 14 o~ the secondary winding o~ the transformer T10 have lines 15, 16, respectively, connected to first terminals of 6eries resistances R10, Rll, respectively, who~e second terminal is connected to the output te~minals Sxl, Sx2, respectiv~ly. The two-wire subscriber line in the transmission direction is connected to these output terminals Sxl and Sx2. The line~ 15 and 16 are connected to one another Yia diode circuite D10 and Dll that are connected in an antiparallel fashion as depicted 8 ~
in FIG 1. The on-state voltage of these diode circuits 10 and D11 lies ~bov~ the peak voltage o~ the ~ignal to be tran~mitted and limits the diPferential voltage at the secondary winding o~ the transfor~er T10.
The series resistances R10 and R11 are PTC resis~ors that exponentially increase their value o~ resi~tanca giv~n heating that occurs due to an increased current flow and thus change the internal resistance o~ the inter~ace circuit. DeYiationfi of these re~istance~ from the nominal value hiav~ an e~fect on the resistance symmetry of the inter~ace circuit.
As an additional protective measure, the output terminal~ Sxl and Sx2 are connected to ground via surge arresters US10, US11, respectively, that are ~illed with inert gas. Di~ferent parasitic capacitance likewise have an e~fect on khe ~ymmetry properties.
For the phantom feed of a subscriber terminal equipment ~not shown) that is connected to the ~ubscriber line, th~ center tap 17 of the secondary winding o~ the transformer T10 i8 connected via the line 18 to a terminal 19 o~ a voltage source SV. The reception circuit E o~ the subscriber circuit has the terminals 21 and 22 connected to the secondary winding of a transformer T20, For protecting the reception circuit ~, these terminals are connect2d to ~round via Zener diodes 2D20, ZD21/ respectively, whose breakdown voltage lies above the peak voltage of tha ~ignal to be transmitted.
The terminals 23 and 24 o~ the pri~ary windinq of the transformer T20 haYe lines 25, 26/ respectively, co~n~cted to first terminals of series resistances R20, R21, respectively, whose s~cond terminal is connected to the output terminals Srl, Sr2, respectively~ The two-wire ~ubscriber line in the reception direction is connected to these output ter~inals Srl and Sr2. The 2 ~
lines ~5 and 26 ~re connected to one another Yia diode circuit~ D20 and D21 that ~re conn~cted in an antipar~llel ~ashion. The on-state voltage of these diode circu:its D20 and D21 li2~ ~bove the peak voltage of the æignal to be tran~mitted and limits the differential voltage at the primary winding o~ the trans~ormer T20.
- Th~ series resistances R20 and R21 are PTC resistor~ that exponentially increa~e their value o~ resist~nce given heating th~t occurs due to an increaæed curr~nt ~low and thus change the ~nternal resistance of the interfaae circui.t. Deviation~ of these resistors from the nominal value have an e~ert on the resistance symmetry of the interface circuit.
As an additional protective measure, the input ter~inals Srl and Sr2 are connected to ground via ~urge arre ter~ US20, ~S21t respectively, that are filled with inert ga~. Dif~erent parasitic capacitances likewise have an effect on the symmetry propertie~.
For completing ths supply current path of the phantom ~eed of a subscriber terminal e~uipment (not shown) that is connected via the subscriber line, the center tap 27 of the primary winding of the transformer T20 is connected by the line 28 to the second terminal 29 o~ the voltage upply SV.
FIG. 2 shows an exemplary embodiment of inter~ace circuits of an ISDN-So inter~ace having the overvoltase protection o~ the present invention. Elements o~ the circuit arrangement that are unmodified by comparison to FIG. 1, the same de~ignations of component parts are also employ~d.
The transmission circuit S of the s~b~criber circuit is connected to the terminals 11 and 12 of th~ primary winding oP a transformer T10 of an interface circuit 10. For protecting the transmission circuit S, these terminals ar~ connected to ground via Zener diodes ZD10, ZDll, respectively, whose ~reakdown voltage lie~
ab~ve the peak vo:ltage o~ the signal to be transmitted.
The terminals 13 and 14 o~ the 6econdary winding of the tran~former ~lo have line6 15, 16, respectively, connected to the output terminals Sxl, Sx2, re~pectively. The two-wir~ subscriber line in transmission direction i!3 connected to these output ter~inal~ Sxl and Sx2. The lines 15 and 16 are connected to one another via diode circuit~ DlO and Dll that are conn~cted in an antiparallel fashion. The on-state voltage o~ the~e diode ~ircuit~
DlO and Dll lies above the peak volt~ge o~ the ~.ignal to be transmitted and limits the diP~erential voltage at the secondary winding of the tran6~0rmer T10. Serles resistances and ~urge arresters a~ in FIG. 1 are not provided.
For the phantom feed of a subscriber terminal equipment ~not shown) connected via the subscriber line, the center tap 17 of the secondary winding of the transformer TlO i~ connected via the line 18 to a first terminal of a sa~ety fuse SilO. The second terminal thereof is connected to a te~minal l9 of a voltage source SVO This connection is connected to ground via a surge arrestor TslO that is a semiconductor circuit in this example.
The reception circuit E o~ the subscriber circuit i connected to the terminals 21 and 22 of the ~econdary winding of a transformer T20 of an interface circuit 20. Por protecting the reception circuit E, the~e terminals are connected to ground via Zener diodes ZD20, ZD21, respectively whose bre~kdown voltage lie above the peak voltage of th~ signal to be transmitted.
The terminals Z3 and 24 o the primary ~inding of the transformer T20 have lines 25, 26, r~spectively, connected to the output terminals Srl, Sr2, respectively. The two-wire ~ubscrib~r line in the reception direction ie connected to these output terminals Srl and Sr2. The lines 25 and 26 are connected to one anoth~r via diode circuits D20 and D21 that are connected in an 2 ~
antiparallel ~a~hion. The on~sta~e voltage of these diode circuit~
D20 and D21 lies abo~e the peak voltage o~ the ~ignal to be transmitted and limit6 the differential volt~ge at the primary winding of the trans~or~0r T20.
For completing the ~upply voltage path o~ the phantom ~eed o~
a subscxiber ter~inal ~quip~ent (IIOt ~hown) connected via the subscriber line, the center tap 27 of the ~econdary winding o~ th~
tra~s~ormer T20 i~ connectQd via a line 28 to a ~lrst terminal oP
a safety ~use Si20. The second terminal thereof i~ conne~ted to a terminal 29 of the voltage ~ource SV. Thi connection is connected to ground via a surge arrestor Ts20 that i5 a semiconductor circui~
in this example.
When, for example, an overvoltage occurs at the terminal Sxl, a leakage current arises via the conne~ting line 15, the transformer T10, the safety ~use SilO and the ~urge arrestor Tsi.
Whsn the voltage drop-off at the sub-winding betw2en the terminals 13 and 17 exceeds the on-state voltage of the diode circuits D10 or Dll, then a parti~l current also flows across ~he corresponding diode circuit and the ~ub-winding ~etween ~he terminals 14 and 17.
When this is a trenchant overvoltage, the safety fuse SilO does not interrupt this c~rrent path. ~he inter~ace cirsuit remainæ Pully functional aft2r the overvoltage.
When, for example, th overvoltages are caused by a contact with the 220 V ~ains voltage, the ~afety fuse interrupts this current path after a defined reæponse time. This occur~ before any permanent effect can occur, such as, fvr exampla, a destruction of the transformer T10. After the ~vervoltage, the interfac~ circuit is still ready for ~ignal txansmission. A phantom fe~d is no longer possible ~i.nce the safety fuse must be replacedO
The invention i8 not limi~ed to th~ particular details o~ the apparatus depictad and other ~odi:eications an~ applications are contemplated. Certain olther ::hanges may be made iLn the ~bove described apparatus withou1: departin~ from the true spirit and scope of the invention herein involved. It i6 intend~d, therefore, that the ~ubject matter in the above~ depiction ~hall be interpreted a~; illustrative and not in a limiting ~en~e.
.D~ L51~L~ OD~SU~N
It i~ an object of the present invention to provlde a circuit arrangement which protects the interface circuit against the ab~ve;
described overvoltag~s without affecting the ~ymmetry propertie~.
Based on the circuit arrange~erlt described above, the present invention achieves this object in that the center tap o~ the transfor~er ~t the line ~ide 1~ connected to the DC voltage potential via a fuse element, and i.n that the connection between fuse element and DC voltage potentiall is connected to ground via a surge arrester element.
Since the elements ~or overvoltage prote~tion are not directly connected to the two-wire subscriber line, they do not act on the sy~metry properties. The cen~er tap represents a re~erence point for the signal transmission and ~or the symmetry of the arrangement that can be connected to a DC voltage potential without affecting the signal transmission properties or the symmetry proper ies with tolerance-affected ~omponent parts.
The leakage currents that ocour for overvoltages are conducted to ground by this arrangement via the elements for over voltage protection on the basis of the line-side winding o~ the transformer. This path can be designed such that this can occur without destroyiny the interface circuit.
It is particularly the line side winding of the transfor~er that must be dimensioned for the case ffl surge arresting. Since limits are pla~ed on the dimensioning thereo~ due to the goal o~ an optimally compact structure, the line-side winding of the transformer is preferably designed ~uch that the leakage currents of trenchant overvoltages can flow without permanent modi~icatlon and that the fuse element interrupts the current path ~or overvoltages that last longer.
2~8~9 There i8 a dependency on the pul~e duration of the leakage current for a maximally possible loadability of the trans~or~er.
The ~horter the leakage current, the higher the peak value of the leakage value can be without ~ausing a destruction or permanent modi~ication of the transmi~aion propartiee. The maximum pos6ible loadability o~ the tran~for~er (aG a function of pul~e duration and pulse amplitude~ is influenced by the w1nding format, structur2, thermal behavior and other material con~tants and can h~ calculated therefrom or be identi~ied by measurement~ This ~unction can b~
utilized to dimension the line~side winding such that the afore-mentioned, trenchant overvoltages do not cause a permanent modification.
Longer-lasting overvoltages, particularly from contact o~ the subscriber line with the 220 V mains voltage~ lead to high thermal loads. Appropriate dimen~ioning of the fuse element can prevent this lo~d from occurring. The trans~ormer can be dimensioned corresponding smaller. A sa~eky fuse is preferably employed as the ~use element. The dependenGy of the interruption of current and currPnt duration present given safety ~uses enables the selection of a fuse that meets the above recited conditions.
In ~ development of the present invention, the surge arrester element is used in co~mon by ~ plurality of interface circuitæ~
This is possible since the surge arrester element is directly connected to a point that lies ~t a co~mon DC voltage potenti~l and does not carry signals.
B~IEF DESCRIPTION OF ~H~ DRAWINÇS
The features of the present invention which are believed to be novsl, are set f~rth with particularity in the appended claims.
The invention, together with further obiects and advantages, may best be understood by reference to the follo~ing description taken in conjunction with the accompanying drawings, in the ~everal Figures in which like re~erence numerals identi~y like elements~
and in which:
FIG. 1 i~ a circuit diagram of inter~ace circuits of an ISDN-50 interface of the pr~or art 7 FIG. 2 is a circuit diagra~ of interPace circuits o~ an exemplary e~bodiment o~ inter~ace circuits o~ a ISDN-So inter~ace having the overvoltage protection cf the present invention.
DESCRIPTION_OF THE ~REFERRED EMBODIM~
FI~. 1 shows interface circuits o~ an ISDN-So interface of the prior art. These inter~ace circuits can be realized as a component part of a subscriber circuit of a teleco~munication ystem that contains other parts ~or signal generating and connection control that are not relevant to the present invention. A respect~ve, identically constructed interface circuit 10, 20 is provided ~or the transmission and reception directions of the ISDN-So interface.
The transmission circuit S of the subscriber circuit has the terminals 11 and 12 connected to the primary winding of a transformer T10. For protecting the transmission circuit S, these tarminals are connected via 2ener diodes ZD10, ZD11 to ground, the breakdown voltage of these Zener diodes being above the peak voltage of the signal to be transmitted.
: The ter~inals 13 and 14 o~ the secondary winding o~ the transformer T10 have lines 15, 16, respectively, connected to first terminals of 6eries resistances R10, Rll, respectively, who~e second terminal is connected to the output te~minals Sxl, Sx2, respectiv~ly. The two-wire subscriber line in the transmission direction is connected to these output terminals Sxl and Sx2. The line~ 15 and 16 are connected to one another Yia diode circuite D10 and Dll that are connected in an antiparallel fashion as depicted 8 ~
in FIG 1. The on-state voltage of these diode circuits 10 and D11 lies ~bov~ the peak voltage o~ the ~ignal to be tran~mitted and limits the diPferential voltage at the secondary winding o~ the transfor~er T10.
The series resistances R10 and R11 are PTC resis~ors that exponentially increase their value o~ resi~tanca giv~n heating that occurs due to an increased current flow and thus change the internal resistance o~ the inter~ace circuit. DeYiationfi of these re~istance~ from the nominal value hiav~ an e~fect on the resistance symmetry of the inter~ace circuit.
As an additional protective measure, the output terminal~ Sxl and Sx2 are connected to ground via surge arresters US10, US11, respectively, that are ~illed with inert gas. Di~ferent parasitic capacitance likewise have an e~fect on khe ~ymmetry properties.
For the phantom feed of a subscriber terminal equipment ~not shown) that is connected to the ~ubscriber line, th~ center tap 17 of the secondary winding o~ the transformer T10 i8 connected via the line 18 to a terminal 19 o~ a voltage source SV. The reception circuit E o~ the subscriber circuit has the terminals 21 and 22 connected to the secondary winding of a transformer T20, For protecting the reception circuit ~, these terminals are connect2d to ~round via Zener diodes 2D20, ZD21/ respectively, whose breakdown voltage lies above the peak voltage of tha ~ignal to be transmitted.
The terminals 23 and 24 o~ the pri~ary windinq of the transformer T20 haYe lines 25, 26/ respectively, co~n~cted to first terminals of series resistances R20, R21, respectively, whose s~cond terminal is connected to the output terminals Srl, Sr2, respectively~ The two-wire ~ubscriber line in the reception direction is connected to these output ter~inals Srl and Sr2. The 2 ~
lines ~5 and 26 ~re connected to one another Yia diode circuit~ D20 and D21 that ~re conn~cted in an antipar~llel ~ashion. The on-state voltage of these diode circu:its D20 and D21 li2~ ~bove the peak voltage of the æignal to be tran~mitted and limits the differential voltage at the primary winding o~ the trans~ormer T20.
- Th~ series resistances R20 and R21 are PTC resistor~ that exponentially increa~e their value o~ resist~nce given heating th~t occurs due to an increaæed curr~nt ~low and thus change the ~nternal resistance of the interfaae circui.t. Deviation~ of these resistors from the nominal value have an e~ert on the resistance symmetry of the interface circuit.
As an additional protective measure, the input ter~inals Srl and Sr2 are connected to ground via ~urge arre ter~ US20, ~S21t respectively, that are filled with inert ga~. Dif~erent parasitic capacitances likewise have an effect on the symmetry propertie~.
For completing ths supply current path of the phantom ~eed of a subscriber terminal e~uipment (not shown) that is connected via the subscriber line, the center tap 27 of the primary winding of the transformer T20 is connected by the line 28 to the second terminal 29 o~ the voltage upply SV.
FIG. 2 shows an exemplary embodiment of inter~ace circuits of an ISDN-So inter~ace having the overvoltase protection o~ the present invention. Elements o~ the circuit arrangement that are unmodified by comparison to FIG. 1, the same de~ignations of component parts are also employ~d.
The transmission circuit S of the s~b~criber circuit is connected to the terminals 11 and 12 of th~ primary winding oP a transformer T10 of an interface circuit 10. For protecting the transmission circuit S, these terminals ar~ connected to ground via Zener diodes ZD10, ZDll, respectively, whose ~reakdown voltage lie~
ab~ve the peak vo:ltage o~ the signal to be transmitted.
The terminals 13 and 14 o~ the 6econdary winding of the tran~former ~lo have line6 15, 16, respectively, connected to the output terminals Sxl, Sx2, re~pectively. The two-wir~ subscriber line in transmission direction i!3 connected to these output ter~inal~ Sxl and Sx2. The lines 15 and 16 are connected to one another via diode circuit~ DlO and Dll that are conn~cted in an antiparallel fashion. The on-state voltage o~ the~e diode ~ircuit~
DlO and Dll lies above the peak volt~ge o~ the ~.ignal to be transmitted and limits the diP~erential voltage at the secondary winding of the tran6~0rmer T10. Serles resistances and ~urge arresters a~ in FIG. 1 are not provided.
For the phantom feed of a subscriber terminal equipment ~not shown) connected via the subscriber line, the center tap 17 of the secondary winding of the transformer TlO i~ connected via the line 18 to a first terminal of a sa~ety fuse SilO. The second terminal thereof is connected to a te~minal l9 of a voltage source SVO This connection is connected to ground via a surge arrestor TslO that is a semiconductor circuit in this example.
The reception circuit E o~ the subscriber circuit i connected to the terminals 21 and 22 of the ~econdary winding of a transformer T20 of an interface circuit 20. Por protecting the reception circuit E, the~e terminals are connected to ground via Zener diodes ZD20, ZD21, respectively whose bre~kdown voltage lie above the peak voltage of th~ signal to be transmitted.
The terminals Z3 and 24 o the primary ~inding of the transformer T20 have lines 25, 26, r~spectively, connected to the output terminals Srl, Sr2, respectively. The two-wire ~ubscrib~r line in the reception direction ie connected to these output terminals Srl and Sr2. The lines 25 and 26 are connected to one anoth~r via diode circuits D20 and D21 that are connected in an 2 ~
antiparallel ~a~hion. The on~sta~e voltage of these diode circuit~
D20 and D21 lies abo~e the peak voltage o~ the ~ignal to be transmitted and limit6 the differential volt~ge at the primary winding of the trans~or~0r T20.
For completing the ~upply voltage path o~ the phantom ~eed o~
a subscxiber ter~inal ~quip~ent (IIOt ~hown) connected via the subscriber line, the center tap 27 of the ~econdary winding o~ th~
tra~s~ormer T20 i~ connectQd via a line 28 to a ~lrst terminal oP
a safety ~use Si20. The second terminal thereof i~ conne~ted to a terminal 29 of the voltage ~ource SV. Thi connection is connected to ground via a surge arrestor Ts20 that i5 a semiconductor circui~
in this example.
When, for example, an overvoltage occurs at the terminal Sxl, a leakage current arises via the conne~ting line 15, the transformer T10, the safety ~use SilO and the ~urge arrestor Tsi.
Whsn the voltage drop-off at the sub-winding betw2en the terminals 13 and 17 exceeds the on-state voltage of the diode circuits D10 or Dll, then a parti~l current also flows across ~he corresponding diode circuit and the ~ub-winding ~etween ~he terminals 14 and 17.
When this is a trenchant overvoltage, the safety fuse SilO does not interrupt this c~rrent path. ~he inter~ace cirsuit remainæ Pully functional aft2r the overvoltage.
When, for example, th overvoltages are caused by a contact with the 220 V ~ains voltage, the ~afety fuse interrupts this current path after a defined reæponse time. This occur~ before any permanent effect can occur, such as, fvr exampla, a destruction of the transformer T10. After the ~vervoltage, the interfac~ circuit is still ready for ~ignal txansmission. A phantom fe~d is no longer possible ~i.nce the safety fuse must be replacedO
The invention i8 not limi~ed to th~ particular details o~ the apparatus depictad and other ~odi:eications an~ applications are contemplated. Certain olther ::hanges may be made iLn the ~bove described apparatus withou1: departin~ from the true spirit and scope of the invention herein involved. It i6 intend~d, therefore, that the ~ubject matter in the above~ depiction ~hall be interpreted a~; illustrative and not in a limiting ~en~e.
Claims (11)
1. A circuit arrangement for protecting at least one interface circuit connected to two-wire subscriber lines against overvoltages occurring on the subscriber lines, the interface circuit having a transformer for signal infeed and/or signal outfeed whose center tap at a line side is at a DC voltage potential, comprising: a fuse element connecting the center tap of the transformer at the line side to the DC voltage potential; and a surge arrestor element connecting a connection between the fuse element and the DC voltage potential to ground.
2. The circuit arrangement according to claim 1, wherein a line-side winding of the transformer is configured such that leakage currents of trenchant overvoltages flow without permanent modification and wherein the fuse element interrupts a respective current path for any overvoltages that last longer than the trenchant overvoltages.
3. The circuit arrangement according to claim 2, wherein the fuse element is a metal-encapsulated safety fuse.
4. The circuit arrangement according to claim 1, wherein the circuit arrangement is for protecting a plurality of interface circuits and wherein a single surge arrestor element is employed in common for the plurality of interface circuits.
5. A circuit arrangement for protecting at least one interface circuit connected to two-wire subscriber lines against overvoltages occurring on the subscriber lines, the interface circuit having a transformer for signal infeed and/or signal outfeed whose center tap at a line side is at a DC voltage potential, comprising: a fuse element connecting the center tap of the transformer at the line side to the DC voltage potential; and a surge arrestor element connecting a connection between the fuse element and the DC voltage potential to ground; leakage currents of trenchant overvoltages flowing without permanent modification from the center tap to ground and the fuse element interrupting current flow for overvoltages that least longer than the trenchant overvoltages.
6. The circuit arrangement according to claim 5, wherein the fuse element is a metal-encapsulated safety fuse.
7. The circuit arrangement according to claim 5, wherein the circuit arrangement is for protecting a plurality of interface circuits and wherein a single surge arrestor element is employed in common for the plurality of interface circuits.
8. A circuit arrangement for protecting at least one interface circuit connected to two-wire subscriber lines against overvoltages occurring on the subscriber lines, comprising: the interface circuit having a transformer for signal infeed and/or single outfeed with a center tap at a line side that is at a DC
voltage potential; a fuse element connecting the center tap of the transformer at the line side to the DC voltage potential; and a surge arrestor element connecting a connection between the fuse element and the DC voltage potential to ground.
voltage potential; a fuse element connecting the center tap of the transformer at the line side to the DC voltage potential; and a surge arrestor element connecting a connection between the fuse element and the DC voltage potential to ground.
9. The circuit arrangement according to claim 8, wherein leakage currents of trenchant overvoltages flow without permanent modification from the center tap to ground and wherein the fuse element interrupts current flow for overvoltages that last longer than the trenchant overvoltages.
10. The circuit arrangement according to claim 9, wherein the fuse element is a metal-encapsulated safety fuse.
11. the circuit arrangement according to claim 8, wherein the circuit arrangement is for protecting a plurality of interface circuits and wherein a single surge arrestor element is employed in common for the plurality of interface circuits.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19914141074 DE4141074C1 (en) | 1991-12-13 | 1991-12-13 | |
| DEP4141074.2 | 1991-12-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2085189A1 true CA2085189A1 (en) | 1993-06-14 |
Family
ID=6446939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2085189 Abandoned CA2085189A1 (en) | 1991-12-13 | 1992-12-11 | Circuit arrangement for protecting interface circuits against overvoltages |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0546487A2 (en) |
| CA (1) | CA2085189A1 (en) |
| DE (1) | DE4141074C1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19725572A1 (en) * | 1997-06-17 | 1999-01-28 | Siemens Ag | Subscriber line termination circuit |
| CN100403617C (en) * | 2004-02-21 | 2008-07-16 | 华为技术有限公司 | Protection method of multiplexer network interface and communication equipment with multiplexer network interface |
| AT512819B1 (en) * | 2012-04-19 | 2015-03-15 | Kmt Kunststoff Metalltechnik Gmbh | Apparatus and method for injection molding a jacket of a component |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3334952A1 (en) * | 1983-09-27 | 1985-04-18 | Siemens AG, 1000 Berlin und 8000 München | CIRCUIT ARRANGEMENT FOR PROTECTING AN ELECTRONIC CIRCUIT CONNECTED TO THE FOURWIRE SIDE OF A TRANSMISSION FORK |
| GB2225908B (en) * | 1988-11-11 | 1993-01-13 | Texas Instruments Ltd | Improvements in or relating to overvoltage protection circuits |
-
1991
- 1991-12-13 DE DE19914141074 patent/DE4141074C1/de not_active Expired - Fee Related
-
1992
- 1992-12-07 EP EP92120831A patent/EP0546487A2/en not_active Withdrawn
- 1992-12-11 CA CA 2085189 patent/CA2085189A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP0546487A2 (en) | 1993-06-16 |
| DE4141074C1 (en) | 1993-06-03 |
| EP0546487A3 (en) | 1994-01-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |